1 #ifndef _ASM_X86_AMD_NB_H
2 #define _ASM_X86_AMD_NB_H
6 struct amd_nb_bus_dev_range {
12 extern const struct pci_device_id amd_nb_misc_ids[];
13 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
16 extern bool early_is_amd_nb(u32 value);
17 extern int amd_cache_northbridges(void);
18 extern void amd_flush_garts(void);
19 extern int amd_numa_init(void);
20 extern int amd_get_subcaches(int);
21 extern int amd_set_subcaches(int, int);
23 struct amd_northbridge {
28 struct amd_northbridge_info {
31 struct amd_northbridge *nb;
33 extern struct amd_northbridge_info amd_northbridges;
35 #define AMD_NB_GART BIT(0)
36 #define AMD_NB_L3_INDEX_DISABLE BIT(1)
37 #define AMD_NB_L3_PARTITIONING BIT(2)
41 static inline u16 amd_nb_num(void)
43 return amd_northbridges.num;
46 static inline bool amd_nb_has_feature(unsigned feature)
48 return ((amd_northbridges.flags & feature) == feature);
51 static inline struct amd_northbridge *node_to_amd_nb(int node)
53 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
58 #define amd_nb_num(x) 0
59 #define amd_nb_has_feature(x) false
60 #define node_to_amd_nb(x) NULL
65 #endif /* _ASM_X86_AMD_NB_H */