2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
33 #include <asm/stacktrace.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
42 #include <asm/unwind.h>
44 #include "perf_event.h"
46 struct x86_pmu x86_pmu __read_mostly;
48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
52 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
53 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
55 u64 __read_mostly hw_cache_event_ids
56 [PERF_COUNT_HW_CACHE_MAX]
57 [PERF_COUNT_HW_CACHE_OP_MAX]
58 [PERF_COUNT_HW_CACHE_RESULT_MAX];
59 u64 __read_mostly hw_cache_extra_regs
60 [PERF_COUNT_HW_CACHE_MAX]
61 [PERF_COUNT_HW_CACHE_OP_MAX]
62 [PERF_COUNT_HW_CACHE_RESULT_MAX];
65 * Propagate event elapsed time into the generic event.
66 * Can only be executed on the CPU where the event is active.
67 * Returns the delta events processed.
69 u64 x86_perf_event_update(struct perf_event *event)
71 struct hw_perf_event *hwc = &event->hw;
72 int shift = 64 - x86_pmu.cntval_bits;
73 u64 prev_raw_count, new_raw_count;
76 if (unlikely(!hwc->event_base))
79 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
80 return x86_pmu.update_topdown_event(event);
83 * Careful: an NMI might modify the previous event value.
85 * Our tactic to handle this is to first atomically read and
86 * exchange a new raw count - then add that new-prev delta
87 * count to the generic event atomically:
90 prev_raw_count = local64_read(&hwc->prev_count);
91 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
93 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
94 new_raw_count) != prev_raw_count)
98 * Now we have the new raw value and have updated the prev
99 * timestamp already. We can now calculate the elapsed delta
100 * (event-)time and add that to the generic event.
102 * Careful, not all hw sign-extends above the physical width
105 delta = (new_raw_count << shift) - (prev_raw_count << shift);
108 local64_add(delta, &event->count);
109 local64_sub(delta, &hwc->period_left);
111 return new_raw_count;
115 * Find and validate any extra registers to set up.
117 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
119 struct hw_perf_event_extra *reg;
120 struct extra_reg *er;
122 reg = &event->hw.extra_reg;
124 if (!x86_pmu.extra_regs)
127 for (er = x86_pmu.extra_regs; er->msr; er++) {
128 if (er->event != (config & er->config_mask))
130 if (event->attr.config1 & ~er->valid_mask)
132 /* Check if the extra msrs can be safely accessed*/
133 if (!er->extra_msr_access)
137 reg->config = event->attr.config1;
144 static atomic_t active_events;
145 static atomic_t pmc_refcount;
146 static DEFINE_MUTEX(pmc_reserve_mutex);
148 #ifdef CONFIG_X86_LOCAL_APIC
150 static bool reserve_pmc_hardware(void)
154 for (i = 0; i < x86_pmu.num_counters; i++) {
155 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
159 for (i = 0; i < x86_pmu.num_counters; i++) {
160 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
167 for (i--; i >= 0; i--)
168 release_evntsel_nmi(x86_pmu_config_addr(i));
170 i = x86_pmu.num_counters;
173 for (i--; i >= 0; i--)
174 release_perfctr_nmi(x86_pmu_event_addr(i));
179 static void release_pmc_hardware(void)
183 for (i = 0; i < x86_pmu.num_counters; i++) {
184 release_perfctr_nmi(x86_pmu_event_addr(i));
185 release_evntsel_nmi(x86_pmu_config_addr(i));
191 static bool reserve_pmc_hardware(void) { return true; }
192 static void release_pmc_hardware(void) {}
196 static bool check_hw_exists(void)
198 u64 val, val_fail = -1, val_new= ~0;
199 int i, reg, reg_fail = -1, ret = 0;
204 * Check to see if the BIOS enabled any of the counters, if so
207 for (i = 0; i < x86_pmu.num_counters; i++) {
208 reg = x86_pmu_config_addr(i);
209 ret = rdmsrl_safe(reg, &val);
212 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
221 if (x86_pmu.num_counters_fixed) {
222 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
223 ret = rdmsrl_safe(reg, &val);
226 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
227 if (val & (0x03 << i*4)) {
236 * If all the counters are enabled, the below test will always
237 * fail. The tools will also become useless in this scenario.
238 * Just fail and disable the hardware counters.
241 if (reg_safe == -1) {
247 * Read the current value, change it and read it back to see if it
248 * matches, this is needed to detect certain hardware emulators
249 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
251 reg = x86_pmu_event_addr(reg_safe);
252 if (rdmsrl_safe(reg, &val))
255 ret = wrmsrl_safe(reg, val);
256 ret |= rdmsrl_safe(reg, &val_new);
257 if (ret || val != val_new)
261 * We still allow the PMU driver to operate:
264 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
265 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
272 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
273 pr_cont("PMU not available due to virtualization, using software events only.\n");
275 pr_cont("Broken PMU hardware detected, using software events only.\n");
276 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
283 static void hw_perf_event_destroy(struct perf_event *event)
285 x86_release_hardware();
286 atomic_dec(&active_events);
289 void hw_perf_lbr_event_destroy(struct perf_event *event)
291 hw_perf_event_destroy(event);
293 /* undo the lbr/bts event accounting */
294 x86_del_exclusive(x86_lbr_exclusive_lbr);
297 static inline int x86_pmu_initialized(void)
299 return x86_pmu.handle_irq != NULL;
303 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
305 struct perf_event_attr *attr = &event->attr;
306 unsigned int cache_type, cache_op, cache_result;
309 config = attr->config;
311 cache_type = (config >> 0) & 0xff;
312 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
314 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
316 cache_op = (config >> 8) & 0xff;
317 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
319 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
321 cache_result = (config >> 16) & 0xff;
322 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
324 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
326 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
335 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
336 return x86_pmu_extra_regs(val, event);
339 int x86_reserve_hardware(void)
343 if (!atomic_inc_not_zero(&pmc_refcount)) {
344 mutex_lock(&pmc_reserve_mutex);
345 if (atomic_read(&pmc_refcount) == 0) {
346 if (!reserve_pmc_hardware())
349 reserve_ds_buffers();
352 atomic_inc(&pmc_refcount);
353 mutex_unlock(&pmc_reserve_mutex);
359 void x86_release_hardware(void)
361 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
362 release_pmc_hardware();
363 release_ds_buffers();
364 release_lbr_buffers();
365 mutex_unlock(&pmc_reserve_mutex);
370 * Check if we can create event of a certain type (that no conflicting events
373 int x86_add_exclusive(unsigned int what)
378 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
379 * LBR and BTS are still mutually exclusive.
381 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
384 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
385 mutex_lock(&pmc_reserve_mutex);
386 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
387 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
390 atomic_inc(&x86_pmu.lbr_exclusive[what]);
391 mutex_unlock(&pmc_reserve_mutex);
395 atomic_inc(&active_events);
399 mutex_unlock(&pmc_reserve_mutex);
403 void x86_del_exclusive(unsigned int what)
405 atomic_dec(&active_events);
408 * See the comment in x86_add_exclusive().
410 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
413 atomic_dec(&x86_pmu.lbr_exclusive[what]);
416 int x86_setup_perfctr(struct perf_event *event)
418 struct perf_event_attr *attr = &event->attr;
419 struct hw_perf_event *hwc = &event->hw;
422 if (!is_sampling_event(event)) {
423 hwc->sample_period = x86_pmu.max_period;
424 hwc->last_period = hwc->sample_period;
425 local64_set(&hwc->period_left, hwc->sample_period);
428 if (attr->type == PERF_TYPE_RAW)
429 return x86_pmu_extra_regs(event->attr.config, event);
431 if (attr->type == PERF_TYPE_HW_CACHE)
432 return set_ext_hw_attr(hwc, event);
434 if (attr->config >= x86_pmu.max_events)
437 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
442 config = x86_pmu.event_map(attr->config);
450 hwc->config |= config;
456 * check that branch_sample_type is compatible with
457 * settings needed for precise_ip > 1 which implies
458 * using the LBR to capture ALL taken branches at the
459 * priv levels of the measurement
461 static inline int precise_br_compat(struct perf_event *event)
463 u64 m = event->attr.branch_sample_type;
466 /* must capture all branches */
467 if (!(m & PERF_SAMPLE_BRANCH_ANY))
470 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
472 if (!event->attr.exclude_user)
473 b |= PERF_SAMPLE_BRANCH_USER;
475 if (!event->attr.exclude_kernel)
476 b |= PERF_SAMPLE_BRANCH_KERNEL;
479 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
485 int x86_pmu_max_precise(void)
489 /* Support for constant skid */
490 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
493 /* Support for IP fixup */
494 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
497 if (x86_pmu.pebs_prec_dist)
503 int x86_pmu_hw_config(struct perf_event *event)
505 if (event->attr.precise_ip) {
506 int precise = x86_pmu_max_precise();
508 if (event->attr.precise_ip > precise)
511 /* There's no sense in having PEBS for non sampling events: */
512 if (!is_sampling_event(event))
516 * check that PEBS LBR correction does not conflict with
517 * whatever the user is asking with attr->branch_sample_type
519 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
520 u64 *br_type = &event->attr.branch_sample_type;
522 if (has_branch_stack(event)) {
523 if (!precise_br_compat(event))
526 /* branch_sample_type is compatible */
530 * user did not specify branch_sample_type
532 * For PEBS fixups, we capture all
533 * the branches at the priv level of the
536 *br_type = PERF_SAMPLE_BRANCH_ANY;
538 if (!event->attr.exclude_user)
539 *br_type |= PERF_SAMPLE_BRANCH_USER;
541 if (!event->attr.exclude_kernel)
542 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
546 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
547 event->attach_state |= PERF_ATTACH_TASK_DATA;
551 * (keep 'enabled' bit clear for now)
553 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
556 * Count user and OS events unless requested not to
558 if (!event->attr.exclude_user)
559 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
560 if (!event->attr.exclude_kernel)
561 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
563 if (event->attr.type == PERF_TYPE_RAW)
564 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
566 if (event->attr.sample_period && x86_pmu.limit_period) {
567 if (x86_pmu.limit_period(event, event->attr.sample_period) >
568 event->attr.sample_period)
572 /* sample_regs_user never support XMM registers */
573 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
576 * Besides the general purpose registers, XMM registers may
577 * be collected in PEBS on some platforms, e.g. Icelake
579 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
580 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
583 if (!event->attr.precise_ip)
587 return x86_setup_perfctr(event);
591 * Setup the hardware configuration for a given attr_type
593 static int __x86_pmu_event_init(struct perf_event *event)
597 if (!x86_pmu_initialized())
600 err = x86_reserve_hardware();
604 atomic_inc(&active_events);
605 event->destroy = hw_perf_event_destroy;
608 event->hw.last_cpu = -1;
609 event->hw.last_tag = ~0ULL;
612 event->hw.extra_reg.idx = EXTRA_REG_NONE;
613 event->hw.branch_reg.idx = EXTRA_REG_NONE;
615 return x86_pmu.hw_config(event);
618 void x86_pmu_disable_all(void)
620 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
623 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
624 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
627 if (!test_bit(idx, cpuc->active_mask))
629 rdmsrl(x86_pmu_config_addr(idx), val);
630 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
632 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
633 wrmsrl(x86_pmu_config_addr(idx), val);
634 if (is_counter_pair(hwc))
635 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
640 * There may be PMI landing after enabled=0. The PMI hitting could be before or
643 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
644 * It will not be re-enabled in the NMI handler again, because enabled=0. After
645 * handling the NMI, disable_all will be called, which will not change the
646 * state either. If PMI hits after disable_all, the PMU is already disabled
647 * before entering NMI handler. The NMI handler will not change the state
650 * So either situation is harmless.
652 static void x86_pmu_disable(struct pmu *pmu)
654 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
656 if (!x86_pmu_initialized())
666 x86_pmu.disable_all();
669 void x86_pmu_enable_all(int added)
671 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
674 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
675 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
677 if (!test_bit(idx, cpuc->active_mask))
680 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
684 static struct pmu pmu;
686 static inline int is_x86_event(struct perf_event *event)
688 return event->pmu == &pmu;
691 struct pmu *x86_get_pmu(void)
696 * Event scheduler state:
698 * Assign events iterating over all events and counters, beginning
699 * with events with least weights first. Keep the current iterator
700 * state in struct sched_state.
704 int event; /* event index */
705 int counter; /* counter index */
706 int unassigned; /* number of events to be assigned left */
707 int nr_gp; /* number of GP counters used */
711 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
712 #define SCHED_STATES_MAX 2
719 struct event_constraint **constraints;
720 struct sched_state state;
721 struct sched_state saved[SCHED_STATES_MAX];
725 * Initialize interator that runs through all events and counters.
727 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
728 int num, int wmin, int wmax, int gpmax)
732 memset(sched, 0, sizeof(*sched));
733 sched->max_events = num;
734 sched->max_weight = wmax;
735 sched->max_gp = gpmax;
736 sched->constraints = constraints;
738 for (idx = 0; idx < num; idx++) {
739 if (constraints[idx]->weight == wmin)
743 sched->state.event = idx; /* start with min weight */
744 sched->state.weight = wmin;
745 sched->state.unassigned = num;
748 static void perf_sched_save_state(struct perf_sched *sched)
750 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
753 sched->saved[sched->saved_states] = sched->state;
754 sched->saved_states++;
757 static bool perf_sched_restore_state(struct perf_sched *sched)
759 if (!sched->saved_states)
762 sched->saved_states--;
763 sched->state = sched->saved[sched->saved_states];
765 /* this assignment didn't work out */
766 /* XXX broken vs EVENT_PAIR */
767 sched->state.used &= ~BIT_ULL(sched->state.counter);
769 /* try the next one */
770 sched->state.counter++;
776 * Select a counter for the current event to schedule. Return true on
779 static bool __perf_sched_find_counter(struct perf_sched *sched)
781 struct event_constraint *c;
784 if (!sched->state.unassigned)
787 if (sched->state.event >= sched->max_events)
790 c = sched->constraints[sched->state.event];
791 /* Prefer fixed purpose counters */
792 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
793 idx = INTEL_PMC_IDX_FIXED;
794 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
795 u64 mask = BIT_ULL(idx);
797 if (sched->state.used & mask)
800 sched->state.used |= mask;
805 /* Grab the first unused counter starting with idx */
806 idx = sched->state.counter;
807 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
808 u64 mask = BIT_ULL(idx);
810 if (c->flags & PERF_X86_EVENT_PAIR)
813 if (sched->state.used & mask)
816 if (sched->state.nr_gp++ >= sched->max_gp)
819 sched->state.used |= mask;
826 sched->state.counter = idx;
829 perf_sched_save_state(sched);
834 static bool perf_sched_find_counter(struct perf_sched *sched)
836 while (!__perf_sched_find_counter(sched)) {
837 if (!perf_sched_restore_state(sched))
845 * Go through all unassigned events and find the next one to schedule.
846 * Take events with the least weight first. Return true on success.
848 static bool perf_sched_next_event(struct perf_sched *sched)
850 struct event_constraint *c;
852 if (!sched->state.unassigned || !--sched->state.unassigned)
857 sched->state.event++;
858 if (sched->state.event >= sched->max_events) {
860 sched->state.event = 0;
861 sched->state.weight++;
862 if (sched->state.weight > sched->max_weight)
865 c = sched->constraints[sched->state.event];
866 } while (c->weight != sched->state.weight);
868 sched->state.counter = 0; /* start with first counter */
874 * Assign a counter for each event.
876 int perf_assign_events(struct event_constraint **constraints, int n,
877 int wmin, int wmax, int gpmax, int *assign)
879 struct perf_sched sched;
881 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
884 if (!perf_sched_find_counter(&sched))
887 assign[sched.state.event] = sched.state.counter;
888 } while (perf_sched_next_event(&sched));
890 return sched.state.unassigned;
892 EXPORT_SYMBOL_GPL(perf_assign_events);
894 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
896 struct event_constraint *c;
897 struct perf_event *e;
898 int n0, i, wmin, wmax, unsched = 0;
899 struct hw_perf_event *hwc;
903 * Compute the number of events already present; see x86_pmu_add(),
904 * validate_group() and x86_pmu_commit_txn(). For the former two
905 * cpuc->n_events hasn't been updated yet, while for the latter
906 * cpuc->n_txn contains the number of events added in the current
910 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
913 if (x86_pmu.start_scheduling)
914 x86_pmu.start_scheduling(cpuc);
916 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
917 c = cpuc->event_constraint[i];
920 * Previously scheduled events should have a cached constraint,
921 * while new events should not have one.
923 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
926 * Request constraints for new events; or for those events that
927 * have a dynamic constraint -- for those the constraint can
928 * change due to external factors (sibling state, allow_tfa).
930 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
931 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
932 cpuc->event_constraint[i] = c;
935 wmin = min(wmin, c->weight);
936 wmax = max(wmax, c->weight);
940 * fastpath, try to reuse previous register
942 for (i = 0; i < n; i++) {
945 hwc = &cpuc->event_list[i]->hw;
946 c = cpuc->event_constraint[i];
952 /* constraint still honored */
953 if (!test_bit(hwc->idx, c->idxmsk))
956 mask = BIT_ULL(hwc->idx);
957 if (is_counter_pair(hwc))
960 /* not already used */
961 if (used_mask & mask)
967 assign[i] = hwc->idx;
972 int gpmax = x86_pmu.num_counters;
975 * Do not allow scheduling of more than half the available
978 * This helps avoid counter starvation of sibling thread by
979 * ensuring at most half the counters cannot be in exclusive
980 * mode. There is no designated counters for the limits. Any
981 * N/2 counters can be used. This helps with events with
982 * specific counter constraints.
984 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
985 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
989 * Reduce the amount of available counters to allow fitting
990 * the extra Merge events needed by large increment events.
992 if (x86_pmu.flags & PMU_FL_PAIR) {
993 gpmax = x86_pmu.num_counters - cpuc->n_pair;
997 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
998 wmax, gpmax, assign);
1002 * In case of success (unsched = 0), mark events as committed,
1003 * so we do not put_constraint() in case new events are added
1004 * and fail to be scheduled
1006 * We invoke the lower level commit callback to lock the resource
1008 * We do not need to do all of this in case we are called to
1009 * validate an event group (assign == NULL)
1011 if (!unsched && assign) {
1012 for (i = 0; i < n; i++) {
1013 e = cpuc->event_list[i];
1014 if (x86_pmu.commit_scheduling)
1015 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
1018 for (i = n0; i < n; i++) {
1019 e = cpuc->event_list[i];
1022 * release events that failed scheduling
1024 if (x86_pmu.put_event_constraints)
1025 x86_pmu.put_event_constraints(cpuc, e);
1027 cpuc->event_constraint[i] = NULL;
1031 if (x86_pmu.stop_scheduling)
1032 x86_pmu.stop_scheduling(cpuc);
1034 return unsched ? -EINVAL : 0;
1037 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1038 struct perf_event *event)
1040 if (is_metric_event(event)) {
1041 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1044 cpuc->n_txn_metric++;
1050 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1051 struct perf_event *event)
1053 if (is_metric_event(event))
1057 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1058 int max_count, int n)
1061 if (x86_pmu.intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1064 if (n >= max_count + cpuc->n_metric)
1067 cpuc->event_list[n] = event;
1068 if (is_counter_pair(&event->hw)) {
1077 * dogrp: true if must collect siblings events (group)
1078 * returns total number of events and error code
1080 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1082 struct perf_event *event;
1085 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1087 /* current number of events already accepted */
1089 if (!cpuc->n_events)
1090 cpuc->pebs_output = 0;
1092 if (!cpuc->is_fake && leader->attr.precise_ip) {
1094 * For PEBS->PT, if !aux_event, the group leader (PT) went
1095 * away, the group was broken down and this singleton event
1096 * can't schedule any more.
1098 if (is_pebs_pt(leader) && !leader->aux_event)
1102 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1104 if (cpuc->pebs_output &&
1105 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1108 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1111 if (is_x86_event(leader)) {
1112 if (collect_event(cpuc, leader, max_count, n))
1120 for_each_sibling_event(event, leader) {
1121 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1124 if (collect_event(cpuc, event, max_count, n))
1132 static inline void x86_assign_hw_event(struct perf_event *event,
1133 struct cpu_hw_events *cpuc, int i)
1135 struct hw_perf_event *hwc = &event->hw;
1138 idx = hwc->idx = cpuc->assign[i];
1139 hwc->last_cpu = smp_processor_id();
1140 hwc->last_tag = ++cpuc->tags[i];
1143 case INTEL_PMC_IDX_FIXED_BTS:
1144 case INTEL_PMC_IDX_FIXED_VLBR:
1145 hwc->config_base = 0;
1146 hwc->event_base = 0;
1149 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1150 /* All the metric events are mapped onto the fixed counter 3. */
1151 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1153 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1154 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1155 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1156 (idx - INTEL_PMC_IDX_FIXED);
1157 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1158 INTEL_PMC_FIXED_RDPMC_BASE;
1162 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1163 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1164 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1170 * x86_perf_rdpmc_index - Return PMC counter used for event
1171 * @event: the perf_event to which the PMC counter was assigned
1173 * The counter assigned to this performance event may change if interrupts
1174 * are enabled. This counter should thus never be used while interrupts are
1175 * enabled. Before this function is used to obtain the assigned counter the
1176 * event should be checked for validity using, for example,
1177 * perf_event_read_local(), within the same interrupt disabled section in
1178 * which this counter is planned to be used.
1180 * Return: The index of the performance monitoring counter assigned to
1183 int x86_perf_rdpmc_index(struct perf_event *event)
1185 lockdep_assert_irqs_disabled();
1187 return event->hw.event_base_rdpmc;
1190 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1191 struct cpu_hw_events *cpuc,
1194 return hwc->idx == cpuc->assign[i] &&
1195 hwc->last_cpu == smp_processor_id() &&
1196 hwc->last_tag == cpuc->tags[i];
1199 static void x86_pmu_start(struct perf_event *event, int flags);
1201 static void x86_pmu_enable(struct pmu *pmu)
1203 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1204 struct perf_event *event;
1205 struct hw_perf_event *hwc;
1206 int i, added = cpuc->n_added;
1208 if (!x86_pmu_initialized())
1214 if (cpuc->n_added) {
1215 int n_running = cpuc->n_events - cpuc->n_added;
1217 * apply assignment obtained either from
1218 * hw_perf_group_sched_in() or x86_pmu_enable()
1220 * step1: save events moving to new counters
1222 for (i = 0; i < n_running; i++) {
1223 event = cpuc->event_list[i];
1227 * we can avoid reprogramming counter if:
1228 * - assigned same counter as last time
1229 * - running on same CPU as last time
1230 * - no other event has used the counter since
1232 if (hwc->idx == -1 ||
1233 match_prev_assignment(hwc, cpuc, i))
1237 * Ensure we don't accidentally enable a stopped
1238 * counter simply because we rescheduled.
1240 if (hwc->state & PERF_HES_STOPPED)
1241 hwc->state |= PERF_HES_ARCH;
1243 x86_pmu_stop(event, PERF_EF_UPDATE);
1247 * step2: reprogram moved events into new counters
1249 for (i = 0; i < cpuc->n_events; i++) {
1250 event = cpuc->event_list[i];
1253 if (!match_prev_assignment(hwc, cpuc, i))
1254 x86_assign_hw_event(event, cpuc, i);
1255 else if (i < n_running)
1258 if (hwc->state & PERF_HES_ARCH)
1261 x86_pmu_start(event, PERF_EF_RELOAD);
1264 perf_events_lapic_init();
1270 x86_pmu.enable_all(added);
1273 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1276 * Set the next IRQ period, based on the hwc->period_left value.
1277 * To be called with the event disabled in hw:
1279 int x86_perf_event_set_period(struct perf_event *event)
1281 struct hw_perf_event *hwc = &event->hw;
1282 s64 left = local64_read(&hwc->period_left);
1283 s64 period = hwc->sample_period;
1284 int ret = 0, idx = hwc->idx;
1286 if (unlikely(!hwc->event_base))
1289 if (unlikely(is_topdown_count(event)) &&
1290 x86_pmu.set_topdown_event_period)
1291 return x86_pmu.set_topdown_event_period(event);
1294 * If we are way outside a reasonable range then just skip forward:
1296 if (unlikely(left <= -period)) {
1298 local64_set(&hwc->period_left, left);
1299 hwc->last_period = period;
1303 if (unlikely(left <= 0)) {
1305 local64_set(&hwc->period_left, left);
1306 hwc->last_period = period;
1310 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1312 if (unlikely(left < 2))
1315 if (left > x86_pmu.max_period)
1316 left = x86_pmu.max_period;
1318 if (x86_pmu.limit_period)
1319 left = x86_pmu.limit_period(event, left);
1321 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1324 * The hw event starts counting from this event offset,
1325 * mark it to be able to extra future deltas:
1327 local64_set(&hwc->prev_count, (u64)-left);
1329 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1332 * Sign extend the Merge event counter's upper 16 bits since
1333 * we currently declare a 48-bit counter width
1335 if (is_counter_pair(hwc))
1336 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1339 * Due to erratum on certan cpu we need
1340 * a second write to be sure the register
1341 * is updated properly
1343 if (x86_pmu.perfctr_second_write) {
1344 wrmsrl(hwc->event_base,
1345 (u64)(-left) & x86_pmu.cntval_mask);
1348 perf_event_update_userpage(event);
1353 void x86_pmu_enable_event(struct perf_event *event)
1355 if (__this_cpu_read(cpu_hw_events.enabled))
1356 __x86_pmu_enable_event(&event->hw,
1357 ARCH_PERFMON_EVENTSEL_ENABLE);
1361 * Add a single event to the PMU.
1363 * The event is added to the group of enabled events
1364 * but only if it can be scheduled with existing events.
1366 static int x86_pmu_add(struct perf_event *event, int flags)
1368 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1369 struct hw_perf_event *hwc;
1370 int assign[X86_PMC_IDX_MAX];
1375 n0 = cpuc->n_events;
1376 ret = n = collect_events(cpuc, event, false);
1380 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1381 if (!(flags & PERF_EF_START))
1382 hwc->state |= PERF_HES_ARCH;
1385 * If group events scheduling transaction was started,
1386 * skip the schedulability test here, it will be performed
1387 * at commit time (->commit_txn) as a whole.
1389 * If commit fails, we'll call ->del() on all events
1390 * for which ->add() was called.
1392 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1395 ret = x86_pmu.schedule_events(cpuc, n, assign);
1399 * copy new assignment, now we know it is possible
1400 * will be used by hw_perf_enable()
1402 memcpy(cpuc->assign, assign, n*sizeof(int));
1406 * Commit the collect_events() state. See x86_pmu_del() and
1410 cpuc->n_added += n - n0;
1411 cpuc->n_txn += n - n0;
1415 * This is before x86_pmu_enable() will call x86_pmu_start(),
1416 * so we enable LBRs before an event needs them etc..
1426 static void x86_pmu_start(struct perf_event *event, int flags)
1428 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1429 int idx = event->hw.idx;
1431 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1434 if (WARN_ON_ONCE(idx == -1))
1437 if (flags & PERF_EF_RELOAD) {
1438 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1439 x86_perf_event_set_period(event);
1442 event->hw.state = 0;
1444 cpuc->events[idx] = event;
1445 __set_bit(idx, cpuc->active_mask);
1446 __set_bit(idx, cpuc->running);
1447 x86_pmu.enable(event);
1448 perf_event_update_userpage(event);
1451 void perf_event_print_debug(void)
1453 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1455 struct cpu_hw_events *cpuc;
1456 unsigned long flags;
1459 if (!x86_pmu.num_counters)
1462 local_irq_save(flags);
1464 cpu = smp_processor_id();
1465 cpuc = &per_cpu(cpu_hw_events, cpu);
1467 if (x86_pmu.version >= 2) {
1468 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1469 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1470 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1471 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1474 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1475 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1476 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1477 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1478 if (x86_pmu.pebs_constraints) {
1479 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1480 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1482 if (x86_pmu.lbr_nr) {
1483 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1484 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1487 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1489 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1490 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1491 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1493 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1495 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1496 cpu, idx, pmc_ctrl);
1497 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1498 cpu, idx, pmc_count);
1499 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1500 cpu, idx, prev_left);
1502 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1503 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1505 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1506 cpu, idx, pmc_count);
1508 local_irq_restore(flags);
1511 void x86_pmu_stop(struct perf_event *event, int flags)
1513 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1514 struct hw_perf_event *hwc = &event->hw;
1516 if (test_bit(hwc->idx, cpuc->active_mask)) {
1517 x86_pmu.disable(event);
1518 __clear_bit(hwc->idx, cpuc->active_mask);
1519 cpuc->events[hwc->idx] = NULL;
1520 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1521 hwc->state |= PERF_HES_STOPPED;
1524 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1526 * Drain the remaining delta count out of a event
1527 * that we are disabling:
1529 x86_perf_event_update(event);
1530 hwc->state |= PERF_HES_UPTODATE;
1534 static void x86_pmu_del(struct perf_event *event, int flags)
1536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1540 * If we're called during a txn, we only need to undo x86_pmu.add.
1541 * The events never got scheduled and ->cancel_txn will truncate
1544 * XXX assumes any ->del() called during a TXN will only be on
1545 * an event added during that same TXN.
1547 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1551 * Not a TXN, therefore cleanup properly.
1553 x86_pmu_stop(event, PERF_EF_UPDATE);
1555 for (i = 0; i < cpuc->n_events; i++) {
1556 if (event == cpuc->event_list[i])
1560 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1563 /* If we have a newly added event; make sure to decrease n_added. */
1564 if (i >= cpuc->n_events - cpuc->n_added)
1567 if (x86_pmu.put_event_constraints)
1568 x86_pmu.put_event_constraints(cpuc, event);
1570 /* Delete the array entry. */
1571 while (++i < cpuc->n_events) {
1572 cpuc->event_list[i-1] = cpuc->event_list[i];
1573 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1575 cpuc->event_constraint[i-1] = NULL;
1577 if (x86_pmu.intel_cap.perf_metrics)
1578 del_nr_metric_event(cpuc, event);
1580 perf_event_update_userpage(event);
1585 * This is after x86_pmu_stop(); so we disable LBRs after any
1586 * event can need them etc..
1592 int x86_pmu_handle_irq(struct pt_regs *regs)
1594 struct perf_sample_data data;
1595 struct cpu_hw_events *cpuc;
1596 struct perf_event *event;
1597 int idx, handled = 0;
1600 cpuc = this_cpu_ptr(&cpu_hw_events);
1603 * Some chipsets need to unmask the LVTPC in a particular spot
1604 * inside the nmi handler. As a result, the unmasking was pushed
1605 * into all the nmi handlers.
1607 * This generic handler doesn't seem to have any issues where the
1608 * unmasking occurs so it was left at the top.
1610 apic_write(APIC_LVTPC, APIC_DM_NMI);
1612 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1613 if (!test_bit(idx, cpuc->active_mask))
1616 event = cpuc->events[idx];
1618 val = x86_perf_event_update(event);
1619 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1626 perf_sample_data_init(&data, 0, event->hw.last_period);
1628 if (!x86_perf_event_set_period(event))
1631 if (perf_event_overflow(event, &data, regs))
1632 x86_pmu_stop(event, 0);
1636 inc_irq_stat(apic_perf_irqs);
1641 void perf_events_lapic_init(void)
1643 if (!x86_pmu.apic || !x86_pmu_initialized())
1647 * Always use NMI for PMU
1649 apic_write(APIC_LVTPC, APIC_DM_NMI);
1653 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1660 * All PMUs/events that share this PMI handler should make sure to
1661 * increment active_events for their events.
1663 if (!atomic_read(&active_events))
1666 start_clock = sched_clock();
1667 ret = x86_pmu.handle_irq(regs);
1668 finish_clock = sched_clock();
1670 perf_sample_event_took(finish_clock - start_clock);
1674 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1676 struct event_constraint emptyconstraint;
1677 struct event_constraint unconstrained;
1679 static int x86_pmu_prepare_cpu(unsigned int cpu)
1681 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1684 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1685 cpuc->kfree_on_online[i] = NULL;
1686 if (x86_pmu.cpu_prepare)
1687 return x86_pmu.cpu_prepare(cpu);
1691 static int x86_pmu_dead_cpu(unsigned int cpu)
1693 if (x86_pmu.cpu_dead)
1694 x86_pmu.cpu_dead(cpu);
1698 static int x86_pmu_online_cpu(unsigned int cpu)
1700 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1703 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1704 kfree(cpuc->kfree_on_online[i]);
1705 cpuc->kfree_on_online[i] = NULL;
1710 static int x86_pmu_starting_cpu(unsigned int cpu)
1712 if (x86_pmu.cpu_starting)
1713 x86_pmu.cpu_starting(cpu);
1717 static int x86_pmu_dying_cpu(unsigned int cpu)
1719 if (x86_pmu.cpu_dying)
1720 x86_pmu.cpu_dying(cpu);
1724 static void __init pmu_check_apic(void)
1726 if (boot_cpu_has(X86_FEATURE_APIC))
1730 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1731 pr_info("no hardware sampling interrupt available.\n");
1734 * If we have a PMU initialized but no APIC
1735 * interrupts, we cannot sample hardware
1736 * events (user-space has to fall back and
1737 * sample via a hrtimer based software event):
1739 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1743 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1748 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1750 struct perf_pmu_events_attr *pmu_attr =
1751 container_of(attr, struct perf_pmu_events_attr, attr);
1754 if (pmu_attr->id < x86_pmu.max_events)
1755 config = x86_pmu.event_map(pmu_attr->id);
1757 /* string trumps id */
1758 if (pmu_attr->event_str)
1759 return sprintf(page, "%s", pmu_attr->event_str);
1761 return x86_pmu.events_sysfs_show(page, config);
1763 EXPORT_SYMBOL_GPL(events_sysfs_show);
1765 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1768 struct perf_pmu_events_ht_attr *pmu_attr =
1769 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1772 * Report conditional events depending on Hyper-Threading.
1774 * This is overly conservative as usually the HT special
1775 * handling is not needed if the other CPU thread is idle.
1777 * Note this does not (and cannot) handle the case when thread
1778 * siblings are invisible, for example with virtualization
1779 * if they are owned by some other guest. The user tool
1780 * has to re-read when a thread sibling gets onlined later.
1782 return sprintf(page, "%s",
1783 topology_max_smt_threads() > 1 ?
1784 pmu_attr->event_str_ht :
1785 pmu_attr->event_str_noht);
1788 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1789 EVENT_ATTR(instructions, INSTRUCTIONS );
1790 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1791 EVENT_ATTR(cache-misses, CACHE_MISSES );
1792 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1793 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1794 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1795 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1796 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1797 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1799 static struct attribute *empty_attrs;
1801 static struct attribute *events_attr[] = {
1802 EVENT_PTR(CPU_CYCLES),
1803 EVENT_PTR(INSTRUCTIONS),
1804 EVENT_PTR(CACHE_REFERENCES),
1805 EVENT_PTR(CACHE_MISSES),
1806 EVENT_PTR(BRANCH_INSTRUCTIONS),
1807 EVENT_PTR(BRANCH_MISSES),
1808 EVENT_PTR(BUS_CYCLES),
1809 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1810 EVENT_PTR(STALLED_CYCLES_BACKEND),
1811 EVENT_PTR(REF_CPU_CYCLES),
1816 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1817 * out of events_attr attributes.
1820 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1822 struct perf_pmu_events_attr *pmu_attr;
1824 if (idx >= x86_pmu.max_events)
1827 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1829 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1832 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1834 .attrs = events_attr,
1835 .is_visible = is_visible,
1838 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1840 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1841 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1842 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1843 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1844 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1845 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1849 * We have whole page size to spend and just little data
1850 * to write, so we can safely use sprintf.
1852 ret = sprintf(page, "event=0x%02llx", event);
1855 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1858 ret += sprintf(page + ret, ",edge");
1861 ret += sprintf(page + ret, ",pc");
1864 ret += sprintf(page + ret, ",any");
1867 ret += sprintf(page + ret, ",inv");
1870 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1872 ret += sprintf(page + ret, "\n");
1877 static struct attribute_group x86_pmu_attr_group;
1878 static struct attribute_group x86_pmu_caps_group;
1880 static int __init init_hw_perf_events(void)
1882 struct x86_pmu_quirk *quirk;
1885 pr_info("Performance Events: ");
1887 switch (boot_cpu_data.x86_vendor) {
1888 case X86_VENDOR_INTEL:
1889 err = intel_pmu_init();
1891 case X86_VENDOR_AMD:
1892 err = amd_pmu_init();
1894 case X86_VENDOR_HYGON:
1895 err = amd_pmu_init();
1896 x86_pmu.name = "HYGON";
1898 case X86_VENDOR_ZHAOXIN:
1899 case X86_VENDOR_CENTAUR:
1900 err = zhaoxin_pmu_init();
1906 pr_cont("no PMU driver, software events only.\n");
1912 /* sanity check that the hardware exists or is emulated */
1913 if (!check_hw_exists())
1916 pr_cont("%s PMU driver.\n", x86_pmu.name);
1918 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1920 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1923 if (!x86_pmu.intel_ctrl)
1924 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1926 perf_events_lapic_init();
1927 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1929 unconstrained = (struct event_constraint)
1930 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1931 0, x86_pmu.num_counters, 0, 0);
1933 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1935 if (!x86_pmu.events_sysfs_show)
1936 x86_pmu_events_group.attrs = &empty_attrs;
1938 pmu.attr_update = x86_pmu.attr_update;
1940 pr_info("... version: %d\n", x86_pmu.version);
1941 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1942 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1943 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1944 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1945 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1946 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1949 * Install callbacks. Core will call them for each online
1952 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1953 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1957 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1958 "perf/x86:starting", x86_pmu_starting_cpu,
1963 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1964 x86_pmu_online_cpu, NULL);
1968 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1975 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1977 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1979 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1982 early_initcall(init_hw_perf_events);
1984 static inline void x86_pmu_read(struct perf_event *event)
1987 return x86_pmu.read(event);
1988 x86_perf_event_update(event);
1992 * Start group events scheduling transaction
1993 * Set the flag to make pmu::enable() not perform the
1994 * schedulability test, it will be performed at commit time
1996 * We only support PERF_PMU_TXN_ADD transactions. Save the
1997 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2000 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2002 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2004 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2006 cpuc->txn_flags = txn_flags;
2007 if (txn_flags & ~PERF_PMU_TXN_ADD)
2010 perf_pmu_disable(pmu);
2011 __this_cpu_write(cpu_hw_events.n_txn, 0);
2012 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2013 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2017 * Stop group events scheduling transaction
2018 * Clear the flag and pmu::enable() will perform the
2019 * schedulability test.
2021 static void x86_pmu_cancel_txn(struct pmu *pmu)
2023 unsigned int txn_flags;
2024 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2026 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2028 txn_flags = cpuc->txn_flags;
2029 cpuc->txn_flags = 0;
2030 if (txn_flags & ~PERF_PMU_TXN_ADD)
2034 * Truncate collected array by the number of events added in this
2035 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2037 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2038 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2039 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2040 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2041 perf_pmu_enable(pmu);
2045 * Commit group events scheduling transaction
2046 * Perform the group schedulability test as a whole
2047 * Return 0 if success
2049 * Does not cancel the transaction on failure; expects the caller to do this.
2051 static int x86_pmu_commit_txn(struct pmu *pmu)
2053 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2054 int assign[X86_PMC_IDX_MAX];
2057 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2059 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2060 cpuc->txn_flags = 0;
2066 if (!x86_pmu_initialized())
2069 ret = x86_pmu.schedule_events(cpuc, n, assign);
2074 * copy new assignment, now we know it is possible
2075 * will be used by hw_perf_enable()
2077 memcpy(cpuc->assign, assign, n*sizeof(int));
2079 cpuc->txn_flags = 0;
2080 perf_pmu_enable(pmu);
2084 * a fake_cpuc is used to validate event groups. Due to
2085 * the extra reg logic, we need to also allocate a fake
2086 * per_core and per_cpu structure. Otherwise, group events
2087 * using extra reg may conflict without the kernel being
2088 * able to catch this when the last event gets added to
2091 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2093 intel_cpuc_finish(cpuc);
2097 static struct cpu_hw_events *allocate_fake_cpuc(void)
2099 struct cpu_hw_events *cpuc;
2100 int cpu = raw_smp_processor_id();
2102 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2104 return ERR_PTR(-ENOMEM);
2107 if (intel_cpuc_prepare(cpuc, cpu))
2112 free_fake_cpuc(cpuc);
2113 return ERR_PTR(-ENOMEM);
2117 * validate that we can schedule this event
2119 static int validate_event(struct perf_event *event)
2121 struct cpu_hw_events *fake_cpuc;
2122 struct event_constraint *c;
2125 fake_cpuc = allocate_fake_cpuc();
2126 if (IS_ERR(fake_cpuc))
2127 return PTR_ERR(fake_cpuc);
2129 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2131 if (!c || !c->weight)
2134 if (x86_pmu.put_event_constraints)
2135 x86_pmu.put_event_constraints(fake_cpuc, event);
2137 free_fake_cpuc(fake_cpuc);
2143 * validate a single event group
2145 * validation include:
2146 * - check events are compatible which each other
2147 * - events do not compete for the same counter
2148 * - number of events <= number of counters
2150 * validation ensures the group can be loaded onto the
2151 * PMU if it was the only group available.
2153 static int validate_group(struct perf_event *event)
2155 struct perf_event *leader = event->group_leader;
2156 struct cpu_hw_events *fake_cpuc;
2157 int ret = -EINVAL, n;
2159 fake_cpuc = allocate_fake_cpuc();
2160 if (IS_ERR(fake_cpuc))
2161 return PTR_ERR(fake_cpuc);
2163 * the event is not yet connected with its
2164 * siblings therefore we must first collect
2165 * existing siblings, then add the new event
2166 * before we can simulate the scheduling
2168 n = collect_events(fake_cpuc, leader, true);
2172 fake_cpuc->n_events = n;
2173 n = collect_events(fake_cpuc, event, false);
2177 fake_cpuc->n_events = 0;
2178 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2181 free_fake_cpuc(fake_cpuc);
2185 static int x86_pmu_event_init(struct perf_event *event)
2190 switch (event->attr.type) {
2192 case PERF_TYPE_HARDWARE:
2193 case PERF_TYPE_HW_CACHE:
2200 err = __x86_pmu_event_init(event);
2203 * we temporarily connect event to its pmu
2204 * such that validate_group() can classify
2205 * it as an x86 event using is_x86_event()
2210 if (event->group_leader != event)
2211 err = validate_group(event);
2213 err = validate_event(event);
2219 event->destroy(event);
2222 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2223 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2224 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2229 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2231 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2235 * This function relies on not being called concurrently in two
2236 * tasks in the same mm. Otherwise one task could observe
2237 * perf_rdpmc_allowed > 1 and return all the way back to
2238 * userspace with CR4.PCE clear while another task is still
2239 * doing on_each_cpu_mask() to propagate CR4.PCE.
2241 * For now, this can't happen because all callers hold mmap_lock
2242 * for write. If this changes, we'll need a different solution.
2244 mmap_assert_write_locked(mm);
2246 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2247 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2250 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2253 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2256 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2257 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2260 static int x86_pmu_event_idx(struct perf_event *event)
2262 struct hw_perf_event *hwc = &event->hw;
2264 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2267 if (is_metric_idx(hwc->idx))
2268 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2270 return hwc->event_base_rdpmc + 1;
2273 static ssize_t get_attr_rdpmc(struct device *cdev,
2274 struct device_attribute *attr,
2277 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2280 static ssize_t set_attr_rdpmc(struct device *cdev,
2281 struct device_attribute *attr,
2282 const char *buf, size_t count)
2287 ret = kstrtoul(buf, 0, &val);
2294 if (x86_pmu.attr_rdpmc_broken)
2297 if (val != x86_pmu.attr_rdpmc) {
2299 * Changing into or out of never available or always available,
2300 * aka perf-event-bypassing mode. This path is extremely slow,
2301 * but only root can trigger it, so it's okay.
2304 static_branch_inc(&rdpmc_never_available_key);
2305 else if (x86_pmu.attr_rdpmc == 0)
2306 static_branch_dec(&rdpmc_never_available_key);
2309 static_branch_inc(&rdpmc_always_available_key);
2310 else if (x86_pmu.attr_rdpmc == 2)
2311 static_branch_dec(&rdpmc_always_available_key);
2313 on_each_cpu(cr4_update_pce, NULL, 1);
2314 x86_pmu.attr_rdpmc = val;
2320 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2322 static struct attribute *x86_pmu_attrs[] = {
2323 &dev_attr_rdpmc.attr,
2327 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2328 .attrs = x86_pmu_attrs,
2331 static ssize_t max_precise_show(struct device *cdev,
2332 struct device_attribute *attr,
2335 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2338 static DEVICE_ATTR_RO(max_precise);
2340 static struct attribute *x86_pmu_caps_attrs[] = {
2341 &dev_attr_max_precise.attr,
2345 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2347 .attrs = x86_pmu_caps_attrs,
2350 static const struct attribute_group *x86_pmu_attr_groups[] = {
2351 &x86_pmu_attr_group,
2352 &x86_pmu_format_group,
2353 &x86_pmu_events_group,
2354 &x86_pmu_caps_group,
2358 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2360 if (x86_pmu.sched_task)
2361 x86_pmu.sched_task(ctx, sched_in);
2364 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2365 struct perf_event_context *next)
2367 if (x86_pmu.swap_task_ctx)
2368 x86_pmu.swap_task_ctx(prev, next);
2371 void perf_check_microcode(void)
2373 if (x86_pmu.check_microcode)
2374 x86_pmu.check_microcode();
2377 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2379 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2382 if (value && x86_pmu.limit_period) {
2383 if (x86_pmu.limit_period(event, value) > value)
2390 static int x86_pmu_aux_output_match(struct perf_event *event)
2392 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2395 if (x86_pmu.aux_output_match)
2396 return x86_pmu.aux_output_match(event);
2401 static struct pmu pmu = {
2402 .pmu_enable = x86_pmu_enable,
2403 .pmu_disable = x86_pmu_disable,
2405 .attr_groups = x86_pmu_attr_groups,
2407 .event_init = x86_pmu_event_init,
2409 .event_mapped = x86_pmu_event_mapped,
2410 .event_unmapped = x86_pmu_event_unmapped,
2414 .start = x86_pmu_start,
2415 .stop = x86_pmu_stop,
2416 .read = x86_pmu_read,
2418 .start_txn = x86_pmu_start_txn,
2419 .cancel_txn = x86_pmu_cancel_txn,
2420 .commit_txn = x86_pmu_commit_txn,
2422 .event_idx = x86_pmu_event_idx,
2423 .sched_task = x86_pmu_sched_task,
2424 .swap_task_ctx = x86_pmu_swap_task_ctx,
2425 .check_period = x86_pmu_check_period,
2427 .aux_output_match = x86_pmu_aux_output_match,
2430 void arch_perf_update_userpage(struct perf_event *event,
2431 struct perf_event_mmap_page *userpg, u64 now)
2433 struct cyc2ns_data data;
2436 userpg->cap_user_time = 0;
2437 userpg->cap_user_time_zero = 0;
2438 userpg->cap_user_rdpmc =
2439 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2440 userpg->pmc_width = x86_pmu.cntval_bits;
2442 if (!using_native_sched_clock() || !sched_clock_stable())
2445 cyc2ns_read_begin(&data);
2447 offset = data.cyc2ns_offset + __sched_clock_offset;
2450 * Internal timekeeping for enabled/running/stopped times
2451 * is always in the local_clock domain.
2453 userpg->cap_user_time = 1;
2454 userpg->time_mult = data.cyc2ns_mul;
2455 userpg->time_shift = data.cyc2ns_shift;
2456 userpg->time_offset = offset - now;
2459 * cap_user_time_zero doesn't make sense when we're using a different
2460 * time base for the records.
2462 if (!event->attr.use_clockid) {
2463 userpg->cap_user_time_zero = 1;
2464 userpg->time_zero = offset;
2471 * Determine whether the regs were taken from an irq/exception handler rather
2472 * than from perf_arch_fetch_caller_regs().
2474 static bool perf_hw_regs(struct pt_regs *regs)
2476 return regs->flags & X86_EFLAGS_FIXED;
2480 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2482 struct unwind_state state;
2485 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2486 /* TODO: We don't support guest os callchain now */
2490 if (perf_callchain_store(entry, regs->ip))
2493 if (perf_hw_regs(regs))
2494 unwind_start(&state, current, regs, NULL);
2496 unwind_start(&state, current, NULL, (void *)regs->sp);
2498 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2499 addr = unwind_get_return_address(&state);
2500 if (!addr || perf_callchain_store(entry, addr))
2506 valid_user_frame(const void __user *fp, unsigned long size)
2508 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2511 static unsigned long get_segment_base(unsigned int segment)
2513 struct desc_struct *desc;
2514 unsigned int idx = segment >> 3;
2516 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2517 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2518 struct ldt_struct *ldt;
2520 /* IRQs are off, so this synchronizes with smp_store_release */
2521 ldt = READ_ONCE(current->active_mm->context.ldt);
2522 if (!ldt || idx >= ldt->nr_entries)
2525 desc = &ldt->entries[idx];
2530 if (idx >= GDT_ENTRIES)
2533 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2536 return get_desc_base(desc);
2539 #ifdef CONFIG_IA32_EMULATION
2541 #include <linux/compat.h>
2544 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2546 /* 32-bit process in 64-bit kernel. */
2547 unsigned long ss_base, cs_base;
2548 struct stack_frame_ia32 frame;
2549 const struct stack_frame_ia32 __user *fp;
2551 if (!test_thread_flag(TIF_IA32))
2554 cs_base = get_segment_base(regs->cs);
2555 ss_base = get_segment_base(regs->ss);
2557 fp = compat_ptr(ss_base + regs->bp);
2558 pagefault_disable();
2559 while (entry->nr < entry->max_stack) {
2560 if (!valid_user_frame(fp, sizeof(frame)))
2563 if (__get_user(frame.next_frame, &fp->next_frame))
2565 if (__get_user(frame.return_address, &fp->return_address))
2568 perf_callchain_store(entry, cs_base + frame.return_address);
2569 fp = compat_ptr(ss_base + frame.next_frame);
2576 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2583 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2585 struct stack_frame frame;
2586 const struct stack_frame __user *fp;
2588 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2589 /* TODO: We don't support guest os callchain now */
2594 * We don't know what to do with VM86 stacks.. ignore them for now.
2596 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2599 fp = (void __user *)regs->bp;
2601 perf_callchain_store(entry, regs->ip);
2603 if (!nmi_uaccess_okay())
2606 if (perf_callchain_user32(regs, entry))
2609 pagefault_disable();
2610 while (entry->nr < entry->max_stack) {
2611 if (!valid_user_frame(fp, sizeof(frame)))
2614 if (__get_user(frame.next_frame, &fp->next_frame))
2616 if (__get_user(frame.return_address, &fp->return_address))
2619 perf_callchain_store(entry, frame.return_address);
2620 fp = (void __user *)frame.next_frame;
2626 * Deal with code segment offsets for the various execution modes:
2628 * VM86 - the good olde 16 bit days, where the linear address is
2629 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2631 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2632 * to figure out what the 32bit base address is.
2634 * X32 - has TIF_X32 set, but is running in x86_64
2636 * X86_64 - CS,DS,SS,ES are all zero based.
2638 static unsigned long code_segment_base(struct pt_regs *regs)
2641 * For IA32 we look at the GDT/LDT segment base to convert the
2642 * effective IP to a linear address.
2645 #ifdef CONFIG_X86_32
2647 * If we are in VM86 mode, add the segment offset to convert to a
2650 if (regs->flags & X86_VM_MASK)
2651 return 0x10 * regs->cs;
2653 if (user_mode(regs) && regs->cs != __USER_CS)
2654 return get_segment_base(regs->cs);
2656 if (user_mode(regs) && !user_64bit_mode(regs) &&
2657 regs->cs != __USER32_CS)
2658 return get_segment_base(regs->cs);
2663 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2665 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2666 return perf_guest_cbs->get_guest_ip();
2668 return regs->ip + code_segment_base(regs);
2671 unsigned long perf_misc_flags(struct pt_regs *regs)
2675 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2676 if (perf_guest_cbs->is_user_mode())
2677 misc |= PERF_RECORD_MISC_GUEST_USER;
2679 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2681 if (user_mode(regs))
2682 misc |= PERF_RECORD_MISC_USER;
2684 misc |= PERF_RECORD_MISC_KERNEL;
2687 if (regs->flags & PERF_EFLAGS_EXACT)
2688 misc |= PERF_RECORD_MISC_EXACT_IP;
2693 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2695 cap->version = x86_pmu.version;
2696 cap->num_counters_gp = x86_pmu.num_counters;
2697 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2698 cap->bit_width_gp = x86_pmu.cntval_bits;
2699 cap->bit_width_fixed = x86_pmu.cntval_bits;
2700 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2701 cap->events_mask_len = x86_pmu.events_mask_len;
2703 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);