arch/x86/events/core.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/export.h>
  21 #include <linux/init.h>
  22 #include <linux/kdebug.h>
  23 #include <linux/sched/mm.h>
  24 #include <linux/sched/clock.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/slab.h>
  27 #include <linux/cpu.h>
  28 #include <linux/bitops.h>
  29 #include <linux/device.h>
  30 #include <linux/nospec.h>
  31
  32 #include <asm/apic.h>
  33 #include <asm/stacktrace.h>
  34 #include <asm/nmi.h>
  35 #include <asm/smp.h>
  36 #include <asm/alternative.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/tlbflush.h>
  39 #include <asm/timer.h>
  40 #include <asm/desc.h>
  41 #include <asm/ldt.h>
  42 #include <asm/unwind.h>
  43
  44 #include "perf_event.h"
  45
  46 struct x86_pmu x86_pmu __read_mostly;
  47
  48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  49         .enabled = 1,
  50 };
  51
  52 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
  53 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
  54
  55 u64 __read_mostly hw_cache_event_ids
  56                                 [PERF_COUNT_HW_CACHE_MAX]
  57                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  58                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  59 u64 __read_mostly hw_cache_extra_regs
  60                                 [PERF_COUNT_HW_CACHE_MAX]
  61                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  62                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  63
  64 /*
  65  * Propagate event elapsed time into the generic event.
  66  * Can only be executed on the CPU where the event is active.
  67  * Returns the delta events processed.
  68  */
  69 u64 x86_perf_event_update(struct perf_event *event)
  70 {
  71         struct hw_perf_event *hwc = &event->hw;
  72         int shift = 64 - x86_pmu.cntval_bits;
  73         u64 prev_raw_count, new_raw_count;
  74         u64 delta;
  75
  76         if (unlikely(!hwc->event_base))
  77                 return 0;
  78
  79         if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
  80                 return x86_pmu.update_topdown_event(event);
  81
  82         /*
  83          * Careful: an NMI might modify the previous event value.
  84          *
  85          * Our tactic to handle this is to first atomically read and
  86          * exchange a new raw count - then add that new-prev delta
  87          * count to the generic event atomically:
  88          */
  89 again:
  90         prev_raw_count = local64_read(&hwc->prev_count);
  91         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  92
  93         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  94                                         new_raw_count) != prev_raw_count)
  95                 goto again;
  96
  97         /*
  98          * Now we have the new raw value and have updated the prev
  99          * timestamp already. We can now calculate the elapsed delta
 100          * (event-)time and add that to the generic event.
 101          *
 102          * Careful, not all hw sign-extends above the physical width
 103          * of the count.
 104          */
 105         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 106         delta >>= shift;
 107
 108         local64_add(delta, &event->count);
 109         local64_sub(delta, &hwc->period_left);
 110
 111         return new_raw_count;
 112 }
 113
 114 /*
 115  * Find and validate any extra registers to set up.
 116  */
 117 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 118 {
 119         struct hw_perf_event_extra *reg;
 120         struct extra_reg *er;
 121
 122         reg = &event->hw.extra_reg;
 123
 124         if (!x86_pmu.extra_regs)
 125                 return 0;
 126
 127         for (er = x86_pmu.extra_regs; er->msr; er++) {
 128                 if (er->event != (config & er->config_mask))
 129                         continue;
 130                 if (event->attr.config1 & ~er->valid_mask)
 131                         return -EINVAL;
 132                 /* Check if the extra msrs can be safely accessed*/
 133                 if (!er->extra_msr_access)
 134                         return -ENXIO;
 135
 136                 reg->idx = er->idx;
 137                 reg->config = event->attr.config1;
 138                 reg->reg = er->msr;
 139                 break;
 140         }
 141         return 0;
 142 }
 143
 144 static atomic_t active_events;
 145 static atomic_t pmc_refcount;
 146 static DEFINE_MUTEX(pmc_reserve_mutex);
 147
 148 #ifdef CONFIG_X86_LOCAL_APIC
 149
 150 static bool reserve_pmc_hardware(void)
 151 {
 152         int i;
 153
 154         for (i = 0; i < x86_pmu.num_counters; i++) {
 155                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 156                         goto perfctr_fail;
 157         }
 158
 159         for (i = 0; i < x86_pmu.num_counters; i++) {
 160                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 161                         goto eventsel_fail;
 162         }
 163
 164         return true;
 165
 166 eventsel_fail:
 167         for (i--; i >= 0; i--)
 168                 release_evntsel_nmi(x86_pmu_config_addr(i));
 169
 170         i = x86_pmu.num_counters;
 171
 172 perfctr_fail:
 173         for (i--; i >= 0; i--)
 174                 release_perfctr_nmi(x86_pmu_event_addr(i));
 175
 176         return false;
 177 }
 178
 179 static void release_pmc_hardware(void)
 180 {
 181         int i;
 182
 183         for (i = 0; i < x86_pmu.num_counters; i++) {
 184                 release_perfctr_nmi(x86_pmu_event_addr(i));
 185                 release_evntsel_nmi(x86_pmu_config_addr(i));
 186         }
 187 }
 188
 189 #else
 190
 191 static bool reserve_pmc_hardware(void) { return true; }
 192 static void release_pmc_hardware(void) {}
 193
 194 #endif
 195
 196 static bool check_hw_exists(void)
 197 {
 198         u64 val, val_fail = -1, val_new= ~0;
 199         int i, reg, reg_fail = -1, ret = 0;
 200         int bios_fail = 0;
 201         int reg_safe = -1;
 202
 203         /*
 204          * Check to see if the BIOS enabled any of the counters, if so
 205          * complain and bail.
 206          */
 207         for (i = 0; i < x86_pmu.num_counters; i++) {
 208                 reg = x86_pmu_config_addr(i);
 209                 ret = rdmsrl_safe(reg, &val);
 210                 if (ret)
 211                         goto msr_fail;
 212                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 213                         bios_fail = 1;
 214                         val_fail = val;
 215                         reg_fail = reg;
 216                 } else {
 217                         reg_safe = i;
 218                 }
 219         }
 220
 221         if (x86_pmu.num_counters_fixed) {
 222                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 223                 ret = rdmsrl_safe(reg, &val);
 224                 if (ret)
 225                         goto msr_fail;
 226                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 227                         if (val & (0x03 << i*4)) {
 228                                 bios_fail = 1;
 229                                 val_fail = val;
 230                                 reg_fail = reg;
 231                         }
 232                 }
 233         }
 234
 235         /*
 236          * If all the counters are enabled, the below test will always
 237          * fail.  The tools will also become useless in this scenario.
 238          * Just fail and disable the hardware counters.
 239          */
 240
 241         if (reg_safe == -1) {
 242                 reg = reg_safe;
 243                 goto msr_fail;
 244         }
 245
 246         /*
 247          * Read the current value, change it and read it back to see if it
 248          * matches, this is needed to detect certain hardware emulators
 249          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 250          */
 251         reg = x86_pmu_event_addr(reg_safe);
 252         if (rdmsrl_safe(reg, &val))
 253                 goto msr_fail;
 254         val ^= 0xffffUL;
 255         ret = wrmsrl_safe(reg, val);
 256         ret |= rdmsrl_safe(reg, &val_new);
 257         if (ret || val != val_new)
 258                 goto msr_fail;
 259
 260         /*
 261          * We still allow the PMU driver to operate:
 262          */
 263         if (bios_fail) {
 264                 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
 265                 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
 266                               reg_fail, val_fail);
 267         }
 268
 269         return true;
 270
 271 msr_fail:
 272         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
 273                 pr_cont("PMU not available due to virtualization, using software events only.\n");
 274         } else {
 275                 pr_cont("Broken PMU hardware detected, using software events only.\n");
 276                 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
 277                        reg, val_new);
 278         }
 279
 280         return false;
 281 }
 282
 283 static void hw_perf_event_destroy(struct perf_event *event)
 284 {
 285         x86_release_hardware();
 286         atomic_dec(&active_events);
 287 }
 288
 289 void hw_perf_lbr_event_destroy(struct perf_event *event)
 290 {
 291         hw_perf_event_destroy(event);
 292
 293         /* undo the lbr/bts event accounting */
 294         x86_del_exclusive(x86_lbr_exclusive_lbr);
 295 }
 296
 297 static inline int x86_pmu_initialized(void)
 298 {
 299         return x86_pmu.handle_irq != NULL;
 300 }
 301
 302 static inline int
 303 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 304 {
 305         struct perf_event_attr *attr = &event->attr;
 306         unsigned int cache_type, cache_op, cache_result;
 307         u64 config, val;
 308
 309         config = attr->config;
 310
 311         cache_type = (config >> 0) & 0xff;
 312         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 313                 return -EINVAL;
 314         cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
 315
 316         cache_op = (config >>  8) & 0xff;
 317         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 318                 return -EINVAL;
 319         cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
 320
 321         cache_result = (config >> 16) & 0xff;
 322         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 323                 return -EINVAL;
 324         cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
 325
 326         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 327
 328         if (val == 0)
 329                 return -ENOENT;
 330
 331         if (val == -1)
 332                 return -EINVAL;
 333
 334         hwc->config |= val;
 335         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 336         return x86_pmu_extra_regs(val, event);
 337 }
 338
 339 int x86_reserve_hardware(void)
 340 {
 341         int err = 0;
 342
 343         if (!atomic_inc_not_zero(&pmc_refcount)) {
 344                 mutex_lock(&pmc_reserve_mutex);
 345                 if (atomic_read(&pmc_refcount) == 0) {
 346                         if (!reserve_pmc_hardware())
 347                                 err = -EBUSY;
 348                         else
 349                                 reserve_ds_buffers();
 350                 }
 351                 if (!err)
 352                         atomic_inc(&pmc_refcount);
 353                 mutex_unlock(&pmc_reserve_mutex);
 354         }
 355
 356         return err;
 357 }
 358
 359 void x86_release_hardware(void)
 360 {
 361         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 362                 release_pmc_hardware();
 363                 release_ds_buffers();
 364                 release_lbr_buffers();
 365                 mutex_unlock(&pmc_reserve_mutex);
 366         }
 367 }
 368
 369 /*
 370  * Check if we can create event of a certain type (that no conflicting events
 371  * are present).
 372  */
 373 int x86_add_exclusive(unsigned int what)
 374 {
 375         int i;
 376
 377         /*
 378          * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
 379          * LBR and BTS are still mutually exclusive.
 380          */
 381         if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
 382                 goto out;
 383
 384         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 385                 mutex_lock(&pmc_reserve_mutex);
 386                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 387                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 388                                 goto fail_unlock;
 389                 }
 390                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 391                 mutex_unlock(&pmc_reserve_mutex);
 392         }
 393
 394 out:
 395         atomic_inc(&active_events);
 396         return 0;
 397
 398 fail_unlock:
 399         mutex_unlock(&pmc_reserve_mutex);
 400         return -EBUSY;
 401 }
 402
 403 void x86_del_exclusive(unsigned int what)
 404 {
 405         atomic_dec(&active_events);
 406
 407         /*
 408          * See the comment in x86_add_exclusive().
 409          */
 410         if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
 411                 return;
 412
 413         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 414 }
 415
 416 int x86_setup_perfctr(struct perf_event *event)
 417 {
 418         struct perf_event_attr *attr = &event->attr;
 419         struct hw_perf_event *hwc = &event->hw;
 420         u64 config;
 421
 422         if (!is_sampling_event(event)) {
 423                 hwc->sample_period = x86_pmu.max_period;
 424                 hwc->last_period = hwc->sample_period;
 425                 local64_set(&hwc->period_left, hwc->sample_period);
 426         }
 427
 428         if (attr->type == PERF_TYPE_RAW)
 429                 return x86_pmu_extra_regs(event->attr.config, event);
 430
 431         if (attr->type == PERF_TYPE_HW_CACHE)
 432                 return set_ext_hw_attr(hwc, event);
 433
 434         if (attr->config >= x86_pmu.max_events)
 435                 return -EINVAL;
 436
 437         attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
 438
 439         /*
 440          * The generic map:
 441          */
 442         config = x86_pmu.event_map(attr->config);
 443
 444         if (config == 0)
 445                 return -ENOENT;
 446
 447         if (config == -1LL)
 448                 return -EINVAL;
 449
 450         hwc->config |= config;
 451
 452         return 0;
 453 }
 454
 455 /*
 456  * check that branch_sample_type is compatible with
 457  * settings needed for precise_ip > 1 which implies
 458  * using the LBR to capture ALL taken branches at the
 459  * priv levels of the measurement
 460  */
 461 static inline int precise_br_compat(struct perf_event *event)
 462 {
 463         u64 m = event->attr.branch_sample_type;
 464         u64 b = 0;
 465
 466         /* must capture all branches */
 467         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 468                 return 0;
 469
 470         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 471
 472         if (!event->attr.exclude_user)
 473                 b |= PERF_SAMPLE_BRANCH_USER;
 474
 475         if (!event->attr.exclude_kernel)
 476                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 477
 478         /*
 479          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 480          */
 481
 482         return m == b;
 483 }
 484
 485 int x86_pmu_max_precise(void)
 486 {
 487         int precise = 0;
 488
 489         /* Support for constant skid */
 490         if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 491                 precise++;
 492
 493                 /* Support for IP fixup */
 494                 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 495                         precise++;
 496
 497                 if (x86_pmu.pebs_prec_dist)
 498                         precise++;
 499         }
 500         return precise;
 501 }
 502
 503 int x86_pmu_hw_config(struct perf_event *event)
 504 {
 505         if (event->attr.precise_ip) {
 506                 int precise = x86_pmu_max_precise();
 507
 508                 if (event->attr.precise_ip > precise)
 509                         return -EOPNOTSUPP;
 510
 511                 /* There's no sense in having PEBS for non sampling events: */
 512                 if (!is_sampling_event(event))
 513                         return -EINVAL;
 514         }
 515         /*
 516          * check that PEBS LBR correction does not conflict with
 517          * whatever the user is asking with attr->branch_sample_type
 518          */
 519         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 520                 u64 *br_type = &event->attr.branch_sample_type;
 521
 522                 if (has_branch_stack(event)) {
 523                         if (!precise_br_compat(event))
 524                                 return -EOPNOTSUPP;
 525
 526                         /* branch_sample_type is compatible */
 527
 528                 } else {
 529                         /*
 530                          * user did not specify  branch_sample_type
 531                          *
 532                          * For PEBS fixups, we capture all
 533                          * the branches at the priv level of the
 534                          * event.
 535                          */
 536                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 537
 538                         if (!event->attr.exclude_user)
 539                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 540
 541                         if (!event->attr.exclude_kernel)
 542                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 543                 }
 544         }
 545
 546         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 547                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 548
 549         /*
 550          * Generate PMC IRQs:
 551          * (keep 'enabled' bit clear for now)
 552          */
 553         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 554
 555         /*
 556          * Count user and OS events unless requested not to
 557          */
 558         if (!event->attr.exclude_user)
 559                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 560         if (!event->attr.exclude_kernel)
 561                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 562
 563         if (event->attr.type == PERF_TYPE_RAW)
 564                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 565
 566         if (event->attr.sample_period && x86_pmu.limit_period) {
 567                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 568                                 event->attr.sample_period)
 569                         return -EINVAL;
 570         }
 571
 572         /* sample_regs_user never support XMM registers */
 573         if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
 574                 return -EINVAL;
 575         /*
 576          * Besides the general purpose registers, XMM registers may
 577          * be collected in PEBS on some platforms, e.g. Icelake
 578          */
 579         if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
 580                 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
 581                         return -EINVAL;
 582
 583                 if (!event->attr.precise_ip)
 584                         return -EINVAL;
 585         }
 586
 587         return x86_setup_perfctr(event);
 588 }
 589
 590 /*
 591  * Setup the hardware configuration for a given attr_type
 592  */
 593 static int __x86_pmu_event_init(struct perf_event *event)
 594 {
 595         int err;
 596
 597         if (!x86_pmu_initialized())
 598                 return -ENODEV;
 599
 600         err = x86_reserve_hardware();
 601         if (err)
 602                 return err;
 603
 604         atomic_inc(&active_events);
 605         event->destroy = hw_perf_event_destroy;
 606
 607         event->hw.idx = -1;
 608         event->hw.last_cpu = -1;
 609         event->hw.last_tag = ~0ULL;
 610
 611         /* mark unused */
 612         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 613         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 614
 615         return x86_pmu.hw_config(event);
 616 }
 617
 618 void x86_pmu_disable_all(void)
 619 {
 620         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 621         int idx;
 622
 623         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 624                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 625                 u64 val;
 626
 627                 if (!test_bit(idx, cpuc->active_mask))
 628                         continue;
 629                 rdmsrl(x86_pmu_config_addr(idx), val);
 630                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 631                         continue;
 632                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 633                 wrmsrl(x86_pmu_config_addr(idx), val);
 634                 if (is_counter_pair(hwc))
 635                         wrmsrl(x86_pmu_config_addr(idx + 1), 0);
 636         }
 637 }
 638
 639 /*
 640  * There may be PMI landing after enabled=0. The PMI hitting could be before or
 641  * after disable_all.
 642  *
 643  * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 644  * It will not be re-enabled in the NMI handler again, because enabled=0. After
 645  * handling the NMI, disable_all will be called, which will not change the
 646  * state either. If PMI hits after disable_all, the PMU is already disabled
 647  * before entering NMI handler. The NMI handler will not change the state
 648  * either.
 649  *
 650  * So either situation is harmless.
 651  */
 652 static void x86_pmu_disable(struct pmu *pmu)
 653 {
 654         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 655
 656         if (!x86_pmu_initialized())
 657                 return;
 658
 659         if (!cpuc->enabled)
 660                 return;
 661
 662         cpuc->n_added = 0;
 663         cpuc->enabled = 0;
 664         barrier();
 665
 666         x86_pmu.disable_all();
 667 }
 668
 669 void x86_pmu_enable_all(int added)
 670 {
 671         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 672         int idx;
 673
 674         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 675                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 676
 677                 if (!test_bit(idx, cpuc->active_mask))
 678                         continue;
 679
 680                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 681         }
 682 }
 683
 684 static struct pmu pmu;
 685
 686 static inline int is_x86_event(struct perf_event *event)
 687 {
 688         return event->pmu == &pmu;
 689 }
 690
 691 struct pmu *x86_get_pmu(void)
 692 {
 693         return &pmu;
 694 }
 695 /*
 696  * Event scheduler state:
 697  *
 698  * Assign events iterating over all events and counters, beginning
 699  * with events with least weights first. Keep the current iterator
 700  * state in struct sched_state.
 701  */
 702 struct sched_state {
 703         int     weight;
 704         int     event;          /* event index */
 705         int     counter;        /* counter index */
 706         int     unassigned;     /* number of events to be assigned left */
 707         int     nr_gp;          /* number of GP counters used */
 708         u64     used;
 709 };
 710
 711 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 712 #define SCHED_STATES_MAX        2
 713
 714 struct perf_sched {
 715         int                     max_weight;
 716         int                     max_events;
 717         int                     max_gp;
 718         int                     saved_states;
 719         struct event_constraint **constraints;
 720         struct sched_state      state;
 721         struct sched_state      saved[SCHED_STATES_MAX];
 722 };
 723
 724 /*
 725  * Initialize interator that runs through all events and counters.
 726  */
 727 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 728                             int num, int wmin, int wmax, int gpmax)
 729 {
 730         int idx;
 731
 732         memset(sched, 0, sizeof(*sched));
 733         sched->max_events       = num;
 734         sched->max_weight       = wmax;
 735         sched->max_gp           = gpmax;
 736         sched->constraints      = constraints;
 737
 738         for (idx = 0; idx < num; idx++) {
 739                 if (constraints[idx]->weight == wmin)
 740                         break;
 741         }
 742
 743         sched->state.event      = idx;          /* start with min weight */
 744         sched->state.weight     = wmin;
 745         sched->state.unassigned = num;
 746 }
 747
 748 static void perf_sched_save_state(struct perf_sched *sched)
 749 {
 750         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 751                 return;
 752
 753         sched->saved[sched->saved_states] = sched->state;
 754         sched->saved_states++;
 755 }
 756
 757 static bool perf_sched_restore_state(struct perf_sched *sched)
 758 {
 759         if (!sched->saved_states)
 760                 return false;
 761
 762         sched->saved_states--;
 763         sched->state = sched->saved[sched->saved_states];
 764
 765         /* this assignment didn't work out */
 766         /* XXX broken vs EVENT_PAIR */
 767         sched->state.used &= ~BIT_ULL(sched->state.counter);
 768
 769         /* try the next one */
 770         sched->state.counter++;
 771
 772         return true;
 773 }
 774
 775 /*
 776  * Select a counter for the current event to schedule. Return true on
 777  * success.
 778  */
 779 static bool __perf_sched_find_counter(struct perf_sched *sched)
 780 {
 781         struct event_constraint *c;
 782         int idx;
 783
 784         if (!sched->state.unassigned)
 785                 return false;
 786
 787         if (sched->state.event >= sched->max_events)
 788                 return false;
 789
 790         c = sched->constraints[sched->state.event];
 791         /* Prefer fixed purpose counters */
 792         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 793                 idx = INTEL_PMC_IDX_FIXED;
 794                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 795                         u64 mask = BIT_ULL(idx);
 796
 797                         if (sched->state.used & mask)
 798                                 continue;
 799
 800                         sched->state.used |= mask;
 801                         goto done;
 802                 }
 803         }
 804
 805         /* Grab the first unused counter starting with idx */
 806         idx = sched->state.counter;
 807         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 808                 u64 mask = BIT_ULL(idx);
 809
 810                 if (c->flags & PERF_X86_EVENT_PAIR)
 811                         mask |= mask << 1;
 812
 813                 if (sched->state.used & mask)
 814                         continue;
 815
 816                 if (sched->state.nr_gp++ >= sched->max_gp)
 817                         return false;
 818
 819                 sched->state.used |= mask;
 820                 goto done;
 821         }
 822
 823         return false;
 824
 825 done:
 826         sched->state.counter = idx;
 827
 828         if (c->overlap)
 829                 perf_sched_save_state(sched);
 830
 831         return true;
 832 }
 833
 834 static bool perf_sched_find_counter(struct perf_sched *sched)
 835 {
 836         while (!__perf_sched_find_counter(sched)) {
 837                 if (!perf_sched_restore_state(sched))
 838                         return false;
 839         }
 840
 841         return true;
 842 }
 843
 844 /*
 845  * Go through all unassigned events and find the next one to schedule.
 846  * Take events with the least weight first. Return true on success.
 847  */
 848 static bool perf_sched_next_event(struct perf_sched *sched)
 849 {
 850         struct event_constraint *c;
 851
 852         if (!sched->state.unassigned || !--sched->state.unassigned)
 853                 return false;
 854
 855         do {
 856                 /* next event */
 857                 sched->state.event++;
 858                 if (sched->state.event >= sched->max_events) {
 859                         /* next weight */
 860                         sched->state.event = 0;
 861                         sched->state.weight++;
 862                         if (sched->state.weight > sched->max_weight)
 863                                 return false;
 864                 }
 865                 c = sched->constraints[sched->state.event];
 866         } while (c->weight != sched->state.weight);
 867
 868         sched->state.counter = 0;       /* start with first counter */
 869
 870         return true;
 871 }
 872
 873 /*
 874  * Assign a counter for each event.
 875  */
 876 int perf_assign_events(struct event_constraint **constraints, int n,
 877                         int wmin, int wmax, int gpmax, int *assign)
 878 {
 879         struct perf_sched sched;
 880
 881         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 882
 883         do {
 884                 if (!perf_sched_find_counter(&sched))
 885                         break;  /* failed */
 886                 if (assign)
 887                         assign[sched.state.event] = sched.state.counter;
 888         } while (perf_sched_next_event(&sched));
 889
 890         return sched.state.unassigned;
 891 }
 892 EXPORT_SYMBOL_GPL(perf_assign_events);
 893
 894 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 895 {
 896         struct event_constraint *c;
 897         struct perf_event *e;
 898         int n0, i, wmin, wmax, unsched = 0;
 899         struct hw_perf_event *hwc;
 900         u64 used_mask = 0;
 901
 902         /*
 903          * Compute the number of events already present; see x86_pmu_add(),
 904          * validate_group() and x86_pmu_commit_txn(). For the former two
 905          * cpuc->n_events hasn't been updated yet, while for the latter
 906          * cpuc->n_txn contains the number of events added in the current
 907          * transaction.
 908          */
 909         n0 = cpuc->n_events;
 910         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
 911                 n0 -= cpuc->n_txn;
 912
 913         if (x86_pmu.start_scheduling)
 914                 x86_pmu.start_scheduling(cpuc);
 915
 916         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 917                 c = cpuc->event_constraint[i];
 918
 919                 /*
 920                  * Previously scheduled events should have a cached constraint,
 921                  * while new events should not have one.
 922                  */
 923                 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
 924
 925                 /*
 926                  * Request constraints for new events; or for those events that
 927                  * have a dynamic constraint -- for those the constraint can
 928                  * change due to external factors (sibling state, allow_tfa).
 929                  */
 930                 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
 931                         c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 932                         cpuc->event_constraint[i] = c;
 933                 }
 934
 935                 wmin = min(wmin, c->weight);
 936                 wmax = max(wmax, c->weight);
 937         }
 938
 939         /*
 940          * fastpath, try to reuse previous register
 941          */
 942         for (i = 0; i < n; i++) {
 943                 u64 mask;
 944
 945                 hwc = &cpuc->event_list[i]->hw;
 946                 c = cpuc->event_constraint[i];
 947
 948                 /* never assigned */
 949                 if (hwc->idx == -1)
 950                         break;
 951
 952                 /* constraint still honored */
 953                 if (!test_bit(hwc->idx, c->idxmsk))
 954                         break;
 955
 956                 mask = BIT_ULL(hwc->idx);
 957                 if (is_counter_pair(hwc))
 958                         mask |= mask << 1;
 959
 960                 /* not already used */
 961                 if (used_mask & mask)
 962                         break;
 963
 964                 used_mask |= mask;
 965
 966                 if (assign)
 967                         assign[i] = hwc->idx;
 968         }
 969
 970         /* slow path */
 971         if (i != n) {
 972                 int gpmax = x86_pmu.num_counters;
 973
 974                 /*
 975                  * Do not allow scheduling of more than half the available
 976                  * generic counters.
 977                  *
 978                  * This helps avoid counter starvation of sibling thread by
 979                  * ensuring at most half the counters cannot be in exclusive
 980                  * mode. There is no designated counters for the limits. Any
 981                  * N/2 counters can be used. This helps with events with
 982                  * specific counter constraints.
 983                  */
 984                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 985                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 986                         gpmax /= 2;
 987
 988                 /*
 989                  * Reduce the amount of available counters to allow fitting
 990                  * the extra Merge events needed by large increment events.
 991                  */
 992                 if (x86_pmu.flags & PMU_FL_PAIR) {
 993                         gpmax = x86_pmu.num_counters - cpuc->n_pair;
 994                         WARN_ON(gpmax <= 0);
 995                 }
 996
 997                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 998                                              wmax, gpmax, assign);
 999         }
1000
1001         /*
1002          * In case of success (unsched = 0), mark events as committed,
1003          * so we do not put_constraint() in case new events are added
1004          * and fail to be scheduled
1005          *
1006          * We invoke the lower level commit callback to lock the resource
1007          *
1008          * We do not need to do all of this in case we are called to
1009          * validate an event group (assign == NULL)
1010          */
1011         if (!unsched && assign) {
1012                 for (i = 0; i < n; i++) {
1013                         e = cpuc->event_list[i];
1014                         if (x86_pmu.commit_scheduling)
1015                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
1016                 }
1017         } else {
1018                 for (i = n0; i < n; i++) {
1019                         e = cpuc->event_list[i];
1020
1021                         /*
1022                          * release events that failed scheduling
1023                          */
1024                         if (x86_pmu.put_event_constraints)
1025                                 x86_pmu.put_event_constraints(cpuc, e);
1026
1027                         cpuc->event_constraint[i] = NULL;
1028                 }
1029         }
1030
1031         if (x86_pmu.stop_scheduling)
1032                 x86_pmu.stop_scheduling(cpuc);
1033
1034         return unsched ? -EINVAL : 0;
1035 }
1036
1037 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1038                                struct perf_event *event)
1039 {
1040         if (is_metric_event(event)) {
1041                 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1042                         return -EINVAL;
1043                 cpuc->n_metric++;
1044         }
1045
1046         return 0;
1047 }
1048
1049 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1050                                 struct perf_event *event)
1051 {
1052         if (is_metric_event(event))
1053                 cpuc->n_metric--;
1054 }
1055
1056 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1057                          int max_count, int n)
1058 {
1059
1060         if (x86_pmu.intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1061                 return -EINVAL;
1062
1063         if (n >= max_count + cpuc->n_metric)
1064                 return -EINVAL;
1065
1066         cpuc->event_list[n] = event;
1067         if (is_counter_pair(&event->hw))
1068                 cpuc->n_pair++;
1069
1070         return 0;
1071 }
1072
1073 /*
1074  * dogrp: true if must collect siblings events (group)
1075  * returns total number of events and error code
1076  */
1077 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1078 {
1079         struct perf_event *event;
1080         int n, max_count;
1081
1082         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1083
1084         /* current number of events already accepted */
1085         n = cpuc->n_events;
1086         if (!cpuc->n_events)
1087                 cpuc->pebs_output = 0;
1088
1089         if (!cpuc->is_fake && leader->attr.precise_ip) {
1090                 /*
1091                  * For PEBS->PT, if !aux_event, the group leader (PT) went
1092                  * away, the group was broken down and this singleton event
1093                  * can't schedule any more.
1094                  */
1095                 if (is_pebs_pt(leader) && !leader->aux_event)
1096                         return -EINVAL;
1097
1098                 /*
1099                  * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1100                  */
1101                 if (cpuc->pebs_output &&
1102                     cpuc->pebs_output != is_pebs_pt(leader) + 1)
1103                         return -EINVAL;
1104
1105                 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1106         }
1107
1108         if (is_x86_event(leader)) {
1109                 if (collect_event(cpuc, leader, max_count, n))
1110                         return -EINVAL;
1111                 n++;
1112         }
1113
1114         if (!dogrp)
1115                 return n;
1116
1117         for_each_sibling_event(event, leader) {
1118                 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1119                         continue;
1120
1121                 if (collect_event(cpuc, event, max_count, n))
1122                         return -EINVAL;
1123
1124                 n++;
1125         }
1126         return n;
1127 }
1128
1129 static inline void x86_assign_hw_event(struct perf_event *event,
1130                                 struct cpu_hw_events *cpuc, int i)
1131 {
1132         struct hw_perf_event *hwc = &event->hw;
1133         int idx;
1134
1135         idx = hwc->idx = cpuc->assign[i];
1136         hwc->last_cpu = smp_processor_id();
1137         hwc->last_tag = ++cpuc->tags[i];
1138
1139         switch (hwc->idx) {
1140         case INTEL_PMC_IDX_FIXED_BTS:
1141         case INTEL_PMC_IDX_FIXED_VLBR:
1142                 hwc->config_base = 0;
1143                 hwc->event_base = 0;
1144                 break;
1145
1146         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1147                 /* All the metric events are mapped onto the fixed counter 3. */
1148                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1149                 /* fall through */
1150         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1151                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1152                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1153                                 (idx - INTEL_PMC_IDX_FIXED);
1154                 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1155                                         INTEL_PMC_FIXED_RDPMC_BASE;
1156                 break;
1157
1158         default:
1159                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1160                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1161                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1162                 break;
1163         }
1164 }
1165
1166 /**
1167  * x86_perf_rdpmc_index - Return PMC counter used for event
1168  * @event: the perf_event to which the PMC counter was assigned
1169  *
1170  * The counter assigned to this performance event may change if interrupts
1171  * are enabled. This counter should thus never be used while interrupts are
1172  * enabled. Before this function is used to obtain the assigned counter the
1173  * event should be checked for validity using, for example,
1174  * perf_event_read_local(), within the same interrupt disabled section in
1175  * which this counter is planned to be used.
1176  *
1177  * Return: The index of the performance monitoring counter assigned to
1178  * @perf_event.
1179  */
1180 int x86_perf_rdpmc_index(struct perf_event *event)
1181 {
1182         lockdep_assert_irqs_disabled();
1183
1184         return event->hw.event_base_rdpmc;
1185 }
1186
1187 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1188                                         struct cpu_hw_events *cpuc,
1189                                         int i)
1190 {
1191         return hwc->idx == cpuc->assign[i] &&
1192                 hwc->last_cpu == smp_processor_id() &&
1193                 hwc->last_tag == cpuc->tags[i];
1194 }
1195
1196 static void x86_pmu_start(struct perf_event *event, int flags);
1197
1198 static void x86_pmu_enable(struct pmu *pmu)
1199 {
1200         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1201         struct perf_event *event;
1202         struct hw_perf_event *hwc;
1203         int i, added = cpuc->n_added;
1204
1205         if (!x86_pmu_initialized())
1206                 return;
1207
1208         if (cpuc->enabled)
1209                 return;
1210
1211         if (cpuc->n_added) {
1212                 int n_running = cpuc->n_events - cpuc->n_added;
1213                 /*
1214                  * apply assignment obtained either from
1215                  * hw_perf_group_sched_in() or x86_pmu_enable()
1216                  *
1217                  * step1: save events moving to new counters
1218                  */
1219                 for (i = 0; i < n_running; i++) {
1220                         event = cpuc->event_list[i];
1221                         hwc = &event->hw;
1222
1223                         /*
1224                          * we can avoid reprogramming counter if:
1225                          * - assigned same counter as last time
1226                          * - running on same CPU as last time
1227                          * - no other event has used the counter since
1228                          */
1229                         if (hwc->idx == -1 ||
1230                             match_prev_assignment(hwc, cpuc, i))
1231                                 continue;
1232
1233                         /*
1234                          * Ensure we don't accidentally enable a stopped
1235                          * counter simply because we rescheduled.
1236                          */
1237                         if (hwc->state & PERF_HES_STOPPED)
1238                                 hwc->state |= PERF_HES_ARCH;
1239
1240                         x86_pmu_stop(event, PERF_EF_UPDATE);
1241                 }
1242
1243                 /*
1244                  * step2: reprogram moved events into new counters
1245                  */
1246                 for (i = 0; i < cpuc->n_events; i++) {
1247                         event = cpuc->event_list[i];
1248                         hwc = &event->hw;
1249
1250                         if (!match_prev_assignment(hwc, cpuc, i))
1251                                 x86_assign_hw_event(event, cpuc, i);
1252                         else if (i < n_running)
1253                                 continue;
1254
1255                         if (hwc->state & PERF_HES_ARCH)
1256                                 continue;
1257
1258                         x86_pmu_start(event, PERF_EF_RELOAD);
1259                 }
1260                 cpuc->n_added = 0;
1261                 perf_events_lapic_init();
1262         }
1263
1264         cpuc->enabled = 1;
1265         barrier();
1266
1267         x86_pmu.enable_all(added);
1268 }
1269
1270 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1271
1272 /*
1273  * Set the next IRQ period, based on the hwc->period_left value.
1274  * To be called with the event disabled in hw:
1275  */
1276 int x86_perf_event_set_period(struct perf_event *event)
1277 {
1278         struct hw_perf_event *hwc = &event->hw;
1279         s64 left = local64_read(&hwc->period_left);
1280         s64 period = hwc->sample_period;
1281         int ret = 0, idx = hwc->idx;
1282
1283         if (unlikely(!hwc->event_base))
1284                 return 0;
1285
1286         if (unlikely(is_topdown_count(event)) &&
1287             x86_pmu.set_topdown_event_period)
1288                 return x86_pmu.set_topdown_event_period(event);
1289
1290         /*
1291          * If we are way outside a reasonable range then just skip forward:
1292          */
1293         if (unlikely(left <= -period)) {
1294                 left = period;
1295                 local64_set(&hwc->period_left, left);
1296                 hwc->last_period = period;
1297                 ret = 1;
1298         }
1299
1300         if (unlikely(left <= 0)) {
1301                 left += period;
1302                 local64_set(&hwc->period_left, left);
1303                 hwc->last_period = period;
1304                 ret = 1;
1305         }
1306         /*
1307          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1308          */
1309         if (unlikely(left < 2))
1310                 left = 2;
1311
1312         if (left > x86_pmu.max_period)
1313                 left = x86_pmu.max_period;
1314
1315         if (x86_pmu.limit_period)
1316                 left = x86_pmu.limit_period(event, left);
1317
1318         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1319
1320         /*
1321          * The hw event starts counting from this event offset,
1322          * mark it to be able to extra future deltas:
1323          */
1324         local64_set(&hwc->prev_count, (u64)-left);
1325
1326         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1327
1328         /*
1329          * Sign extend the Merge event counter's upper 16 bits since
1330          * we currently declare a 48-bit counter width
1331          */
1332         if (is_counter_pair(hwc))
1333                 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1334
1335         /*
1336          * Due to erratum on certan cpu we need
1337          * a second write to be sure the register
1338          * is updated properly
1339          */
1340         if (x86_pmu.perfctr_second_write) {
1341                 wrmsrl(hwc->event_base,
1342                         (u64)(-left) & x86_pmu.cntval_mask);
1343         }
1344
1345         perf_event_update_userpage(event);
1346
1347         return ret;
1348 }
1349
1350 void x86_pmu_enable_event(struct perf_event *event)
1351 {
1352         if (__this_cpu_read(cpu_hw_events.enabled))
1353                 __x86_pmu_enable_event(&event->hw,
1354                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1355 }
1356
1357 /*
1358  * Add a single event to the PMU.
1359  *
1360  * The event is added to the group of enabled events
1361  * but only if it can be scheduled with existing events.
1362  */
1363 static int x86_pmu_add(struct perf_event *event, int flags)
1364 {
1365         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1366         struct hw_perf_event *hwc;
1367         int assign[X86_PMC_IDX_MAX];
1368         int n, n0, ret;
1369
1370         hwc = &event->hw;
1371
1372         n0 = cpuc->n_events;
1373         ret = n = collect_events(cpuc, event, false);
1374         if (ret < 0)
1375                 goto out;
1376
1377         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1378         if (!(flags & PERF_EF_START))
1379                 hwc->state |= PERF_HES_ARCH;
1380
1381         /*
1382          * If group events scheduling transaction was started,
1383          * skip the schedulability test here, it will be performed
1384          * at commit time (->commit_txn) as a whole.
1385          *
1386          * If commit fails, we'll call ->del() on all events
1387          * for which ->add() was called.
1388          */
1389         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1390                 goto done_collect;
1391
1392         ret = x86_pmu.schedule_events(cpuc, n, assign);
1393         if (ret)
1394                 goto out;
1395         /*
1396          * copy new assignment, now we know it is possible
1397          * will be used by hw_perf_enable()
1398          */
1399         memcpy(cpuc->assign, assign, n*sizeof(int));
1400
1401 done_collect:
1402         /*
1403          * Commit the collect_events() state. See x86_pmu_del() and
1404          * x86_pmu_*_txn().
1405          */
1406         cpuc->n_events = n;
1407         cpuc->n_added += n - n0;
1408         cpuc->n_txn += n - n0;
1409
1410         if (x86_pmu.add) {
1411                 /*
1412                  * This is before x86_pmu_enable() will call x86_pmu_start(),
1413                  * so we enable LBRs before an event needs them etc..
1414                  */
1415                 x86_pmu.add(event);
1416         }
1417
1418         ret = 0;
1419 out:
1420         return ret;
1421 }
1422
1423 static void x86_pmu_start(struct perf_event *event, int flags)
1424 {
1425         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1426         int idx = event->hw.idx;
1427
1428         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1429                 return;
1430
1431         if (WARN_ON_ONCE(idx == -1))
1432                 return;
1433
1434         if (flags & PERF_EF_RELOAD) {
1435                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1436                 x86_perf_event_set_period(event);
1437         }
1438
1439         event->hw.state = 0;
1440
1441         cpuc->events[idx] = event;
1442         __set_bit(idx, cpuc->active_mask);
1443         __set_bit(idx, cpuc->running);
1444         x86_pmu.enable(event);
1445         perf_event_update_userpage(event);
1446 }
1447
1448 void perf_event_print_debug(void)
1449 {
1450         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1451         u64 pebs, debugctl;
1452         struct cpu_hw_events *cpuc;
1453         unsigned long flags;
1454         int cpu, idx;
1455
1456         if (!x86_pmu.num_counters)
1457                 return;
1458
1459         local_irq_save(flags);
1460
1461         cpu = smp_processor_id();
1462         cpuc = &per_cpu(cpu_hw_events, cpu);
1463
1464         if (x86_pmu.version >= 2) {
1465                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1466                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1467                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1468                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1469
1470                 pr_info("\n");
1471                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1472                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1473                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1474                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1475                 if (x86_pmu.pebs_constraints) {
1476                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1477                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1478                 }
1479                 if (x86_pmu.lbr_nr) {
1480                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1481                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1482                 }
1483         }
1484         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1485
1486         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1487                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1488                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1489
1490                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1491
1492                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1493                         cpu, idx, pmc_ctrl);
1494                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1495                         cpu, idx, pmc_count);
1496                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1497                         cpu, idx, prev_left);
1498         }
1499         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1500                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1501
1502                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1503                         cpu, idx, pmc_count);
1504         }
1505         local_irq_restore(flags);
1506 }
1507
1508 void x86_pmu_stop(struct perf_event *event, int flags)
1509 {
1510         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1511         struct hw_perf_event *hwc = &event->hw;
1512
1513         if (test_bit(hwc->idx, cpuc->active_mask)) {
1514                 x86_pmu.disable(event);
1515                 __clear_bit(hwc->idx, cpuc->active_mask);
1516                 cpuc->events[hwc->idx] = NULL;
1517                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1518                 hwc->state |= PERF_HES_STOPPED;
1519         }
1520
1521         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1522                 /*
1523                  * Drain the remaining delta count out of a event
1524                  * that we are disabling:
1525                  */
1526                 x86_perf_event_update(event);
1527                 hwc->state |= PERF_HES_UPTODATE;
1528         }
1529 }
1530
1531 static void x86_pmu_del(struct perf_event *event, int flags)
1532 {
1533         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1534         int i;
1535
1536         /*
1537          * If we're called during a txn, we only need to undo x86_pmu.add.
1538          * The events never got scheduled and ->cancel_txn will truncate
1539          * the event_list.
1540          *
1541          * XXX assumes any ->del() called during a TXN will only be on
1542          * an event added during that same TXN.
1543          */
1544         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1545                 goto do_del;
1546
1547         /*
1548          * Not a TXN, therefore cleanup properly.
1549          */
1550         x86_pmu_stop(event, PERF_EF_UPDATE);
1551
1552         for (i = 0; i < cpuc->n_events; i++) {
1553                 if (event == cpuc->event_list[i])
1554                         break;
1555         }
1556
1557         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1558                 return;
1559
1560         /* If we have a newly added event; make sure to decrease n_added. */
1561         if (i >= cpuc->n_events - cpuc->n_added)
1562                 --cpuc->n_added;
1563
1564         if (x86_pmu.put_event_constraints)
1565                 x86_pmu.put_event_constraints(cpuc, event);
1566
1567         /* Delete the array entry. */
1568         while (++i < cpuc->n_events) {
1569                 cpuc->event_list[i-1] = cpuc->event_list[i];
1570                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1571         }
1572         cpuc->event_constraint[i-1] = NULL;
1573         --cpuc->n_events;
1574         if (x86_pmu.intel_cap.perf_metrics)
1575                 del_nr_metric_event(cpuc, event);
1576
1577         perf_event_update_userpage(event);
1578
1579 do_del:
1580         if (x86_pmu.del) {
1581                 /*
1582                  * This is after x86_pmu_stop(); so we disable LBRs after any
1583                  * event can need them etc..
1584                  */
1585                 x86_pmu.del(event);
1586         }
1587 }
1588
1589 int x86_pmu_handle_irq(struct pt_regs *regs)
1590 {
1591         struct perf_sample_data data;
1592         struct cpu_hw_events *cpuc;
1593         struct perf_event *event;
1594         int idx, handled = 0;
1595         u64 val;
1596
1597         cpuc = this_cpu_ptr(&cpu_hw_events);
1598
1599         /*
1600          * Some chipsets need to unmask the LVTPC in a particular spot
1601          * inside the nmi handler.  As a result, the unmasking was pushed
1602          * into all the nmi handlers.
1603          *
1604          * This generic handler doesn't seem to have any issues where the
1605          * unmasking occurs so it was left at the top.
1606          */
1607         apic_write(APIC_LVTPC, APIC_DM_NMI);
1608
1609         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1610                 if (!test_bit(idx, cpuc->active_mask))
1611                         continue;
1612
1613                 event = cpuc->events[idx];
1614
1615                 val = x86_perf_event_update(event);
1616                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1617                         continue;
1618
1619                 /*
1620                  * event overflow
1621                  */
1622                 handled++;
1623                 perf_sample_data_init(&data, 0, event->hw.last_period);
1624
1625                 if (!x86_perf_event_set_period(event))
1626                         continue;
1627
1628                 if (perf_event_overflow(event, &data, regs))
1629                         x86_pmu_stop(event, 0);
1630         }
1631
1632         if (handled)
1633                 inc_irq_stat(apic_perf_irqs);
1634
1635         return handled;
1636 }
1637
1638 void perf_events_lapic_init(void)
1639 {
1640         if (!x86_pmu.apic || !x86_pmu_initialized())
1641                 return;
1642
1643         /*
1644          * Always use NMI for PMU
1645          */
1646         apic_write(APIC_LVTPC, APIC_DM_NMI);
1647 }
1648
1649 static int
1650 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1651 {
1652         u64 start_clock;
1653         u64 finish_clock;
1654         int ret;
1655
1656         /*
1657          * All PMUs/events that share this PMI handler should make sure to
1658          * increment active_events for their events.
1659          */
1660         if (!atomic_read(&active_events))
1661                 return NMI_DONE;
1662
1663         start_clock = sched_clock();
1664         ret = x86_pmu.handle_irq(regs);
1665         finish_clock = sched_clock();
1666
1667         perf_sample_event_took(finish_clock - start_clock);
1668
1669         return ret;
1670 }
1671 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1672
1673 struct event_constraint emptyconstraint;
1674 struct event_constraint unconstrained;
1675
1676 static int x86_pmu_prepare_cpu(unsigned int cpu)
1677 {
1678         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1679         int i;
1680
1681         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1682                 cpuc->kfree_on_online[i] = NULL;
1683         if (x86_pmu.cpu_prepare)
1684                 return x86_pmu.cpu_prepare(cpu);
1685         return 0;
1686 }
1687
1688 static int x86_pmu_dead_cpu(unsigned int cpu)
1689 {
1690         if (x86_pmu.cpu_dead)
1691                 x86_pmu.cpu_dead(cpu);
1692         return 0;
1693 }
1694
1695 static int x86_pmu_online_cpu(unsigned int cpu)
1696 {
1697         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1698         int i;
1699
1700         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1701                 kfree(cpuc->kfree_on_online[i]);
1702                 cpuc->kfree_on_online[i] = NULL;
1703         }
1704         return 0;
1705 }
1706
1707 static int x86_pmu_starting_cpu(unsigned int cpu)
1708 {
1709         if (x86_pmu.cpu_starting)
1710                 x86_pmu.cpu_starting(cpu);
1711         return 0;
1712 }
1713
1714 static int x86_pmu_dying_cpu(unsigned int cpu)
1715 {
1716         if (x86_pmu.cpu_dying)
1717                 x86_pmu.cpu_dying(cpu);
1718         return 0;
1719 }
1720
1721 static void __init pmu_check_apic(void)
1722 {
1723         if (boot_cpu_has(X86_FEATURE_APIC))
1724                 return;
1725
1726         x86_pmu.apic = 0;
1727         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1728         pr_info("no hardware sampling interrupt available.\n");
1729
1730         /*
1731          * If we have a PMU initialized but no APIC
1732          * interrupts, we cannot sample hardware
1733          * events (user-space has to fall back and
1734          * sample via a hrtimer based software event):
1735          */
1736         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1737
1738 }
1739
1740 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1741         .name = "format",
1742         .attrs = NULL,
1743 };
1744
1745 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1746 {
1747         struct perf_pmu_events_attr *pmu_attr =
1748                 container_of(attr, struct perf_pmu_events_attr, attr);
1749         u64 config = 0;
1750
1751         if (pmu_attr->id < x86_pmu.max_events)
1752                 config = x86_pmu.event_map(pmu_attr->id);
1753
1754         /* string trumps id */
1755         if (pmu_attr->event_str)
1756                 return sprintf(page, "%s", pmu_attr->event_str);
1757
1758         return x86_pmu.events_sysfs_show(page, config);
1759 }
1760 EXPORT_SYMBOL_GPL(events_sysfs_show);
1761
1762 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1763                           char *page)
1764 {
1765         struct perf_pmu_events_ht_attr *pmu_attr =
1766                 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1767
1768         /*
1769          * Report conditional events depending on Hyper-Threading.
1770          *
1771          * This is overly conservative as usually the HT special
1772          * handling is not needed if the other CPU thread is idle.
1773          *
1774          * Note this does not (and cannot) handle the case when thread
1775          * siblings are invisible, for example with virtualization
1776          * if they are owned by some other guest.  The user tool
1777          * has to re-read when a thread sibling gets onlined later.
1778          */
1779         return sprintf(page, "%s",
1780                         topology_max_smt_threads() > 1 ?
1781                         pmu_attr->event_str_ht :
1782                         pmu_attr->event_str_noht);
1783 }
1784
1785 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1786 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1787 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1788 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1789 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1790 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1791 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1792 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1793 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1794 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1795
1796 static struct attribute *empty_attrs;
1797
1798 static struct attribute *events_attr[] = {
1799         EVENT_PTR(CPU_CYCLES),
1800         EVENT_PTR(INSTRUCTIONS),
1801         EVENT_PTR(CACHE_REFERENCES),
1802         EVENT_PTR(CACHE_MISSES),
1803         EVENT_PTR(BRANCH_INSTRUCTIONS),
1804         EVENT_PTR(BRANCH_MISSES),
1805         EVENT_PTR(BUS_CYCLES),
1806         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1807         EVENT_PTR(STALLED_CYCLES_BACKEND),
1808         EVENT_PTR(REF_CPU_CYCLES),
1809         NULL,
1810 };
1811
1812 /*
1813  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1814  * out of events_attr attributes.
1815  */
1816 static umode_t
1817 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1818 {
1819         struct perf_pmu_events_attr *pmu_attr;
1820
1821         if (idx >= x86_pmu.max_events)
1822                 return 0;
1823
1824         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1825         /* str trumps id */
1826         return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1827 }
1828
1829 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1830         .name = "events",
1831         .attrs = events_attr,
1832         .is_visible = is_visible,
1833 };
1834
1835 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1836 {
1837         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1838         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1839         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1840         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1841         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1842         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1843         ssize_t ret;
1844
1845         /*
1846         * We have whole page size to spend and just little data
1847         * to write, so we can safely use sprintf.
1848         */
1849         ret = sprintf(page, "event=0x%02llx", event);
1850
1851         if (umask)
1852                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1853
1854         if (edge)
1855                 ret += sprintf(page + ret, ",edge");
1856
1857         if (pc)
1858                 ret += sprintf(page + ret, ",pc");
1859
1860         if (any)
1861                 ret += sprintf(page + ret, ",any");
1862
1863         if (inv)
1864                 ret += sprintf(page + ret, ",inv");
1865
1866         if (cmask)
1867                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1868
1869         ret += sprintf(page + ret, "\n");
1870
1871         return ret;
1872 }
1873
1874 static struct attribute_group x86_pmu_attr_group;
1875 static struct attribute_group x86_pmu_caps_group;
1876
1877 static int __init init_hw_perf_events(void)
1878 {
1879         struct x86_pmu_quirk *quirk;
1880         int err;
1881
1882         pr_info("Performance Events: ");
1883
1884         switch (boot_cpu_data.x86_vendor) {
1885         case X86_VENDOR_INTEL:
1886                 err = intel_pmu_init();
1887                 break;
1888         case X86_VENDOR_AMD:
1889                 err = amd_pmu_init();
1890                 break;
1891         case X86_VENDOR_HYGON:
1892                 err = amd_pmu_init();
1893                 x86_pmu.name = "HYGON";
1894                 break;
1895         case X86_VENDOR_ZHAOXIN:
1896         case X86_VENDOR_CENTAUR:
1897                 err = zhaoxin_pmu_init();
1898                 break;
1899         default:
1900                 err = -ENOTSUPP;
1901         }
1902         if (err != 0) {
1903                 pr_cont("no PMU driver, software events only.\n");
1904                 return 0;
1905         }
1906
1907         pmu_check_apic();
1908
1909         /* sanity check that the hardware exists or is emulated */
1910         if (!check_hw_exists())
1911                 return 0;
1912
1913         pr_cont("%s PMU driver.\n", x86_pmu.name);
1914
1915         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1916
1917         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1918                 quirk->func();
1919
1920         if (!x86_pmu.intel_ctrl)
1921                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1922
1923         perf_events_lapic_init();
1924         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1925
1926         unconstrained = (struct event_constraint)
1927                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1928                                    0, x86_pmu.num_counters, 0, 0);
1929
1930         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1931
1932         if (!x86_pmu.events_sysfs_show)
1933                 x86_pmu_events_group.attrs = &empty_attrs;
1934
1935         pmu.attr_update = x86_pmu.attr_update;
1936
1937         pr_info("... version:                %d\n",     x86_pmu.version);
1938         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1939         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1940         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1941         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1942         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1943         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1944
1945         /*
1946          * Install callbacks. Core will call them for each online
1947          * cpu.
1948          */
1949         err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1950                                 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1951         if (err)
1952                 return err;
1953
1954         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1955                                 "perf/x86:starting", x86_pmu_starting_cpu,
1956                                 x86_pmu_dying_cpu);
1957         if (err)
1958                 goto out;
1959
1960         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1961                                 x86_pmu_online_cpu, NULL);
1962         if (err)
1963                 goto out1;
1964
1965         err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1966         if (err)
1967                 goto out2;
1968
1969         return 0;
1970
1971 out2:
1972         cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1973 out1:
1974         cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1975 out:
1976         cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1977         return err;
1978 }
1979 early_initcall(init_hw_perf_events);
1980
1981 static inline void x86_pmu_read(struct perf_event *event)
1982 {
1983         if (x86_pmu.read)
1984                 return x86_pmu.read(event);
1985         x86_perf_event_update(event);
1986 }
1987
1988 /*
1989  * Start group events scheduling transaction
1990  * Set the flag to make pmu::enable() not perform the
1991  * schedulability test, it will be performed at commit time
1992  *
1993  * We only support PERF_PMU_TXN_ADD transactions. Save the
1994  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1995  * transactions.
1996  */
1997 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1998 {
1999         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2000
2001         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
2002
2003         cpuc->txn_flags = txn_flags;
2004         if (txn_flags & ~PERF_PMU_TXN_ADD)
2005                 return;
2006
2007         perf_pmu_disable(pmu);
2008         __this_cpu_write(cpu_hw_events.n_txn, 0);
2009 }
2010
2011 /*
2012  * Stop group events scheduling transaction
2013  * Clear the flag and pmu::enable() will perform the
2014  * schedulability test.
2015  */
2016 static void x86_pmu_cancel_txn(struct pmu *pmu)
2017 {
2018         unsigned int txn_flags;
2019         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2020
2021         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2022
2023         txn_flags = cpuc->txn_flags;
2024         cpuc->txn_flags = 0;
2025         if (txn_flags & ~PERF_PMU_TXN_ADD)
2026                 return;
2027
2028         /*
2029          * Truncate collected array by the number of events added in this
2030          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2031          */
2032         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2033         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2034         perf_pmu_enable(pmu);
2035 }
2036
2037 /*
2038  * Commit group events scheduling transaction
2039  * Perform the group schedulability test as a whole
2040  * Return 0 if success
2041  *
2042  * Does not cancel the transaction on failure; expects the caller to do this.
2043  */
2044 static int x86_pmu_commit_txn(struct pmu *pmu)
2045 {
2046         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2047         int assign[X86_PMC_IDX_MAX];
2048         int n, ret;
2049
2050         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2051
2052         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2053                 cpuc->txn_flags = 0;
2054                 return 0;
2055         }
2056
2057         n = cpuc->n_events;
2058
2059         if (!x86_pmu_initialized())
2060                 return -EAGAIN;
2061
2062         ret = x86_pmu.schedule_events(cpuc, n, assign);
2063         if (ret)
2064                 return ret;
2065
2066         /*
2067          * copy new assignment, now we know it is possible
2068          * will be used by hw_perf_enable()
2069          */
2070         memcpy(cpuc->assign, assign, n*sizeof(int));
2071
2072         cpuc->txn_flags = 0;
2073         perf_pmu_enable(pmu);
2074         return 0;
2075 }
2076 /*
2077  * a fake_cpuc is used to validate event groups. Due to
2078  * the extra reg logic, we need to also allocate a fake
2079  * per_core and per_cpu structure. Otherwise, group events
2080  * using extra reg may conflict without the kernel being
2081  * able to catch this when the last event gets added to
2082  * the group.
2083  */
2084 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2085 {
2086         intel_cpuc_finish(cpuc);
2087         kfree(cpuc);
2088 }
2089
2090 static struct cpu_hw_events *allocate_fake_cpuc(void)
2091 {
2092         struct cpu_hw_events *cpuc;
2093         int cpu = raw_smp_processor_id();
2094
2095         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2096         if (!cpuc)
2097                 return ERR_PTR(-ENOMEM);
2098         cpuc->is_fake = 1;
2099
2100         if (intel_cpuc_prepare(cpuc, cpu))
2101                 goto error;
2102
2103         return cpuc;
2104 error:
2105         free_fake_cpuc(cpuc);
2106         return ERR_PTR(-ENOMEM);
2107 }
2108
2109 /*
2110  * validate that we can schedule this event
2111  */
2112 static int validate_event(struct perf_event *event)
2113 {
2114         struct cpu_hw_events *fake_cpuc;
2115         struct event_constraint *c;
2116         int ret = 0;
2117
2118         fake_cpuc = allocate_fake_cpuc();
2119         if (IS_ERR(fake_cpuc))
2120                 return PTR_ERR(fake_cpuc);
2121
2122         c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2123
2124         if (!c || !c->weight)
2125                 ret = -EINVAL;
2126
2127         if (x86_pmu.put_event_constraints)
2128                 x86_pmu.put_event_constraints(fake_cpuc, event);
2129
2130         free_fake_cpuc(fake_cpuc);
2131
2132         return ret;
2133 }
2134
2135 /*
2136  * validate a single event group
2137  *
2138  * validation include:
2139  *      - check events are compatible which each other
2140  *      - events do not compete for the same counter
2141  *      - number of events <= number of counters
2142  *
2143  * validation ensures the group can be loaded onto the
2144  * PMU if it was the only group available.
2145  */
2146 static int validate_group(struct perf_event *event)
2147 {
2148         struct perf_event *leader = event->group_leader;
2149         struct cpu_hw_events *fake_cpuc;
2150         int ret = -EINVAL, n;
2151
2152         fake_cpuc = allocate_fake_cpuc();
2153         if (IS_ERR(fake_cpuc))
2154                 return PTR_ERR(fake_cpuc);
2155         /*
2156          * the event is not yet connected with its
2157          * siblings therefore we must first collect
2158          * existing siblings, then add the new event
2159          * before we can simulate the scheduling
2160          */
2161         n = collect_events(fake_cpuc, leader, true);
2162         if (n < 0)
2163                 goto out;
2164
2165         fake_cpuc->n_events = n;
2166         n = collect_events(fake_cpuc, event, false);
2167         if (n < 0)
2168                 goto out;
2169
2170         fake_cpuc->n_events = 0;
2171         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2172
2173 out:
2174         free_fake_cpuc(fake_cpuc);
2175         return ret;
2176 }
2177
2178 static int x86_pmu_event_init(struct perf_event *event)
2179 {
2180         struct pmu *tmp;
2181         int err;
2182
2183         switch (event->attr.type) {
2184         case PERF_TYPE_RAW:
2185         case PERF_TYPE_HARDWARE:
2186         case PERF_TYPE_HW_CACHE:
2187                 break;
2188
2189         default:
2190                 return -ENOENT;
2191         }
2192
2193         err = __x86_pmu_event_init(event);
2194         if (!err) {
2195                 /*
2196                  * we temporarily connect event to its pmu
2197                  * such that validate_group() can classify
2198                  * it as an x86 event using is_x86_event()
2199                  */
2200                 tmp = event->pmu;
2201                 event->pmu = &pmu;
2202
2203                 if (event->group_leader != event)
2204                         err = validate_group(event);
2205                 else
2206                         err = validate_event(event);
2207
2208                 event->pmu = tmp;
2209         }
2210         if (err) {
2211                 if (event->destroy)
2212                         event->destroy(event);
2213         }
2214
2215         if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2216             !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2217                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2218
2219         return err;
2220 }
2221
2222 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2223 {
2224         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2225                 return;
2226
2227         /*
2228          * This function relies on not being called concurrently in two
2229          * tasks in the same mm.  Otherwise one task could observe
2230          * perf_rdpmc_allowed > 1 and return all the way back to
2231          * userspace with CR4.PCE clear while another task is still
2232          * doing on_each_cpu_mask() to propagate CR4.PCE.
2233          *
2234          * For now, this can't happen because all callers hold mmap_lock
2235          * for write.  If this changes, we'll need a different solution.
2236          */
2237         mmap_assert_write_locked(mm);
2238
2239         if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2240                 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2241 }
2242
2243 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2244 {
2245
2246         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2247                 return;
2248
2249         if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2250                 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2251 }
2252
2253 static int x86_pmu_event_idx(struct perf_event *event)
2254 {
2255         struct hw_perf_event *hwc = &event->hw;
2256
2257         if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2258                 return 0;
2259
2260         if (is_metric_idx(hwc->idx))
2261                 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2262         else
2263                 return hwc->event_base_rdpmc + 1;
2264 }
2265
2266 static ssize_t get_attr_rdpmc(struct device *cdev,
2267                               struct device_attribute *attr,
2268                               char *buf)
2269 {
2270         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2271 }
2272
2273 static ssize_t set_attr_rdpmc(struct device *cdev,
2274                               struct device_attribute *attr,
2275                               const char *buf, size_t count)
2276 {
2277         unsigned long val;
2278         ssize_t ret;
2279
2280         ret = kstrtoul(buf, 0, &val);
2281         if (ret)
2282                 return ret;
2283
2284         if (val > 2)
2285                 return -EINVAL;
2286
2287         if (x86_pmu.attr_rdpmc_broken)
2288                 return -ENOTSUPP;
2289
2290         if (val != x86_pmu.attr_rdpmc) {
2291                 /*
2292                  * Changing into or out of never available or always available,
2293                  * aka perf-event-bypassing mode. This path is extremely slow,
2294                  * but only root can trigger it, so it's okay.
2295                  */
2296                 if (val == 0)
2297                         static_branch_inc(&rdpmc_never_available_key);
2298                 else if (x86_pmu.attr_rdpmc == 0)
2299                         static_branch_dec(&rdpmc_never_available_key);
2300
2301                 if (val == 2)
2302                         static_branch_inc(&rdpmc_always_available_key);
2303                 else if (x86_pmu.attr_rdpmc == 2)
2304                         static_branch_dec(&rdpmc_always_available_key);
2305
2306                 on_each_cpu(cr4_update_pce, NULL, 1);
2307                 x86_pmu.attr_rdpmc = val;
2308         }
2309
2310         return count;
2311 }
2312
2313 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2314
2315 static struct attribute *x86_pmu_attrs[] = {
2316         &dev_attr_rdpmc.attr,
2317         NULL,
2318 };
2319
2320 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2321         .attrs = x86_pmu_attrs,
2322 };
2323
2324 static ssize_t max_precise_show(struct device *cdev,
2325                                   struct device_attribute *attr,
2326                                   char *buf)
2327 {
2328         return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2329 }
2330
2331 static DEVICE_ATTR_RO(max_precise);
2332
2333 static struct attribute *x86_pmu_caps_attrs[] = {
2334         &dev_attr_max_precise.attr,
2335         NULL
2336 };
2337
2338 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2339         .name = "caps",
2340         .attrs = x86_pmu_caps_attrs,
2341 };
2342
2343 static const struct attribute_group *x86_pmu_attr_groups[] = {
2344         &x86_pmu_attr_group,
2345         &x86_pmu_format_group,
2346         &x86_pmu_events_group,
2347         &x86_pmu_caps_group,
2348         NULL,
2349 };
2350
2351 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2352 {
2353         if (x86_pmu.sched_task)
2354                 x86_pmu.sched_task(ctx, sched_in);
2355 }
2356
2357 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2358                                   struct perf_event_context *next)
2359 {
2360         if (x86_pmu.swap_task_ctx)
2361                 x86_pmu.swap_task_ctx(prev, next);
2362 }
2363
2364 void perf_check_microcode(void)
2365 {
2366         if (x86_pmu.check_microcode)
2367                 x86_pmu.check_microcode();
2368 }
2369
2370 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2371 {
2372         if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2373                 return -EINVAL;
2374
2375         if (value && x86_pmu.limit_period) {
2376                 if (x86_pmu.limit_period(event, value) > value)
2377                         return -EINVAL;
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int x86_pmu_aux_output_match(struct perf_event *event)
2384 {
2385         if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2386                 return 0;
2387
2388         if (x86_pmu.aux_output_match)
2389                 return x86_pmu.aux_output_match(event);
2390
2391         return 0;
2392 }
2393
2394 static struct pmu pmu = {
2395         .pmu_enable             = x86_pmu_enable,
2396         .pmu_disable            = x86_pmu_disable,
2397
2398         .attr_groups            = x86_pmu_attr_groups,
2399
2400         .event_init             = x86_pmu_event_init,
2401
2402         .event_mapped           = x86_pmu_event_mapped,
2403         .event_unmapped         = x86_pmu_event_unmapped,
2404
2405         .add                    = x86_pmu_add,
2406         .del                    = x86_pmu_del,
2407         .start                  = x86_pmu_start,
2408         .stop                   = x86_pmu_stop,
2409         .read                   = x86_pmu_read,
2410
2411         .start_txn              = x86_pmu_start_txn,
2412         .cancel_txn             = x86_pmu_cancel_txn,
2413         .commit_txn             = x86_pmu_commit_txn,
2414
2415         .event_idx              = x86_pmu_event_idx,
2416         .sched_task             = x86_pmu_sched_task,
2417         .swap_task_ctx          = x86_pmu_swap_task_ctx,
2418         .check_period           = x86_pmu_check_period,
2419
2420         .aux_output_match       = x86_pmu_aux_output_match,
2421 };
2422
2423 void arch_perf_update_userpage(struct perf_event *event,
2424                                struct perf_event_mmap_page *userpg, u64 now)
2425 {
2426         struct cyc2ns_data data;
2427         u64 offset;
2428
2429         userpg->cap_user_time = 0;
2430         userpg->cap_user_time_zero = 0;
2431         userpg->cap_user_rdpmc =
2432                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2433         userpg->pmc_width = x86_pmu.cntval_bits;
2434
2435         if (!using_native_sched_clock() || !sched_clock_stable())
2436                 return;
2437
2438         cyc2ns_read_begin(&data);
2439
2440         offset = data.cyc2ns_offset + __sched_clock_offset;
2441
2442         /*
2443          * Internal timekeeping for enabled/running/stopped times
2444          * is always in the local_clock domain.
2445          */
2446         userpg->cap_user_time = 1;
2447         userpg->time_mult = data.cyc2ns_mul;
2448         userpg->time_shift = data.cyc2ns_shift;
2449         userpg->time_offset = offset - now;
2450
2451         /*
2452          * cap_user_time_zero doesn't make sense when we're using a different
2453          * time base for the records.
2454          */
2455         if (!event->attr.use_clockid) {
2456                 userpg->cap_user_time_zero = 1;
2457                 userpg->time_zero = offset;
2458         }
2459
2460         cyc2ns_read_end();
2461 }
2462
2463 /*
2464  * Determine whether the regs were taken from an irq/exception handler rather
2465  * than from perf_arch_fetch_caller_regs().
2466  */
2467 static bool perf_hw_regs(struct pt_regs *regs)
2468 {
2469         return regs->flags & X86_EFLAGS_FIXED;
2470 }
2471
2472 void
2473 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2474 {
2475         struct unwind_state state;
2476         unsigned long addr;
2477
2478         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2479                 /* TODO: We don't support guest os callchain now */
2480                 return;
2481         }
2482
2483         if (perf_callchain_store(entry, regs->ip))
2484                 return;
2485
2486         if (perf_hw_regs(regs))
2487                 unwind_start(&state, current, regs, NULL);
2488         else
2489                 unwind_start(&state, current, NULL, (void *)regs->sp);
2490
2491         for (; !unwind_done(&state); unwind_next_frame(&state)) {
2492                 addr = unwind_get_return_address(&state);
2493                 if (!addr || perf_callchain_store(entry, addr))
2494                         return;
2495         }
2496 }
2497
2498 static inline int
2499 valid_user_frame(const void __user *fp, unsigned long size)
2500 {
2501         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2502 }
2503
2504 static unsigned long get_segment_base(unsigned int segment)
2505 {
2506         struct desc_struct *desc;
2507         unsigned int idx = segment >> 3;
2508
2509         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2510 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2511                 struct ldt_struct *ldt;
2512
2513                 /* IRQs are off, so this synchronizes with smp_store_release */
2514                 ldt = READ_ONCE(current->active_mm->context.ldt);
2515                 if (!ldt || idx >= ldt->nr_entries)
2516                         return 0;
2517
2518                 desc = &ldt->entries[idx];
2519 #else
2520                 return 0;
2521 #endif
2522         } else {
2523                 if (idx >= GDT_ENTRIES)
2524                         return 0;
2525
2526                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2527         }
2528
2529         return get_desc_base(desc);
2530 }
2531
2532 #ifdef CONFIG_IA32_EMULATION
2533
2534 #include <linux/compat.h>
2535
2536 static inline int
2537 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2538 {
2539         /* 32-bit process in 64-bit kernel. */
2540         unsigned long ss_base, cs_base;
2541         struct stack_frame_ia32 frame;
2542         const struct stack_frame_ia32 __user *fp;
2543
2544         if (!test_thread_flag(TIF_IA32))
2545                 return 0;
2546
2547         cs_base = get_segment_base(regs->cs);
2548         ss_base = get_segment_base(regs->ss);
2549
2550         fp = compat_ptr(ss_base + regs->bp);
2551         pagefault_disable();
2552         while (entry->nr < entry->max_stack) {
2553                 if (!valid_user_frame(fp, sizeof(frame)))
2554                         break;
2555
2556                 if (__get_user(frame.next_frame, &fp->next_frame))
2557                         break;
2558                 if (__get_user(frame.return_address, &fp->return_address))
2559                         break;
2560
2561                 perf_callchain_store(entry, cs_base + frame.return_address);
2562                 fp = compat_ptr(ss_base + frame.next_frame);
2563         }
2564         pagefault_enable();
2565         return 1;
2566 }
2567 #else
2568 static inline int
2569 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2570 {
2571     return 0;
2572 }
2573 #endif
2574
2575 void
2576 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2577 {
2578         struct stack_frame frame;
2579         const struct stack_frame __user *fp;
2580
2581         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2582                 /* TODO: We don't support guest os callchain now */
2583                 return;
2584         }
2585
2586         /*
2587          * We don't know what to do with VM86 stacks.. ignore them for now.
2588          */
2589         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2590                 return;
2591
2592         fp = (void __user *)regs->bp;
2593
2594         perf_callchain_store(entry, regs->ip);
2595
2596         if (!nmi_uaccess_okay())
2597                 return;
2598
2599         if (perf_callchain_user32(regs, entry))
2600                 return;
2601
2602         pagefault_disable();
2603         while (entry->nr < entry->max_stack) {
2604                 if (!valid_user_frame(fp, sizeof(frame)))
2605                         break;
2606
2607                 if (__get_user(frame.next_frame, &fp->next_frame))
2608                         break;
2609                 if (__get_user(frame.return_address, &fp->return_address))
2610                         break;
2611
2612                 perf_callchain_store(entry, frame.return_address);
2613                 fp = (void __user *)frame.next_frame;
2614         }
2615         pagefault_enable();
2616 }
2617
2618 /*
2619  * Deal with code segment offsets for the various execution modes:
2620  *
2621  *   VM86 - the good olde 16 bit days, where the linear address is
2622  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2623  *
2624  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2625  *          to figure out what the 32bit base address is.
2626  *
2627  *    X32 - has TIF_X32 set, but is running in x86_64
2628  *
2629  * X86_64 - CS,DS,SS,ES are all zero based.
2630  */
2631 static unsigned long code_segment_base(struct pt_regs *regs)
2632 {
2633         /*
2634          * For IA32 we look at the GDT/LDT segment base to convert the
2635          * effective IP to a linear address.
2636          */
2637
2638 #ifdef CONFIG_X86_32
2639         /*
2640          * If we are in VM86 mode, add the segment offset to convert to a
2641          * linear address.
2642          */
2643         if (regs->flags & X86_VM_MASK)
2644                 return 0x10 * regs->cs;
2645
2646         if (user_mode(regs) && regs->cs != __USER_CS)
2647                 return get_segment_base(regs->cs);
2648 #else
2649         if (user_mode(regs) && !user_64bit_mode(regs) &&
2650             regs->cs != __USER32_CS)
2651                 return get_segment_base(regs->cs);
2652 #endif
2653         return 0;
2654 }
2655
2656 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2657 {
2658         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2659                 return perf_guest_cbs->get_guest_ip();
2660
2661         return regs->ip + code_segment_base(regs);
2662 }
2663
2664 unsigned long perf_misc_flags(struct pt_regs *regs)
2665 {
2666         int misc = 0;
2667
2668         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2669                 if (perf_guest_cbs->is_user_mode())
2670                         misc |= PERF_RECORD_MISC_GUEST_USER;
2671                 else
2672                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2673         } else {
2674                 if (user_mode(regs))
2675                         misc |= PERF_RECORD_MISC_USER;
2676                 else
2677                         misc |= PERF_RECORD_MISC_KERNEL;
2678         }
2679
2680         if (regs->flags & PERF_EFLAGS_EXACT)
2681                 misc |= PERF_RECORD_MISC_EXACT_IP;
2682
2683         return misc;
2684 }
2685
2686 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2687 {
2688         cap->version            = x86_pmu.version;
2689         cap->num_counters_gp    = x86_pmu.num_counters;
2690         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2691         cap->bit_width_gp       = x86_pmu.cntval_bits;
2692         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2693         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2694         cap->events_mask_len    = x86_pmu.events_mask_len;
2695 }
2696 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);