2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_set_period, *x86_pmu.set_period);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_update, *x86_pmu.update);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_limit_period, *x86_pmu.limit_period);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
80 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
83 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
85 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
87 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
88 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
90 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
91 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
93 DEFINE_STATIC_CALL_NULL(x86_pmu_filter, *x86_pmu.filter);
96 * This one is magic, it will get called even when PMU init fails (because
97 * there is no PMU), in which case it should simply return NULL.
99 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
101 u64 __read_mostly hw_cache_event_ids
102 [PERF_COUNT_HW_CACHE_MAX]
103 [PERF_COUNT_HW_CACHE_OP_MAX]
104 [PERF_COUNT_HW_CACHE_RESULT_MAX];
105 u64 __read_mostly hw_cache_extra_regs
106 [PERF_COUNT_HW_CACHE_MAX]
107 [PERF_COUNT_HW_CACHE_OP_MAX]
108 [PERF_COUNT_HW_CACHE_RESULT_MAX];
111 * Propagate event elapsed time into the generic event.
112 * Can only be executed on the CPU where the event is active.
113 * Returns the delta events processed.
115 u64 x86_perf_event_update(struct perf_event *event)
117 struct hw_perf_event *hwc = &event->hw;
118 int shift = 64 - x86_pmu.cntval_bits;
119 u64 prev_raw_count, new_raw_count;
122 if (unlikely(!hwc->event_base))
126 * Careful: an NMI might modify the previous event value.
128 * Our tactic to handle this is to first atomically read and
129 * exchange a new raw count - then add that new-prev delta
130 * count to the generic event atomically:
133 prev_raw_count = local64_read(&hwc->prev_count);
134 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
136 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
137 new_raw_count) != prev_raw_count)
141 * Now we have the new raw value and have updated the prev
142 * timestamp already. We can now calculate the elapsed delta
143 * (event-)time and add that to the generic event.
145 * Careful, not all hw sign-extends above the physical width
148 delta = (new_raw_count << shift) - (prev_raw_count << shift);
151 local64_add(delta, &event->count);
152 local64_sub(delta, &hwc->period_left);
154 return new_raw_count;
158 * Find and validate any extra registers to set up.
160 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
162 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
163 struct hw_perf_event_extra *reg;
164 struct extra_reg *er;
166 reg = &event->hw.extra_reg;
171 for (er = extra_regs; er->msr; er++) {
172 if (er->event != (config & er->config_mask))
174 if (event->attr.config1 & ~er->valid_mask)
176 /* Check if the extra msrs can be safely accessed*/
177 if (!er->extra_msr_access)
181 reg->config = event->attr.config1;
188 static atomic_t active_events;
189 static atomic_t pmc_refcount;
190 static DEFINE_MUTEX(pmc_reserve_mutex);
192 #ifdef CONFIG_X86_LOCAL_APIC
194 static inline int get_possible_num_counters(void)
196 int i, num_counters = x86_pmu.num_counters;
201 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
202 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
207 static bool reserve_pmc_hardware(void)
209 int i, num_counters = get_possible_num_counters();
211 for (i = 0; i < num_counters; i++) {
212 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
216 for (i = 0; i < num_counters; i++) {
217 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
224 for (i--; i >= 0; i--)
225 release_evntsel_nmi(x86_pmu_config_addr(i));
230 for (i--; i >= 0; i--)
231 release_perfctr_nmi(x86_pmu_event_addr(i));
236 static void release_pmc_hardware(void)
238 int i, num_counters = get_possible_num_counters();
240 for (i = 0; i < num_counters; i++) {
241 release_perfctr_nmi(x86_pmu_event_addr(i));
242 release_evntsel_nmi(x86_pmu_config_addr(i));
248 static bool reserve_pmc_hardware(void) { return true; }
249 static void release_pmc_hardware(void) {}
253 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
255 u64 val, val_fail = -1, val_new= ~0;
256 int i, reg, reg_fail = -1, ret = 0;
261 * Check to see if the BIOS enabled any of the counters, if so
264 for (i = 0; i < num_counters; i++) {
265 reg = x86_pmu_config_addr(i);
266 ret = rdmsrl_safe(reg, &val);
269 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
278 if (num_counters_fixed) {
279 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
280 ret = rdmsrl_safe(reg, &val);
283 for (i = 0; i < num_counters_fixed; i++) {
284 if (fixed_counter_disabled(i, pmu))
286 if (val & (0x03ULL << i*4)) {
295 * If all the counters are enabled, the below test will always
296 * fail. The tools will also become useless in this scenario.
297 * Just fail and disable the hardware counters.
300 if (reg_safe == -1) {
306 * Read the current value, change it and read it back to see if it
307 * matches, this is needed to detect certain hardware emulators
308 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
310 reg = x86_pmu_event_addr(reg_safe);
311 if (rdmsrl_safe(reg, &val))
314 ret = wrmsrl_safe(reg, val);
315 ret |= rdmsrl_safe(reg, &val_new);
316 if (ret || val != val_new)
320 * We still allow the PMU driver to operate:
323 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
324 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
331 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
332 pr_cont("PMU not available due to virtualization, using software events only.\n");
334 pr_cont("Broken PMU hardware detected, using software events only.\n");
335 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
342 static void hw_perf_event_destroy(struct perf_event *event)
344 x86_release_hardware();
345 atomic_dec(&active_events);
348 void hw_perf_lbr_event_destroy(struct perf_event *event)
350 hw_perf_event_destroy(event);
352 /* undo the lbr/bts event accounting */
353 x86_del_exclusive(x86_lbr_exclusive_lbr);
356 static inline int x86_pmu_initialized(void)
358 return x86_pmu.handle_irq != NULL;
362 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
364 struct perf_event_attr *attr = &event->attr;
365 unsigned int cache_type, cache_op, cache_result;
368 config = attr->config;
370 cache_type = (config >> 0) & 0xff;
371 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
373 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
375 cache_op = (config >> 8) & 0xff;
376 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
378 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
380 cache_result = (config >> 16) & 0xff;
381 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
383 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
385 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
393 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
394 return x86_pmu_extra_regs(val, event);
397 int x86_reserve_hardware(void)
401 if (!atomic_inc_not_zero(&pmc_refcount)) {
402 mutex_lock(&pmc_reserve_mutex);
403 if (atomic_read(&pmc_refcount) == 0) {
404 if (!reserve_pmc_hardware()) {
407 reserve_ds_buffers();
408 reserve_lbr_buffers();
412 atomic_inc(&pmc_refcount);
413 mutex_unlock(&pmc_reserve_mutex);
419 void x86_release_hardware(void)
421 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
422 release_pmc_hardware();
423 release_ds_buffers();
424 release_lbr_buffers();
425 mutex_unlock(&pmc_reserve_mutex);
430 * Check if we can create event of a certain type (that no conflicting events
433 int x86_add_exclusive(unsigned int what)
438 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
439 * LBR and BTS are still mutually exclusive.
441 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
444 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
445 mutex_lock(&pmc_reserve_mutex);
446 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
447 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
450 atomic_inc(&x86_pmu.lbr_exclusive[what]);
451 mutex_unlock(&pmc_reserve_mutex);
455 atomic_inc(&active_events);
459 mutex_unlock(&pmc_reserve_mutex);
463 void x86_del_exclusive(unsigned int what)
465 atomic_dec(&active_events);
468 * See the comment in x86_add_exclusive().
470 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
473 atomic_dec(&x86_pmu.lbr_exclusive[what]);
476 int x86_setup_perfctr(struct perf_event *event)
478 struct perf_event_attr *attr = &event->attr;
479 struct hw_perf_event *hwc = &event->hw;
482 if (!is_sampling_event(event)) {
483 hwc->sample_period = x86_pmu.max_period;
484 hwc->last_period = hwc->sample_period;
485 local64_set(&hwc->period_left, hwc->sample_period);
488 if (attr->type == event->pmu->type)
489 return x86_pmu_extra_regs(event->attr.config, event);
491 if (attr->type == PERF_TYPE_HW_CACHE)
492 return set_ext_hw_attr(hwc, event);
494 if (attr->config >= x86_pmu.max_events)
497 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
502 config = x86_pmu.event_map(attr->config);
510 hwc->config |= config;
516 * check that branch_sample_type is compatible with
517 * settings needed for precise_ip > 1 which implies
518 * using the LBR to capture ALL taken branches at the
519 * priv levels of the measurement
521 static inline int precise_br_compat(struct perf_event *event)
523 u64 m = event->attr.branch_sample_type;
526 /* must capture all branches */
527 if (!(m & PERF_SAMPLE_BRANCH_ANY))
530 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
532 if (!event->attr.exclude_user)
533 b |= PERF_SAMPLE_BRANCH_USER;
535 if (!event->attr.exclude_kernel)
536 b |= PERF_SAMPLE_BRANCH_KERNEL;
539 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
545 int x86_pmu_max_precise(void)
549 /* Support for constant skid */
550 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
553 /* Support for IP fixup */
554 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
557 if (x86_pmu.pebs_prec_dist)
563 int x86_pmu_hw_config(struct perf_event *event)
565 if (event->attr.precise_ip) {
566 int precise = x86_pmu_max_precise();
568 if (event->attr.precise_ip > precise)
571 /* There's no sense in having PEBS for non sampling events: */
572 if (!is_sampling_event(event))
576 * check that PEBS LBR correction does not conflict with
577 * whatever the user is asking with attr->branch_sample_type
579 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
580 u64 *br_type = &event->attr.branch_sample_type;
582 if (has_branch_stack(event)) {
583 if (!precise_br_compat(event))
586 /* branch_sample_type is compatible */
590 * user did not specify branch_sample_type
592 * For PEBS fixups, we capture all
593 * the branches at the priv level of the
596 *br_type = PERF_SAMPLE_BRANCH_ANY;
598 if (!event->attr.exclude_user)
599 *br_type |= PERF_SAMPLE_BRANCH_USER;
601 if (!event->attr.exclude_kernel)
602 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
606 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
607 event->attach_state |= PERF_ATTACH_TASK_DATA;
611 * (keep 'enabled' bit clear for now)
613 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
616 * Count user and OS events unless requested not to
618 if (!event->attr.exclude_user)
619 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
620 if (!event->attr.exclude_kernel)
621 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
623 if (event->attr.type == event->pmu->type)
624 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
626 if (event->attr.sample_period && x86_pmu.limit_period) {
627 s64 left = event->attr.sample_period;
628 x86_pmu.limit_period(event, &left);
629 if (left > event->attr.sample_period)
633 /* sample_regs_user never support XMM registers */
634 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
637 * Besides the general purpose registers, XMM registers may
638 * be collected in PEBS on some platforms, e.g. Icelake
640 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
641 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
644 if (!event->attr.precise_ip)
648 return x86_setup_perfctr(event);
652 * Setup the hardware configuration for a given attr_type
654 static int __x86_pmu_event_init(struct perf_event *event)
658 if (!x86_pmu_initialized())
661 err = x86_reserve_hardware();
665 atomic_inc(&active_events);
666 event->destroy = hw_perf_event_destroy;
669 event->hw.last_cpu = -1;
670 event->hw.last_tag = ~0ULL;
673 event->hw.extra_reg.idx = EXTRA_REG_NONE;
674 event->hw.branch_reg.idx = EXTRA_REG_NONE;
676 return x86_pmu.hw_config(event);
679 void x86_pmu_disable_all(void)
681 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
684 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
685 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
688 if (!test_bit(idx, cpuc->active_mask))
690 rdmsrl(x86_pmu_config_addr(idx), val);
691 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
693 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
694 wrmsrl(x86_pmu_config_addr(idx), val);
695 if (is_counter_pair(hwc))
696 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
700 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
702 return static_call(x86_pmu_guest_get_msrs)(nr, data);
704 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
707 * There may be PMI landing after enabled=0. The PMI hitting could be before or
710 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
711 * It will not be re-enabled in the NMI handler again, because enabled=0. After
712 * handling the NMI, disable_all will be called, which will not change the
713 * state either. If PMI hits after disable_all, the PMU is already disabled
714 * before entering NMI handler. The NMI handler will not change the state
717 * So either situation is harmless.
719 static void x86_pmu_disable(struct pmu *pmu)
721 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
723 if (!x86_pmu_initialized())
733 static_call(x86_pmu_disable_all)();
736 void x86_pmu_enable_all(int added)
738 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
741 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
742 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
744 if (!test_bit(idx, cpuc->active_mask))
747 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
751 static inline int is_x86_event(struct perf_event *event)
756 return event->pmu == &pmu;
758 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
759 if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
766 struct pmu *x86_get_pmu(unsigned int cpu)
768 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
771 * All CPUs of the hybrid type have been offline.
772 * The x86_get_pmu() should not be invoked.
774 if (WARN_ON_ONCE(!cpuc->pmu))
780 * Event scheduler state:
782 * Assign events iterating over all events and counters, beginning
783 * with events with least weights first. Keep the current iterator
784 * state in struct sched_state.
788 int event; /* event index */
789 int counter; /* counter index */
790 int unassigned; /* number of events to be assigned left */
791 int nr_gp; /* number of GP counters used */
795 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
796 #define SCHED_STATES_MAX 2
803 struct event_constraint **constraints;
804 struct sched_state state;
805 struct sched_state saved[SCHED_STATES_MAX];
809 * Initialize iterator that runs through all events and counters.
811 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
812 int num, int wmin, int wmax, int gpmax)
816 memset(sched, 0, sizeof(*sched));
817 sched->max_events = num;
818 sched->max_weight = wmax;
819 sched->max_gp = gpmax;
820 sched->constraints = constraints;
822 for (idx = 0; idx < num; idx++) {
823 if (constraints[idx]->weight == wmin)
827 sched->state.event = idx; /* start with min weight */
828 sched->state.weight = wmin;
829 sched->state.unassigned = num;
832 static void perf_sched_save_state(struct perf_sched *sched)
834 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
837 sched->saved[sched->saved_states] = sched->state;
838 sched->saved_states++;
841 static bool perf_sched_restore_state(struct perf_sched *sched)
843 if (!sched->saved_states)
846 sched->saved_states--;
847 sched->state = sched->saved[sched->saved_states];
849 /* this assignment didn't work out */
850 /* XXX broken vs EVENT_PAIR */
851 sched->state.used &= ~BIT_ULL(sched->state.counter);
853 /* try the next one */
854 sched->state.counter++;
860 * Select a counter for the current event to schedule. Return true on
863 static bool __perf_sched_find_counter(struct perf_sched *sched)
865 struct event_constraint *c;
868 if (!sched->state.unassigned)
871 if (sched->state.event >= sched->max_events)
874 c = sched->constraints[sched->state.event];
875 /* Prefer fixed purpose counters */
876 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
877 idx = INTEL_PMC_IDX_FIXED;
878 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
879 u64 mask = BIT_ULL(idx);
881 if (sched->state.used & mask)
884 sched->state.used |= mask;
889 /* Grab the first unused counter starting with idx */
890 idx = sched->state.counter;
891 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
892 u64 mask = BIT_ULL(idx);
894 if (c->flags & PERF_X86_EVENT_PAIR)
897 if (sched->state.used & mask)
900 if (sched->state.nr_gp++ >= sched->max_gp)
903 sched->state.used |= mask;
910 sched->state.counter = idx;
913 perf_sched_save_state(sched);
918 static bool perf_sched_find_counter(struct perf_sched *sched)
920 while (!__perf_sched_find_counter(sched)) {
921 if (!perf_sched_restore_state(sched))
929 * Go through all unassigned events and find the next one to schedule.
930 * Take events with the least weight first. Return true on success.
932 static bool perf_sched_next_event(struct perf_sched *sched)
934 struct event_constraint *c;
936 if (!sched->state.unassigned || !--sched->state.unassigned)
941 sched->state.event++;
942 if (sched->state.event >= sched->max_events) {
944 sched->state.event = 0;
945 sched->state.weight++;
946 if (sched->state.weight > sched->max_weight)
949 c = sched->constraints[sched->state.event];
950 } while (c->weight != sched->state.weight);
952 sched->state.counter = 0; /* start with first counter */
958 * Assign a counter for each event.
960 int perf_assign_events(struct event_constraint **constraints, int n,
961 int wmin, int wmax, int gpmax, int *assign)
963 struct perf_sched sched;
965 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
968 if (!perf_sched_find_counter(&sched))
971 assign[sched.state.event] = sched.state.counter;
972 } while (perf_sched_next_event(&sched));
974 return sched.state.unassigned;
976 EXPORT_SYMBOL_GPL(perf_assign_events);
978 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
980 int num_counters = hybrid(cpuc->pmu, num_counters);
981 struct event_constraint *c;
982 struct perf_event *e;
983 int n0, i, wmin, wmax, unsched = 0;
984 struct hw_perf_event *hwc;
988 * Compute the number of events already present; see x86_pmu_add(),
989 * validate_group() and x86_pmu_commit_txn(). For the former two
990 * cpuc->n_events hasn't been updated yet, while for the latter
991 * cpuc->n_txn contains the number of events added in the current
995 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
998 static_call_cond(x86_pmu_start_scheduling)(cpuc);
1000 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
1001 c = cpuc->event_constraint[i];
1004 * Previously scheduled events should have a cached constraint,
1005 * while new events should not have one.
1007 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1010 * Request constraints for new events; or for those events that
1011 * have a dynamic constraint -- for those the constraint can
1012 * change due to external factors (sibling state, allow_tfa).
1014 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1015 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1016 cpuc->event_constraint[i] = c;
1019 wmin = min(wmin, c->weight);
1020 wmax = max(wmax, c->weight);
1024 * fastpath, try to reuse previous register
1026 for (i = 0; i < n; i++) {
1029 hwc = &cpuc->event_list[i]->hw;
1030 c = cpuc->event_constraint[i];
1032 /* never assigned */
1036 /* constraint still honored */
1037 if (!test_bit(hwc->idx, c->idxmsk))
1040 mask = BIT_ULL(hwc->idx);
1041 if (is_counter_pair(hwc))
1044 /* not already used */
1045 if (used_mask & mask)
1051 assign[i] = hwc->idx;
1056 int gpmax = num_counters;
1059 * Do not allow scheduling of more than half the available
1062 * This helps avoid counter starvation of sibling thread by
1063 * ensuring at most half the counters cannot be in exclusive
1064 * mode. There is no designated counters for the limits. Any
1065 * N/2 counters can be used. This helps with events with
1066 * specific counter constraints.
1068 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1069 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1073 * Reduce the amount of available counters to allow fitting
1074 * the extra Merge events needed by large increment events.
1076 if (x86_pmu.flags & PMU_FL_PAIR) {
1077 gpmax = num_counters - cpuc->n_pair;
1078 WARN_ON(gpmax <= 0);
1081 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1082 wmax, gpmax, assign);
1086 * In case of success (unsched = 0), mark events as committed,
1087 * so we do not put_constraint() in case new events are added
1088 * and fail to be scheduled
1090 * We invoke the lower level commit callback to lock the resource
1092 * We do not need to do all of this in case we are called to
1093 * validate an event group (assign == NULL)
1095 if (!unsched && assign) {
1096 for (i = 0; i < n; i++)
1097 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1099 for (i = n0; i < n; i++) {
1100 e = cpuc->event_list[i];
1103 * release events that failed scheduling
1105 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1107 cpuc->event_constraint[i] = NULL;
1111 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1113 return unsched ? -EINVAL : 0;
1116 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1117 struct perf_event *event)
1119 if (is_metric_event(event)) {
1120 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1123 cpuc->n_txn_metric++;
1129 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1130 struct perf_event *event)
1132 if (is_metric_event(event))
1136 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1137 int max_count, int n)
1139 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1141 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1144 if (n >= max_count + cpuc->n_metric)
1147 cpuc->event_list[n] = event;
1148 if (is_counter_pair(&event->hw)) {
1157 * dogrp: true if must collect siblings events (group)
1158 * returns total number of events and error code
1160 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1162 int num_counters = hybrid(cpuc->pmu, num_counters);
1163 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1164 struct perf_event *event;
1167 max_count = num_counters + num_counters_fixed;
1169 /* current number of events already accepted */
1171 if (!cpuc->n_events)
1172 cpuc->pebs_output = 0;
1174 if (!cpuc->is_fake && leader->attr.precise_ip) {
1176 * For PEBS->PT, if !aux_event, the group leader (PT) went
1177 * away, the group was broken down and this singleton event
1178 * can't schedule any more.
1180 if (is_pebs_pt(leader) && !leader->aux_event)
1184 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1186 if (cpuc->pebs_output &&
1187 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1190 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1193 if (is_x86_event(leader)) {
1194 if (collect_event(cpuc, leader, max_count, n))
1202 for_each_sibling_event(event, leader) {
1203 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1206 if (collect_event(cpuc, event, max_count, n))
1214 static inline void x86_assign_hw_event(struct perf_event *event,
1215 struct cpu_hw_events *cpuc, int i)
1217 struct hw_perf_event *hwc = &event->hw;
1220 idx = hwc->idx = cpuc->assign[i];
1221 hwc->last_cpu = smp_processor_id();
1222 hwc->last_tag = ++cpuc->tags[i];
1224 static_call_cond(x86_pmu_assign)(event, idx);
1227 case INTEL_PMC_IDX_FIXED_BTS:
1228 case INTEL_PMC_IDX_FIXED_VLBR:
1229 hwc->config_base = 0;
1230 hwc->event_base = 0;
1233 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1234 /* All the metric events are mapped onto the fixed counter 3. */
1235 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1237 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1238 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1239 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1240 (idx - INTEL_PMC_IDX_FIXED);
1241 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1242 INTEL_PMC_FIXED_RDPMC_BASE;
1246 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1247 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1248 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1254 * x86_perf_rdpmc_index - Return PMC counter used for event
1255 * @event: the perf_event to which the PMC counter was assigned
1257 * The counter assigned to this performance event may change if interrupts
1258 * are enabled. This counter should thus never be used while interrupts are
1259 * enabled. Before this function is used to obtain the assigned counter the
1260 * event should be checked for validity using, for example,
1261 * perf_event_read_local(), within the same interrupt disabled section in
1262 * which this counter is planned to be used.
1264 * Return: The index of the performance monitoring counter assigned to
1267 int x86_perf_rdpmc_index(struct perf_event *event)
1269 lockdep_assert_irqs_disabled();
1271 return event->hw.event_base_rdpmc;
1274 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1275 struct cpu_hw_events *cpuc,
1278 return hwc->idx == cpuc->assign[i] &&
1279 hwc->last_cpu == smp_processor_id() &&
1280 hwc->last_tag == cpuc->tags[i];
1283 static void x86_pmu_start(struct perf_event *event, int flags);
1285 static void x86_pmu_enable(struct pmu *pmu)
1287 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1288 struct perf_event *event;
1289 struct hw_perf_event *hwc;
1290 int i, added = cpuc->n_added;
1292 if (!x86_pmu_initialized())
1298 if (cpuc->n_added) {
1299 int n_running = cpuc->n_events - cpuc->n_added;
1301 * apply assignment obtained either from
1302 * hw_perf_group_sched_in() or x86_pmu_enable()
1304 * step1: save events moving to new counters
1306 for (i = 0; i < n_running; i++) {
1307 event = cpuc->event_list[i];
1311 * we can avoid reprogramming counter if:
1312 * - assigned same counter as last time
1313 * - running on same CPU as last time
1314 * - no other event has used the counter since
1316 if (hwc->idx == -1 ||
1317 match_prev_assignment(hwc, cpuc, i))
1321 * Ensure we don't accidentally enable a stopped
1322 * counter simply because we rescheduled.
1324 if (hwc->state & PERF_HES_STOPPED)
1325 hwc->state |= PERF_HES_ARCH;
1327 x86_pmu_stop(event, PERF_EF_UPDATE);
1331 * step2: reprogram moved events into new counters
1333 for (i = 0; i < cpuc->n_events; i++) {
1334 event = cpuc->event_list[i];
1337 if (!match_prev_assignment(hwc, cpuc, i))
1338 x86_assign_hw_event(event, cpuc, i);
1339 else if (i < n_running)
1342 if (hwc->state & PERF_HES_ARCH)
1346 * if cpuc->enabled = 0, then no wrmsr as
1347 * per x86_pmu_enable_event()
1349 x86_pmu_start(event, PERF_EF_RELOAD);
1352 perf_events_lapic_init();
1358 static_call(x86_pmu_enable_all)(added);
1361 DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1364 * Set the next IRQ period, based on the hwc->period_left value.
1365 * To be called with the event disabled in hw:
1367 int x86_perf_event_set_period(struct perf_event *event)
1369 struct hw_perf_event *hwc = &event->hw;
1370 s64 left = local64_read(&hwc->period_left);
1371 s64 period = hwc->sample_period;
1372 int ret = 0, idx = hwc->idx;
1374 if (unlikely(!hwc->event_base))
1378 * If we are way outside a reasonable range then just skip forward:
1380 if (unlikely(left <= -period)) {
1382 local64_set(&hwc->period_left, left);
1383 hwc->last_period = period;
1387 if (unlikely(left <= 0)) {
1389 local64_set(&hwc->period_left, left);
1390 hwc->last_period = period;
1394 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1396 if (unlikely(left < 2))
1399 if (left > x86_pmu.max_period)
1400 left = x86_pmu.max_period;
1402 static_call_cond(x86_pmu_limit_period)(event, &left);
1404 this_cpu_write(pmc_prev_left[idx], left);
1407 * The hw event starts counting from this event offset,
1408 * mark it to be able to extra future deltas:
1410 local64_set(&hwc->prev_count, (u64)-left);
1412 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1415 * Sign extend the Merge event counter's upper 16 bits since
1416 * we currently declare a 48-bit counter width
1418 if (is_counter_pair(hwc))
1419 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1421 perf_event_update_userpage(event);
1426 void x86_pmu_enable_event(struct perf_event *event)
1428 if (__this_cpu_read(cpu_hw_events.enabled))
1429 __x86_pmu_enable_event(&event->hw,
1430 ARCH_PERFMON_EVENTSEL_ENABLE);
1434 * Add a single event to the PMU.
1436 * The event is added to the group of enabled events
1437 * but only if it can be scheduled with existing events.
1439 static int x86_pmu_add(struct perf_event *event, int flags)
1441 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1442 struct hw_perf_event *hwc;
1443 int assign[X86_PMC_IDX_MAX];
1448 n0 = cpuc->n_events;
1449 ret = n = collect_events(cpuc, event, false);
1453 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1454 if (!(flags & PERF_EF_START))
1455 hwc->state |= PERF_HES_ARCH;
1458 * If group events scheduling transaction was started,
1459 * skip the schedulability test here, it will be performed
1460 * at commit time (->commit_txn) as a whole.
1462 * If commit fails, we'll call ->del() on all events
1463 * for which ->add() was called.
1465 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1468 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1472 * copy new assignment, now we know it is possible
1473 * will be used by hw_perf_enable()
1475 memcpy(cpuc->assign, assign, n*sizeof(int));
1479 * Commit the collect_events() state. See x86_pmu_del() and
1483 cpuc->n_added += n - n0;
1484 cpuc->n_txn += n - n0;
1487 * This is before x86_pmu_enable() will call x86_pmu_start(),
1488 * so we enable LBRs before an event needs them etc..
1490 static_call_cond(x86_pmu_add)(event);
1497 static void x86_pmu_start(struct perf_event *event, int flags)
1499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1500 int idx = event->hw.idx;
1502 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1505 if (WARN_ON_ONCE(idx == -1))
1508 if (flags & PERF_EF_RELOAD) {
1509 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1510 static_call(x86_pmu_set_period)(event);
1513 event->hw.state = 0;
1515 cpuc->events[idx] = event;
1516 __set_bit(idx, cpuc->active_mask);
1517 static_call(x86_pmu_enable)(event);
1518 perf_event_update_userpage(event);
1521 void perf_event_print_debug(void)
1523 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1525 int cpu = smp_processor_id();
1526 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1527 int num_counters = hybrid(cpuc->pmu, num_counters);
1528 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1529 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1530 unsigned long flags;
1536 local_irq_save(flags);
1538 if (x86_pmu.version >= 2) {
1539 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1540 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1541 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1542 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1545 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1546 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1547 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1548 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1549 if (pebs_constraints) {
1550 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1551 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1553 if (x86_pmu.lbr_nr) {
1554 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1555 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1558 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1560 for (idx = 0; idx < num_counters; idx++) {
1561 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1562 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1564 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1566 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1567 cpu, idx, pmc_ctrl);
1568 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1569 cpu, idx, pmc_count);
1570 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1571 cpu, idx, prev_left);
1573 for (idx = 0; idx < num_counters_fixed; idx++) {
1574 if (fixed_counter_disabled(idx, cpuc->pmu))
1576 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1578 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1579 cpu, idx, pmc_count);
1581 local_irq_restore(flags);
1584 void x86_pmu_stop(struct perf_event *event, int flags)
1586 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1587 struct hw_perf_event *hwc = &event->hw;
1589 if (test_bit(hwc->idx, cpuc->active_mask)) {
1590 static_call(x86_pmu_disable)(event);
1591 __clear_bit(hwc->idx, cpuc->active_mask);
1592 cpuc->events[hwc->idx] = NULL;
1593 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1594 hwc->state |= PERF_HES_STOPPED;
1597 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1599 * Drain the remaining delta count out of a event
1600 * that we are disabling:
1602 static_call(x86_pmu_update)(event);
1603 hwc->state |= PERF_HES_UPTODATE;
1607 static void x86_pmu_del(struct perf_event *event, int flags)
1609 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1610 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1614 * If we're called during a txn, we only need to undo x86_pmu.add.
1615 * The events never got scheduled and ->cancel_txn will truncate
1618 * XXX assumes any ->del() called during a TXN will only be on
1619 * an event added during that same TXN.
1621 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1624 __set_bit(event->hw.idx, cpuc->dirty);
1627 * Not a TXN, therefore cleanup properly.
1629 x86_pmu_stop(event, PERF_EF_UPDATE);
1631 for (i = 0; i < cpuc->n_events; i++) {
1632 if (event == cpuc->event_list[i])
1636 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1639 /* If we have a newly added event; make sure to decrease n_added. */
1640 if (i >= cpuc->n_events - cpuc->n_added)
1643 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1645 /* Delete the array entry. */
1646 while (++i < cpuc->n_events) {
1647 cpuc->event_list[i-1] = cpuc->event_list[i];
1648 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1650 cpuc->event_constraint[i-1] = NULL;
1652 if (intel_cap.perf_metrics)
1653 del_nr_metric_event(cpuc, event);
1655 perf_event_update_userpage(event);
1660 * This is after x86_pmu_stop(); so we disable LBRs after any
1661 * event can need them etc..
1663 static_call_cond(x86_pmu_del)(event);
1666 int x86_pmu_handle_irq(struct pt_regs *regs)
1668 struct perf_sample_data data;
1669 struct cpu_hw_events *cpuc;
1670 struct perf_event *event;
1671 int idx, handled = 0;
1674 cpuc = this_cpu_ptr(&cpu_hw_events);
1677 * Some chipsets need to unmask the LVTPC in a particular spot
1678 * inside the nmi handler. As a result, the unmasking was pushed
1679 * into all the nmi handlers.
1681 * This generic handler doesn't seem to have any issues where the
1682 * unmasking occurs so it was left at the top.
1684 apic_write(APIC_LVTPC, APIC_DM_NMI);
1686 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1687 if (!test_bit(idx, cpuc->active_mask))
1690 event = cpuc->events[idx];
1692 val = static_call(x86_pmu_update)(event);
1693 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1701 if (!static_call(x86_pmu_set_period)(event))
1704 perf_sample_data_init(&data, 0, event->hw.last_period);
1706 if (has_branch_stack(event)) {
1707 data.br_stack = &cpuc->lbr_stack;
1708 data.sample_flags |= PERF_SAMPLE_BRANCH_STACK;
1711 if (perf_event_overflow(event, &data, regs))
1712 x86_pmu_stop(event, 0);
1716 inc_irq_stat(apic_perf_irqs);
1721 void perf_events_lapic_init(void)
1723 if (!x86_pmu.apic || !x86_pmu_initialized())
1727 * Always use NMI for PMU
1729 apic_write(APIC_LVTPC, APIC_DM_NMI);
1733 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1740 * All PMUs/events that share this PMI handler should make sure to
1741 * increment active_events for their events.
1743 if (!atomic_read(&active_events))
1746 start_clock = sched_clock();
1747 ret = static_call(x86_pmu_handle_irq)(regs);
1748 finish_clock = sched_clock();
1750 perf_sample_event_took(finish_clock - start_clock);
1754 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1756 struct event_constraint emptyconstraint;
1757 struct event_constraint unconstrained;
1759 static int x86_pmu_prepare_cpu(unsigned int cpu)
1761 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1764 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1765 cpuc->kfree_on_online[i] = NULL;
1766 if (x86_pmu.cpu_prepare)
1767 return x86_pmu.cpu_prepare(cpu);
1771 static int x86_pmu_dead_cpu(unsigned int cpu)
1773 if (x86_pmu.cpu_dead)
1774 x86_pmu.cpu_dead(cpu);
1778 static int x86_pmu_online_cpu(unsigned int cpu)
1780 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1783 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1784 kfree(cpuc->kfree_on_online[i]);
1785 cpuc->kfree_on_online[i] = NULL;
1790 static int x86_pmu_starting_cpu(unsigned int cpu)
1792 if (x86_pmu.cpu_starting)
1793 x86_pmu.cpu_starting(cpu);
1797 static int x86_pmu_dying_cpu(unsigned int cpu)
1799 if (x86_pmu.cpu_dying)
1800 x86_pmu.cpu_dying(cpu);
1804 static void __init pmu_check_apic(void)
1806 if (boot_cpu_has(X86_FEATURE_APIC))
1810 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1811 pr_info("no hardware sampling interrupt available.\n");
1814 * If we have a PMU initialized but no APIC
1815 * interrupts, we cannot sample hardware
1816 * events (user-space has to fall back and
1817 * sample via a hrtimer based software event):
1819 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1823 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1828 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1830 struct perf_pmu_events_attr *pmu_attr =
1831 container_of(attr, struct perf_pmu_events_attr, attr);
1834 if (pmu_attr->id < x86_pmu.max_events)
1835 config = x86_pmu.event_map(pmu_attr->id);
1837 /* string trumps id */
1838 if (pmu_attr->event_str)
1839 return sprintf(page, "%s\n", pmu_attr->event_str);
1841 return x86_pmu.events_sysfs_show(page, config);
1843 EXPORT_SYMBOL_GPL(events_sysfs_show);
1845 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1848 struct perf_pmu_events_ht_attr *pmu_attr =
1849 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1852 * Report conditional events depending on Hyper-Threading.
1854 * This is overly conservative as usually the HT special
1855 * handling is not needed if the other CPU thread is idle.
1857 * Note this does not (and cannot) handle the case when thread
1858 * siblings are invisible, for example with virtualization
1859 * if they are owned by some other guest. The user tool
1860 * has to re-read when a thread sibling gets onlined later.
1862 return sprintf(page, "%s",
1863 topology_max_smt_threads() > 1 ?
1864 pmu_attr->event_str_ht :
1865 pmu_attr->event_str_noht);
1868 ssize_t events_hybrid_sysfs_show(struct device *dev,
1869 struct device_attribute *attr,
1872 struct perf_pmu_events_hybrid_attr *pmu_attr =
1873 container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1874 struct x86_hybrid_pmu *pmu;
1875 const char *str, *next_str;
1878 if (hweight64(pmu_attr->pmu_type) == 1)
1879 return sprintf(page, "%s", pmu_attr->event_str);
1882 * Hybrid PMUs may support the same event name, but with different
1883 * event encoding, e.g., the mem-loads event on an Atom PMU has
1884 * different event encoding from a Core PMU.
1886 * The event_str includes all event encodings. Each event encoding
1887 * is divided by ";". The order of the event encodings must follow
1888 * the order of the hybrid PMU index.
1890 pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1892 str = pmu_attr->event_str;
1893 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1894 if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1896 if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1897 next_str = strchr(str, ';');
1899 return snprintf(page, next_str - str + 1, "%s", str);
1901 return sprintf(page, "%s", str);
1903 str = strchr(str, ';');
1909 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1911 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1912 EVENT_ATTR(instructions, INSTRUCTIONS );
1913 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1914 EVENT_ATTR(cache-misses, CACHE_MISSES );
1915 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1916 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1917 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1918 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1919 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1920 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1922 static struct attribute *empty_attrs;
1924 static struct attribute *events_attr[] = {
1925 EVENT_PTR(CPU_CYCLES),
1926 EVENT_PTR(INSTRUCTIONS),
1927 EVENT_PTR(CACHE_REFERENCES),
1928 EVENT_PTR(CACHE_MISSES),
1929 EVENT_PTR(BRANCH_INSTRUCTIONS),
1930 EVENT_PTR(BRANCH_MISSES),
1931 EVENT_PTR(BUS_CYCLES),
1932 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1933 EVENT_PTR(STALLED_CYCLES_BACKEND),
1934 EVENT_PTR(REF_CPU_CYCLES),
1939 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1940 * out of events_attr attributes.
1943 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1945 struct perf_pmu_events_attr *pmu_attr;
1947 if (idx >= x86_pmu.max_events)
1950 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1952 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1955 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1957 .attrs = events_attr,
1958 .is_visible = is_visible,
1961 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1963 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1964 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1965 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1966 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1967 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1968 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1972 * We have whole page size to spend and just little data
1973 * to write, so we can safely use sprintf.
1975 ret = sprintf(page, "event=0x%02llx", event);
1978 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1981 ret += sprintf(page + ret, ",edge");
1984 ret += sprintf(page + ret, ",pc");
1987 ret += sprintf(page + ret, ",any");
1990 ret += sprintf(page + ret, ",inv");
1993 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1995 ret += sprintf(page + ret, "\n");
2000 static struct attribute_group x86_pmu_attr_group;
2001 static struct attribute_group x86_pmu_caps_group;
2003 static void x86_pmu_static_call_update(void)
2005 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2006 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2007 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2008 static_call_update(x86_pmu_enable, x86_pmu.enable);
2009 static_call_update(x86_pmu_disable, x86_pmu.disable);
2011 static_call_update(x86_pmu_assign, x86_pmu.assign);
2013 static_call_update(x86_pmu_add, x86_pmu.add);
2014 static_call_update(x86_pmu_del, x86_pmu.del);
2015 static_call_update(x86_pmu_read, x86_pmu.read);
2017 static_call_update(x86_pmu_set_period, x86_pmu.set_period);
2018 static_call_update(x86_pmu_update, x86_pmu.update);
2019 static_call_update(x86_pmu_limit_period, x86_pmu.limit_period);
2021 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2022 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2023 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2025 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2026 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2027 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2029 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2030 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2032 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2033 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2035 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2036 static_call_update(x86_pmu_filter, x86_pmu.filter);
2039 static void _x86_pmu_read(struct perf_event *event)
2041 static_call(x86_pmu_update)(event);
2044 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2047 pr_info("... version: %d\n", x86_pmu.version);
2048 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2049 pr_info("... generic registers: %d\n", num_counters);
2050 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2051 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2052 pr_info("... fixed-purpose events: %lu\n",
2053 hweight64((((1ULL << num_counters_fixed) - 1)
2054 << INTEL_PMC_IDX_FIXED) & intel_ctrl));
2055 pr_info("... event mask: %016Lx\n", intel_ctrl);
2058 static int __init init_hw_perf_events(void)
2060 struct x86_pmu_quirk *quirk;
2063 pr_info("Performance Events: ");
2065 switch (boot_cpu_data.x86_vendor) {
2066 case X86_VENDOR_INTEL:
2067 err = intel_pmu_init();
2069 case X86_VENDOR_AMD:
2070 err = amd_pmu_init();
2072 case X86_VENDOR_HYGON:
2073 err = amd_pmu_init();
2074 x86_pmu.name = "HYGON";
2076 case X86_VENDOR_ZHAOXIN:
2077 case X86_VENDOR_CENTAUR:
2078 err = zhaoxin_pmu_init();
2084 pr_cont("no PMU driver, software events only.\n");
2091 /* sanity check that the hardware exists or is emulated */
2092 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2095 pr_cont("%s PMU driver.\n", x86_pmu.name);
2097 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2099 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2102 if (!x86_pmu.intel_ctrl)
2103 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2105 perf_events_lapic_init();
2106 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2108 unconstrained = (struct event_constraint)
2109 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2110 0, x86_pmu.num_counters, 0, 0);
2112 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2114 if (!x86_pmu.events_sysfs_show)
2115 x86_pmu_events_group.attrs = &empty_attrs;
2117 pmu.attr_update = x86_pmu.attr_update;
2120 x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2121 x86_pmu.num_counters_fixed,
2122 x86_pmu.intel_ctrl);
2126 x86_pmu.read = _x86_pmu_read;
2128 if (!x86_pmu.guest_get_msrs)
2129 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2131 if (!x86_pmu.set_period)
2132 x86_pmu.set_period = x86_perf_event_set_period;
2134 if (!x86_pmu.update)
2135 x86_pmu.update = x86_perf_event_update;
2137 x86_pmu_static_call_update();
2140 * Install callbacks. Core will call them for each online
2143 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2144 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2148 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2149 "perf/x86:starting", x86_pmu_starting_cpu,
2154 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2155 x86_pmu_online_cpu, NULL);
2160 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2164 struct x86_hybrid_pmu *hybrid_pmu;
2167 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2168 hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2170 hybrid_pmu->pmu = pmu;
2171 hybrid_pmu->pmu.type = -1;
2172 hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2173 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
2174 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2176 err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2177 (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2182 if (i < x86_pmu.num_hybrid_pmus) {
2183 for (j = 0; j < i; j++)
2184 perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2185 pr_warn("Failed to register hybrid PMUs\n");
2186 kfree(x86_pmu.hybrid_pmu);
2187 x86_pmu.hybrid_pmu = NULL;
2188 x86_pmu.num_hybrid_pmus = 0;
2196 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2198 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2200 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2202 memset(&x86_pmu, 0, sizeof(x86_pmu));
2205 early_initcall(init_hw_perf_events);
2207 static void x86_pmu_read(struct perf_event *event)
2209 static_call(x86_pmu_read)(event);
2213 * Start group events scheduling transaction
2214 * Set the flag to make pmu::enable() not perform the
2215 * schedulability test, it will be performed at commit time
2217 * We only support PERF_PMU_TXN_ADD transactions. Save the
2218 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2221 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2223 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2225 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2227 cpuc->txn_flags = txn_flags;
2228 if (txn_flags & ~PERF_PMU_TXN_ADD)
2231 perf_pmu_disable(pmu);
2232 __this_cpu_write(cpu_hw_events.n_txn, 0);
2233 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2234 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2238 * Stop group events scheduling transaction
2239 * Clear the flag and pmu::enable() will perform the
2240 * schedulability test.
2242 static void x86_pmu_cancel_txn(struct pmu *pmu)
2244 unsigned int txn_flags;
2245 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2247 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2249 txn_flags = cpuc->txn_flags;
2250 cpuc->txn_flags = 0;
2251 if (txn_flags & ~PERF_PMU_TXN_ADD)
2255 * Truncate collected array by the number of events added in this
2256 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2258 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2259 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2260 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2261 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2262 perf_pmu_enable(pmu);
2266 * Commit group events scheduling transaction
2267 * Perform the group schedulability test as a whole
2268 * Return 0 if success
2270 * Does not cancel the transaction on failure; expects the caller to do this.
2272 static int x86_pmu_commit_txn(struct pmu *pmu)
2274 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2275 int assign[X86_PMC_IDX_MAX];
2278 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2280 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2281 cpuc->txn_flags = 0;
2287 if (!x86_pmu_initialized())
2290 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2295 * copy new assignment, now we know it is possible
2296 * will be used by hw_perf_enable()
2298 memcpy(cpuc->assign, assign, n*sizeof(int));
2300 cpuc->txn_flags = 0;
2301 perf_pmu_enable(pmu);
2305 * a fake_cpuc is used to validate event groups. Due to
2306 * the extra reg logic, we need to also allocate a fake
2307 * per_core and per_cpu structure. Otherwise, group events
2308 * using extra reg may conflict without the kernel being
2309 * able to catch this when the last event gets added to
2312 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2314 intel_cpuc_finish(cpuc);
2318 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2320 struct cpu_hw_events *cpuc;
2323 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2325 return ERR_PTR(-ENOMEM);
2329 struct x86_hybrid_pmu *h_pmu;
2331 h_pmu = hybrid_pmu(event_pmu);
2332 if (cpumask_empty(&h_pmu->supported_cpus))
2334 cpu = cpumask_first(&h_pmu->supported_cpus);
2336 cpu = raw_smp_processor_id();
2337 cpuc->pmu = event_pmu;
2339 if (intel_cpuc_prepare(cpuc, cpu))
2344 free_fake_cpuc(cpuc);
2345 return ERR_PTR(-ENOMEM);
2349 * validate that we can schedule this event
2351 static int validate_event(struct perf_event *event)
2353 struct cpu_hw_events *fake_cpuc;
2354 struct event_constraint *c;
2357 fake_cpuc = allocate_fake_cpuc(event->pmu);
2358 if (IS_ERR(fake_cpuc))
2359 return PTR_ERR(fake_cpuc);
2361 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2363 if (!c || !c->weight)
2366 if (x86_pmu.put_event_constraints)
2367 x86_pmu.put_event_constraints(fake_cpuc, event);
2369 free_fake_cpuc(fake_cpuc);
2375 * validate a single event group
2377 * validation include:
2378 * - check events are compatible which each other
2379 * - events do not compete for the same counter
2380 * - number of events <= number of counters
2382 * validation ensures the group can be loaded onto the
2383 * PMU if it was the only group available.
2385 static int validate_group(struct perf_event *event)
2387 struct perf_event *leader = event->group_leader;
2388 struct cpu_hw_events *fake_cpuc;
2389 int ret = -EINVAL, n;
2392 * Reject events from different hybrid PMUs.
2395 struct perf_event *sibling;
2396 struct pmu *pmu = NULL;
2398 if (is_x86_event(leader))
2401 for_each_sibling_event(sibling, leader) {
2402 if (!is_x86_event(sibling))
2406 else if (pmu != sibling->pmu)
2411 fake_cpuc = allocate_fake_cpuc(event->pmu);
2412 if (IS_ERR(fake_cpuc))
2413 return PTR_ERR(fake_cpuc);
2415 * the event is not yet connected with its
2416 * siblings therefore we must first collect
2417 * existing siblings, then add the new event
2418 * before we can simulate the scheduling
2420 n = collect_events(fake_cpuc, leader, true);
2424 fake_cpuc->n_events = n;
2425 n = collect_events(fake_cpuc, event, false);
2429 fake_cpuc->n_events = 0;
2430 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2433 free_fake_cpuc(fake_cpuc);
2437 static int x86_pmu_event_init(struct perf_event *event)
2439 struct x86_hybrid_pmu *pmu = NULL;
2442 if ((event->attr.type != event->pmu->type) &&
2443 (event->attr.type != PERF_TYPE_HARDWARE) &&
2444 (event->attr.type != PERF_TYPE_HW_CACHE))
2447 if (is_hybrid() && (event->cpu != -1)) {
2448 pmu = hybrid_pmu(event->pmu);
2449 if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2453 err = __x86_pmu_event_init(event);
2455 if (event->group_leader != event)
2456 err = validate_group(event);
2458 err = validate_event(event);
2462 event->destroy(event);
2463 event->destroy = NULL;
2466 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2467 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2468 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
2473 void perf_clear_dirty_counters(void)
2475 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2478 /* Don't need to clear the assigned counter. */
2479 for (i = 0; i < cpuc->n_events; i++)
2480 __clear_bit(cpuc->assign[i], cpuc->dirty);
2482 if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))
2485 for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2486 if (i >= INTEL_PMC_IDX_FIXED) {
2487 /* Metrics and fake events don't have corresponding HW counters. */
2488 if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2491 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
2493 wrmsrl(x86_pmu_event_addr(i), 0);
2497 bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
2500 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2502 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2506 * This function relies on not being called concurrently in two
2507 * tasks in the same mm. Otherwise one task could observe
2508 * perf_rdpmc_allowed > 1 and return all the way back to
2509 * userspace with CR4.PCE clear while another task is still
2510 * doing on_each_cpu_mask() to propagate CR4.PCE.
2512 * For now, this can't happen because all callers hold mmap_lock
2513 * for write. If this changes, we'll need a different solution.
2515 mmap_assert_write_locked(mm);
2517 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2518 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2521 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2523 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2526 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2527 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2530 static int x86_pmu_event_idx(struct perf_event *event)
2532 struct hw_perf_event *hwc = &event->hw;
2534 if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
2537 if (is_metric_idx(hwc->idx))
2538 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2540 return hwc->event_base_rdpmc + 1;
2543 static ssize_t get_attr_rdpmc(struct device *cdev,
2544 struct device_attribute *attr,
2547 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2550 static ssize_t set_attr_rdpmc(struct device *cdev,
2551 struct device_attribute *attr,
2552 const char *buf, size_t count)
2557 ret = kstrtoul(buf, 0, &val);
2564 if (x86_pmu.attr_rdpmc_broken)
2567 if (val != x86_pmu.attr_rdpmc) {
2569 * Changing into or out of never available or always available,
2570 * aka perf-event-bypassing mode. This path is extremely slow,
2571 * but only root can trigger it, so it's okay.
2574 static_branch_inc(&rdpmc_never_available_key);
2575 else if (x86_pmu.attr_rdpmc == 0)
2576 static_branch_dec(&rdpmc_never_available_key);
2579 static_branch_inc(&rdpmc_always_available_key);
2580 else if (x86_pmu.attr_rdpmc == 2)
2581 static_branch_dec(&rdpmc_always_available_key);
2583 on_each_cpu(cr4_update_pce, NULL, 1);
2584 x86_pmu.attr_rdpmc = val;
2590 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2592 static struct attribute *x86_pmu_attrs[] = {
2593 &dev_attr_rdpmc.attr,
2597 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2598 .attrs = x86_pmu_attrs,
2601 static ssize_t max_precise_show(struct device *cdev,
2602 struct device_attribute *attr,
2605 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2608 static DEVICE_ATTR_RO(max_precise);
2610 static struct attribute *x86_pmu_caps_attrs[] = {
2611 &dev_attr_max_precise.attr,
2615 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2617 .attrs = x86_pmu_caps_attrs,
2620 static const struct attribute_group *x86_pmu_attr_groups[] = {
2621 &x86_pmu_attr_group,
2622 &x86_pmu_format_group,
2623 &x86_pmu_events_group,
2624 &x86_pmu_caps_group,
2628 static void x86_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
2630 static_call_cond(x86_pmu_sched_task)(pmu_ctx, sched_in);
2633 static void x86_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
2634 struct perf_event_pmu_context *next_epc)
2636 static_call_cond(x86_pmu_swap_task_ctx)(prev_epc, next_epc);
2639 void perf_check_microcode(void)
2641 if (x86_pmu.check_microcode)
2642 x86_pmu.check_microcode();
2645 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2647 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2650 if (value && x86_pmu.limit_period) {
2652 x86_pmu.limit_period(event, &left);
2660 static int x86_pmu_aux_output_match(struct perf_event *event)
2662 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2665 if (x86_pmu.aux_output_match)
2666 return x86_pmu.aux_output_match(event);
2671 static bool x86_pmu_filter(struct pmu *pmu, int cpu)
2675 static_call_cond(x86_pmu_filter)(pmu, cpu, &ret);
2680 static struct pmu pmu = {
2681 .pmu_enable = x86_pmu_enable,
2682 .pmu_disable = x86_pmu_disable,
2684 .attr_groups = x86_pmu_attr_groups,
2686 .event_init = x86_pmu_event_init,
2688 .event_mapped = x86_pmu_event_mapped,
2689 .event_unmapped = x86_pmu_event_unmapped,
2693 .start = x86_pmu_start,
2694 .stop = x86_pmu_stop,
2695 .read = x86_pmu_read,
2697 .start_txn = x86_pmu_start_txn,
2698 .cancel_txn = x86_pmu_cancel_txn,
2699 .commit_txn = x86_pmu_commit_txn,
2701 .event_idx = x86_pmu_event_idx,
2702 .sched_task = x86_pmu_sched_task,
2703 .swap_task_ctx = x86_pmu_swap_task_ctx,
2704 .check_period = x86_pmu_check_period,
2706 .aux_output_match = x86_pmu_aux_output_match,
2708 .filter = x86_pmu_filter,
2711 void arch_perf_update_userpage(struct perf_event *event,
2712 struct perf_event_mmap_page *userpg, u64 now)
2714 struct cyc2ns_data data;
2717 userpg->cap_user_time = 0;
2718 userpg->cap_user_time_zero = 0;
2719 userpg->cap_user_rdpmc =
2720 !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
2721 userpg->pmc_width = x86_pmu.cntval_bits;
2723 if (!using_native_sched_clock() || !sched_clock_stable())
2726 cyc2ns_read_begin(&data);
2728 offset = data.cyc2ns_offset + __sched_clock_offset;
2731 * Internal timekeeping for enabled/running/stopped times
2732 * is always in the local_clock domain.
2734 userpg->cap_user_time = 1;
2735 userpg->time_mult = data.cyc2ns_mul;
2736 userpg->time_shift = data.cyc2ns_shift;
2737 userpg->time_offset = offset - now;
2740 * cap_user_time_zero doesn't make sense when we're using a different
2741 * time base for the records.
2743 if (!event->attr.use_clockid) {
2744 userpg->cap_user_time_zero = 1;
2745 userpg->time_zero = offset;
2752 * Determine whether the regs were taken from an irq/exception handler rather
2753 * than from perf_arch_fetch_caller_regs().
2755 static bool perf_hw_regs(struct pt_regs *regs)
2757 return regs->flags & X86_EFLAGS_FIXED;
2761 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2763 struct unwind_state state;
2766 if (perf_guest_state()) {
2767 /* TODO: We don't support guest os callchain now */
2771 if (perf_callchain_store(entry, regs->ip))
2774 if (perf_hw_regs(regs))
2775 unwind_start(&state, current, regs, NULL);
2777 unwind_start(&state, current, NULL, (void *)regs->sp);
2779 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2780 addr = unwind_get_return_address(&state);
2781 if (!addr || perf_callchain_store(entry, addr))
2787 valid_user_frame(const void __user *fp, unsigned long size)
2789 return __access_ok(fp, size);
2792 static unsigned long get_segment_base(unsigned int segment)
2794 struct desc_struct *desc;
2795 unsigned int idx = segment >> 3;
2797 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2798 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2799 struct ldt_struct *ldt;
2801 /* IRQs are off, so this synchronizes with smp_store_release */
2802 ldt = READ_ONCE(current->active_mm->context.ldt);
2803 if (!ldt || idx >= ldt->nr_entries)
2806 desc = &ldt->entries[idx];
2811 if (idx >= GDT_ENTRIES)
2814 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2817 return get_desc_base(desc);
2820 #ifdef CONFIG_IA32_EMULATION
2822 #include <linux/compat.h>
2825 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2827 /* 32-bit process in 64-bit kernel. */
2828 unsigned long ss_base, cs_base;
2829 struct stack_frame_ia32 frame;
2830 const struct stack_frame_ia32 __user *fp;
2832 if (user_64bit_mode(regs))
2835 cs_base = get_segment_base(regs->cs);
2836 ss_base = get_segment_base(regs->ss);
2838 fp = compat_ptr(ss_base + regs->bp);
2839 pagefault_disable();
2840 while (entry->nr < entry->max_stack) {
2841 if (!valid_user_frame(fp, sizeof(frame)))
2844 if (__get_user(frame.next_frame, &fp->next_frame))
2846 if (__get_user(frame.return_address, &fp->return_address))
2849 perf_callchain_store(entry, cs_base + frame.return_address);
2850 fp = compat_ptr(ss_base + frame.next_frame);
2857 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2864 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2866 struct stack_frame frame;
2867 const struct stack_frame __user *fp;
2869 if (perf_guest_state()) {
2870 /* TODO: We don't support guest os callchain now */
2875 * We don't know what to do with VM86 stacks.. ignore them for now.
2877 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2880 fp = (void __user *)regs->bp;
2882 perf_callchain_store(entry, regs->ip);
2884 if (!nmi_uaccess_okay())
2887 if (perf_callchain_user32(regs, entry))
2890 pagefault_disable();
2891 while (entry->nr < entry->max_stack) {
2892 if (!valid_user_frame(fp, sizeof(frame)))
2895 if (__get_user(frame.next_frame, &fp->next_frame))
2897 if (__get_user(frame.return_address, &fp->return_address))
2900 perf_callchain_store(entry, frame.return_address);
2901 fp = (void __user *)frame.next_frame;
2907 * Deal with code segment offsets for the various execution modes:
2909 * VM86 - the good olde 16 bit days, where the linear address is
2910 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2912 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2913 * to figure out what the 32bit base address is.
2915 * X32 - has TIF_X32 set, but is running in x86_64
2917 * X86_64 - CS,DS,SS,ES are all zero based.
2919 static unsigned long code_segment_base(struct pt_regs *regs)
2922 * For IA32 we look at the GDT/LDT segment base to convert the
2923 * effective IP to a linear address.
2926 #ifdef CONFIG_X86_32
2928 * If we are in VM86 mode, add the segment offset to convert to a
2931 if (regs->flags & X86_VM_MASK)
2932 return 0x10 * regs->cs;
2934 if (user_mode(regs) && regs->cs != __USER_CS)
2935 return get_segment_base(regs->cs);
2937 if (user_mode(regs) && !user_64bit_mode(regs) &&
2938 regs->cs != __USER32_CS)
2939 return get_segment_base(regs->cs);
2944 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2946 if (perf_guest_state())
2947 return perf_guest_get_ip();
2949 return regs->ip + code_segment_base(regs);
2952 unsigned long perf_misc_flags(struct pt_regs *regs)
2954 unsigned int guest_state = perf_guest_state();
2958 if (guest_state & PERF_GUEST_USER)
2959 misc |= PERF_RECORD_MISC_GUEST_USER;
2961 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2963 if (user_mode(regs))
2964 misc |= PERF_RECORD_MISC_USER;
2966 misc |= PERF_RECORD_MISC_KERNEL;
2969 if (regs->flags & PERF_EFLAGS_EXACT)
2970 misc |= PERF_RECORD_MISC_EXACT_IP;
2975 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2977 /* This API doesn't currently support enumerating hybrid PMUs. */
2978 if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) ||
2979 !x86_pmu_initialized()) {
2980 memset(cap, 0, sizeof(*cap));
2985 * Note, hybrid CPU models get tracked as having hybrid PMUs even when
2986 * all E-cores are disabled via BIOS. When E-cores are disabled, the
2987 * base PMU holds the correct number of counters for P-cores.
2989 cap->version = x86_pmu.version;
2990 cap->num_counters_gp = x86_pmu.num_counters;
2991 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2992 cap->bit_width_gp = x86_pmu.cntval_bits;
2993 cap->bit_width_fixed = x86_pmu.cntval_bits;
2994 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2995 cap->events_mask_len = x86_pmu.events_mask_len;
2996 cap->pebs_ept = x86_pmu.pebs_ept;
2998 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
3000 u64 perf_get_hw_event_config(int hw_event)
3002 int max = x86_pmu.max_events;
3005 return x86_pmu.event_map(array_index_nospec(hw_event, max));
3009 EXPORT_SYMBOL_GPL(perf_get_hw_event_config);