1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/arch/x86/entry_64.rst
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - idtentry: Define exception entry points.
21 #include <linux/linkage.h>
22 #include <asm/segment.h>
23 #include <asm/cache.h>
24 #include <asm/errno.h>
25 #include <asm/asm-offsets.h>
27 #include <asm/unistd.h>
28 #include <asm/thread_info.h>
29 #include <asm/hw_irq.h>
30 #include <asm/page_types.h>
31 #include <asm/irqflags.h>
32 #include <asm/paravirt.h>
33 #include <asm/percpu.h>
36 #include <asm/pgtable_types.h>
37 #include <asm/export.h>
38 #include <asm/frame.h>
39 #include <asm/trapnr.h>
40 #include <asm/nospec-branch.h>
41 #include <asm/fsgsbase.h>
42 #include <linux/err.h>
47 .section .entry.text, "ax"
50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
52 * This is the only entry point used for 64-bit system calls. The
53 * hardware interface is reasonably well designed and the register to
54 * argument mapping Linux uses fits well with the registers that are
55 * available when SYSCALL is used.
57 * SYSCALL instructions can be found inlined in libc implementations as
58 * well as some other programs and libraries. There are also a handful
59 * of SYSCALL instructions in the vDSO used, for example, as a
60 * clock_gettimeofday fallback.
62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
63 * then loads new ss, cs, and rip from previously programmed MSRs.
64 * rflags gets masked by a value from another MSR (so CLD and CLAC
65 * are not needed). SYSCALL does not save anything on the stack
66 * and does not change rsp.
69 * rax system call number
71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
75 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
80 * Only called from user space.
82 * When user can change pt_regs->foo always force IRET. That is because
83 * it deals with uncanonical addresses better. SYSRET has trouble
84 * with them due to bugs in both AMD and Intel CPUs.
87 SYM_CODE_START(entry_SYSCALL_64)
92 /* tss.sp2 is scratch space. */
93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
97 SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
100 /* Construct struct pt_regs on stack */
101 pushq $__USER_DS /* pt_regs->ss */
102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
103 pushq %r11 /* pt_regs->flags */
104 pushq $__USER_CS /* pt_regs->cs */
105 pushq %rcx /* pt_regs->ip */
106 SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
107 pushq %rax /* pt_regs->orig_ax */
109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
113 /* Sign extend the lower 32bit as syscall numbers are treated as int */
116 /* clobbers %rax, make sure it is after saving the syscall nr */
120 call do_syscall_64 /* returns with IRQs disabled */
123 * Try to use SYSRET instead of IRET if we're returning to
124 * a completely clean 64-bit userspace context. If we're not,
125 * go to the slow exit path.
126 * In the Xen PV case we must use iret anyway.
129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \
135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
136 jne swapgs_restore_regs_and_return_to_usermode
139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
140 * in kernel space. This essentially lets the user take over
141 * the kernel, since userspace controls RSP.
143 * If width of "canonical tail" ever becomes variable, this will need
144 * to be updated to remain correct on both old and new CPUs.
146 * Change top bits to match most significant bit (47th or 56th bit
147 * depending on paging mode) in the address.
149 #ifdef CONFIG_X86_5LEVEL
150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
157 /* If this changed %rcx, it was not canonical */
159 jne swapgs_restore_regs_and_return_to_usermode
161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
162 jne swapgs_restore_regs_and_return_to_usermode
165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
166 jne swapgs_restore_regs_and_return_to_usermode
169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
170 * restore RF properly. If the slowpath sets it for whatever reason, we
171 * need to restore it correctly.
173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
174 * trap from userspace immediately after SYSRET. This would cause an
175 * infinite loop whenever #DB happens with register state that satisfies
176 * the opportunistic SYSRET conditions. For example, single-stepping
179 * movq $stuck_here, %rcx
184 * would never get past 'stuck_here'.
186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
187 jnz swapgs_restore_regs_and_return_to_usermode
189 /* nothing to check for RSP */
191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
192 jne swapgs_restore_regs_and_return_to_usermode
195 * We win! This label is here just for ease of understanding
196 * perf profiles. Nothing jumps here.
198 syscall_return_via_sysret:
203 * Now all regs are restored except RSP and RDI.
204 * Save old stack pointer and switch to trampoline stack.
207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
208 UNWIND_HINT_END_OF_STACK
210 pushq RSP-RDI(%rdi) /* RSP */
211 pushq (%rdi) /* RDI */
214 * We are on the trampoline stack. All regs except RDI are live.
215 * We can do future final exit work right here.
217 STACKLEAK_ERASE_NOCLOBBER
219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
223 SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL)
227 SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL)
230 SYM_CODE_END(entry_SYSCALL_64)
236 .pushsection .text, "ax"
237 SYM_FUNC_START(__switch_to_asm)
239 * Save callee-saved registers
240 * This must match the order in inactive_task_frame
250 movq %rsp, TASK_threadsp(%rdi)
251 movq TASK_threadsp(%rsi), %rsp
253 #ifdef CONFIG_STACKPROTECTOR
254 movq TASK_stack_canary(%rsi), %rbx
255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + FIXED_stack_canary
259 * When switching from a shallower to a deeper call stack
260 * the RSB may either underflow or use entries populated
261 * with userspace addresses. On CPUs where those concerns
262 * exist, overwrite the RSB with entries which capture
263 * speculative execution to prevent attack.
265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
267 /* restore callee-saved registers */
276 SYM_FUNC_END(__switch_to_asm)
280 * A newly forked process directly context switches into this address.
282 * rax: prev task we switched from
283 * rbx: kernel thread func (NULL for user thread)
284 * r12: kernel thread arg
286 .pushsection .text, "ax"
287 SYM_CODE_START(ret_from_fork_asm)
289 ANNOTATE_NOENDBR // copy_thread
292 movq %rax, %rdi /* prev */
293 movq %rsp, %rsi /* regs */
294 movq %rbx, %rdx /* fn */
295 movq %r12, %rcx /* fn_arg */
298 jmp swapgs_restore_regs_and_return_to_usermode
299 SYM_CODE_END(ret_from_fork_asm)
302 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
303 #ifdef CONFIG_DEBUG_ENTRY
306 testl $X86_EFLAGS_IF, %eax
314 SYM_CODE_START(xen_error_entry)
317 PUSH_AND_CLEAR_REGS save_ret=1
318 ENCODE_FRAME_POINTER 8
319 UNTRAIN_RET_FROM_CALL
321 SYM_CODE_END(xen_error_entry)
324 * idtentry_body - Macro to emit code calling the C function
325 * @cfunc: C function to be called
326 * @has_error_code: Hardware pushed error code on stack
328 .macro idtentry_body cfunc has_error_code:req
331 * Call error_entry() and switch to the task stack if from userspace.
333 * When in XENPV, it is already in the task stack, and it can't fault
334 * for native_iret() nor native_load_gs_index() since XENPV uses its
335 * own pvops for IRET and load_gs_index(). And it doesn't need to
336 * switch the CR3. So it can skip invoking error_entry().
338 ALTERNATIVE "call error_entry; movq %rax, %rsp", \
339 "call xen_error_entry", X86_FEATURE_XENPV
344 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/
346 .if \has_error_code == 1
347 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
348 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
353 /* For some configurations \cfunc ends up being a noreturn. */
360 * idtentry - Macro to generate entry stubs for simple IDT entries
361 * @vector: Vector number
362 * @asmsym: ASM symbol for the entry point
363 * @cfunc: C function to be called
364 * @has_error_code: Hardware pushed error code on stack
366 * The macro emits code to set up the kernel context for straight forward
367 * and simple IDT entries. No IST stack, no paranoid entry checks.
369 .macro idtentry vector asmsym cfunc has_error_code:req
370 SYM_CODE_START(\asmsym)
372 .if \vector == X86_TRAP_BP
373 /* #BP advances %rip to the next instruction */
374 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8 signal=0
376 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8
383 .if \has_error_code == 0
384 pushq $-1 /* ORIG_RAX: no syscall to restart */
387 .if \vector == X86_TRAP_BP
389 * If coming from kernel space, create a 6-word gap to allow the
390 * int3 handler to emulate a call instruction.
392 testb $3, CS-ORIG_RAX(%rsp)
393 jnz .Lfrom_usermode_no_gap_\@
397 UNWIND_HINT_IRET_REGS offset=8
398 .Lfrom_usermode_no_gap_\@:
401 idtentry_body \cfunc \has_error_code
403 _ASM_NOKPROBE(\asmsym)
404 SYM_CODE_END(\asmsym)
408 * Interrupt entry/exit.
410 + The interrupt stubs push (vector) onto the stack, which is the error_code
411 * position of idtentry exceptions, and jump to one of the two idtentry points
414 * common_interrupt is a hotpath, align it to a cache line
416 .macro idtentry_irq vector cfunc
417 .p2align CONFIG_X86_L1_CACHE_SHIFT
418 idtentry \vector asm_\cfunc \cfunc has_error_code=1
422 * System vectors which invoke their handlers directly and are not
423 * going through the regular common device interrupt handling code.
425 .macro idtentry_sysvec vector cfunc
426 idtentry \vector asm_\cfunc \cfunc has_error_code=0
430 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
431 * @vector: Vector number
432 * @asmsym: ASM symbol for the entry point
433 * @cfunc: C function to be called
435 * The macro emits code to set up the kernel context for #MC and #DB
437 * If the entry comes from user space it uses the normal entry path
438 * including the return to user space work and preemption checks on
441 * If hits in kernel mode then it needs to go through the paranoid
442 * entry as the exception can hit any random state. No preemption
443 * check on exit to keep the paranoid path simple.
445 .macro idtentry_mce_db vector asmsym cfunc
446 SYM_CODE_START(\asmsym)
447 UNWIND_HINT_IRET_ENTRY
452 pushq $-1 /* ORIG_RAX: no syscall to restart */
455 * If the entry is from userspace, switch stacks and treat it as
458 testb $3, CS-ORIG_RAX(%rsp)
459 jnz .Lfrom_usermode_switch_stack_\@
461 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
466 movq %rsp, %rdi /* pt_regs pointer */
472 /* Switch to the regular task stack and use the noist entry point */
473 .Lfrom_usermode_switch_stack_\@:
474 idtentry_body noist_\cfunc, has_error_code=0
476 _ASM_NOKPROBE(\asmsym)
477 SYM_CODE_END(\asmsym)
480 #ifdef CONFIG_AMD_MEM_ENCRYPT
482 * idtentry_vc - Macro to generate entry stub for #VC
483 * @vector: Vector number
484 * @asmsym: ASM symbol for the entry point
485 * @cfunc: C function to be called
487 * The macro emits code to set up the kernel context for #VC. The #VC handler
488 * runs on an IST stack and needs to be able to cause nested #VC exceptions.
490 * To make this work the #VC entry code tries its best to pretend it doesn't use
491 * an IST stack by switching to the task stack if coming from user-space (which
492 * includes early SYSCALL entry path) or back to the stack in the IRET frame if
493 * entered from kernel-mode.
495 * If entered from kernel-mode the return stack is validated first, and if it is
496 * not safe to use (e.g. because it points to the entry stack) the #VC handler
497 * will switch to a fall-back stack (VC2) and call a special handler function.
499 * The macro is only used for one vector, but it is planned to be extended in
500 * the future for the #HV exception.
502 .macro idtentry_vc vector asmsym cfunc
503 SYM_CODE_START(\asmsym)
504 UNWIND_HINT_IRET_ENTRY
510 * If the entry is from userspace, switch stacks and treat it as
513 testb $3, CS-ORIG_RAX(%rsp)
514 jnz .Lfrom_usermode_switch_stack_\@
517 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX.
518 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS
525 * Switch off the IST stack to make it free for nested exceptions. The
526 * vc_switch_off_ist() function will switch back to the interrupted
527 * stack if it is safe to do so. If not it switches to the VC fall-back
530 movq %rsp, %rdi /* pt_regs pointer */
531 call vc_switch_off_ist
532 movq %rax, %rsp /* Switch to new stack */
538 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
539 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
541 movq %rsp, %rdi /* pt_regs pointer */
546 * No need to switch back to the IST stack. The current stack is either
547 * identical to the stack in the IRET frame or the VC fall-back stack,
548 * so it is definitely mapped even with PTI enabled.
552 /* Switch to the regular task stack */
553 .Lfrom_usermode_switch_stack_\@:
554 idtentry_body user_\cfunc, has_error_code=1
556 _ASM_NOKPROBE(\asmsym)
557 SYM_CODE_END(\asmsym)
562 * Double fault entry. Straight paranoid. No checks from which context
563 * this comes because for the espfix induced #DF this would do the wrong
566 .macro idtentry_df vector asmsym cfunc
567 SYM_CODE_START(\asmsym)
568 UNWIND_HINT_IRET_ENTRY offset=8
573 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
577 movq %rsp, %rdi /* pt_regs pointer into first argument */
578 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
579 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
582 /* For some configurations \cfunc ends up being a noreturn. */
587 _ASM_NOKPROBE(\asmsym)
588 SYM_CODE_END(\asmsym)
592 * Include the defines which emit the idt entries which are shared
593 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
594 * so the stacktrace boundary checks work.
597 .globl __irqentry_text_start
598 __irqentry_text_start:
600 #include <asm/idtentry.h>
603 .globl __irqentry_text_end
607 SYM_CODE_START_LOCAL(common_interrupt_return)
608 SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
610 #ifdef CONFIG_DEBUG_ENTRY
611 /* Assert that pt_regs indicates user mode. */
618 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV
624 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
625 * Save old stack pointer and switch to trampoline stack.
628 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
629 UNWIND_HINT_END_OF_STACK
631 /* Copy the IRET frame to the trampoline stack. */
632 pushq 6*8(%rdi) /* SS */
633 pushq 5*8(%rdi) /* RSP */
634 pushq 4*8(%rdi) /* EFLAGS */
635 pushq 3*8(%rdi) /* CS */
636 pushq 2*8(%rdi) /* RIP */
638 /* Push user RDI on the trampoline stack. */
642 * We are on the trampoline stack. All regs except RDI are live.
643 * We can do future final exit work right here.
645 STACKLEAK_ERASE_NOCLOBBER
647 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
655 SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
656 #ifdef CONFIG_DEBUG_ENTRY
657 /* Assert that pt_regs indicates kernel mode. */
664 addq $8, %rsp /* skip regs->orig_ax */
666 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
667 * when returning from IPI handler.
670 SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL)
673 .long .Lnative_iret - (. + 4)
677 UNWIND_HINT_IRET_REGS
679 * Are we returning to a stack segment from the LDT? Note: in
680 * 64-bit mode SS:RSP on the exception stack is always valid.
682 #ifdef CONFIG_X86_ESPFIX64
683 testb $4, (SS-RIP)(%rsp)
684 jnz native_irq_return_ldt
687 SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
688 ANNOTATE_NOENDBR // exc_double_fault
690 * This may fault. Non-paranoid faults on return to userspace are
691 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
692 * Double-faults due to espfix64 are handled in exc_double_fault.
693 * Other faults here are fatal.
697 #ifdef CONFIG_X86_ESPFIX64
698 native_irq_return_ldt:
700 * We are running with user GSBASE. All GPRs contain their user
701 * values. We have a percpu ESPFIX stack that is eight slots
702 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
703 * of the ESPFIX stack.
705 * We clobber RAX and RDI in this code. We stash RDI on the
706 * normal stack and RAX on the ESPFIX stack.
708 * The ESPFIX stack layout we set up looks like this:
710 * --- top of ESPFIX stack ---
715 * RIP <-- RSP points here when we're done
716 * RAX <-- espfix_waddr points here
717 * --- bottom of ESPFIX stack ---
720 pushq %rdi /* Stash user RDI */
721 swapgs /* to kernel GS */
722 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
724 movq PER_CPU_VAR(espfix_waddr), %rdi
725 movq %rax, (0*8)(%rdi) /* user RAX */
726 movq (1*8)(%rsp), %rax /* user RIP */
727 movq %rax, (1*8)(%rdi)
728 movq (2*8)(%rsp), %rax /* user CS */
729 movq %rax, (2*8)(%rdi)
730 movq (3*8)(%rsp), %rax /* user RFLAGS */
731 movq %rax, (3*8)(%rdi)
732 movq (5*8)(%rsp), %rax /* user SS */
733 movq %rax, (5*8)(%rdi)
734 movq (4*8)(%rsp), %rax /* user RSP */
735 movq %rax, (4*8)(%rdi)
736 /* Now RAX == RSP. */
738 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
741 * espfix_stack[31:16] == 0. The page tables are set up such that
742 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
743 * espfix_waddr for any X. That is, there are 65536 RO aliases of
744 * the same page. Set up RSP so that RSP[31:16] contains the
745 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
746 * still points to an RO alias of the ESPFIX stack.
748 orq PER_CPU_VAR(espfix_stack), %rax
750 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
751 swapgs /* to user GS */
752 popq %rdi /* Restore user RDI */
755 UNWIND_HINT_IRET_REGS offset=8
758 * At this point, we cannot write to the stack any more, but we can
761 popq %rax /* Restore user RAX */
764 * RSP now points to an ordinary IRET frame, except that the page
765 * is read-only and RSP[31:16] are preloaded with the userspace
766 * values. We can now IRET back to userspace.
768 jmp native_irq_return_iret
770 SYM_CODE_END(common_interrupt_return)
771 _ASM_NOKPROBE(common_interrupt_return)
774 * Reload gs selector with exception handling
777 * Is in entry.text as it shouldn't be instrumented.
779 SYM_FUNC_START(asm_load_gs_index)
783 ANNOTATE_NOENDBR // error_entry
785 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
790 /* running with kernelgs */
792 swapgs /* switch back to user gs */
794 /* This can't be a string because the preprocessor needs to see it. */
795 movl $__USER_DS, %eax
798 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
803 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
805 SYM_FUNC_END(asm_load_gs_index)
806 EXPORT_SYMBOL(asm_load_gs_index)
810 * A note on the "critical region" in our callback handler.
811 * We want to avoid stacking callback handlers due to events occurring
812 * during handling of the last event. To do this, we keep events disabled
813 * until we've done all processing. HOWEVER, we must enable events before
814 * popping the stack frame (can't be done atomically) and so it would still
815 * be possible to get enough handler activations to overflow the stack.
816 * Although unlikely, bugs of that kind are hard to track down, so we'd
817 * like to avoid the possibility.
818 * So, on entry to the handler we detect whether we interrupted an
819 * existing activation in its critical region -- if so, we pop the current
820 * activation and restart the handler using the previous one.
822 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs)
825 SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback)
828 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
829 * see the correct pointer to the pt_regs
832 movq %rdi, %rsp /* we don't return, adjust the stack frame */
835 call xen_pv_evtchn_do_upcall
838 SYM_CODE_END(exc_xen_hypervisor_callback)
841 * Hypervisor uses this for application faults while it executes.
842 * We get here for two reasons:
843 * 1. Fault while reloading DS, ES, FS or GS
844 * 2. Fault while executing IRET
845 * Category 1 we do not need to fix up as Xen has already reloaded all segment
846 * registers that could be reloaded and zeroed the others.
847 * Category 2 we fix up by killing the current process. We cannot use the
848 * normal Linux return path in this case because if we use the IRET hypercall
849 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
850 * We distinguish between categories by comparing each saved segment register
851 * with its current contents: any discrepancy means we in category 1.
854 SYM_CODE_START_NOALIGN(xen_failsafe_callback)
855 UNWIND_HINT_UNDEFINED
869 /* All segments match their saved values => Category 2 (Bad IRET). */
874 UNWIND_HINT_IRET_REGS offset=8
875 jmp asm_exc_general_protection
876 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
880 UNWIND_HINT_IRET_REGS
881 pushq $-1 /* orig_ax = -1 => not a system call */
885 SYM_CODE_END(xen_failsafe_callback)
886 #endif /* CONFIG_XEN_PV */
889 * Save all registers in pt_regs. Return GSBASE related information
890 * in EBX depending on the availability of the FSGSBASE instructions:
893 * N 0 -> SWAPGS on exit
894 * 1 -> no SWAPGS on exit
896 * Y GSBASE value at entry, must be restored in paranoid_exit
899 * R15 - old SPEC_CTRL
901 SYM_CODE_START(paranoid_entry)
904 PUSH_AND_CLEAR_REGS save_ret=1
905 ENCODE_FRAME_POINTER 8
908 * Always stash CR3 in %r14. This value will be restored,
909 * verbatim, at exit. Needed if paranoid_entry interrupted
910 * another entry that already switched to the user CR3 value
911 * but has not yet returned to userspace.
913 * This is also why CS (stashed in the "iret frame" by the
914 * hardware at entry) can not be used: this may be a return
915 * to kernel code, but with a user CR3 value.
917 * Switching CR3 does not depend on kernel GSBASE so it can
918 * be done before switching to the kernel GSBASE. This is
919 * required for FSGSBASE because the kernel GSBASE has to
920 * be retrieved from a kernel internal table.
922 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
925 * Handling GSBASE depends on the availability of FSGSBASE.
927 * Without FSGSBASE the kernel enforces that negative GSBASE
928 * values indicate kernel GSBASE. With FSGSBASE no assumptions
929 * can be made about the GSBASE value when entering from user
932 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
935 * Read the current GSBASE and store it in %rbx unconditionally,
936 * retrieve and set the current CPUs kernel GSBASE. The stored value
937 * has to be restored in paranoid_exit unconditionally.
939 * The unconditional write to GS base below ensures that no subsequent
940 * loads based on a mispredicted GS base can happen, therefore no LFENCE
943 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
944 jmp .Lparanoid_gsbase_done
946 .Lparanoid_entry_checkgs:
947 /* EBX = 1 -> kernel GSBASE active, no restore required */
951 * The kernel-enforced convention is a negative GSBASE indicates
952 * a kernel value. No SWAPGS needed on entry and exit.
954 movl $MSR_GS_BASE, %ecx
957 js .Lparanoid_kernel_gsbase
959 /* EBX = 0 -> SWAPGS required on exit */
962 .Lparanoid_kernel_gsbase:
963 FENCE_SWAPGS_KERNEL_ENTRY
964 .Lparanoid_gsbase_done:
967 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
968 * CR3 above, keep the old value in a callee saved register.
970 IBRS_ENTER save_reg=%r15
971 UNTRAIN_RET_FROM_CALL
974 SYM_CODE_END(paranoid_entry)
977 * "Paranoid" exit path from exception stack. This is invoked
978 * only on return from non-NMI IST interrupts that came
981 * We may be returning to very strange contexts (e.g. very early
982 * in syscall entry), so checking for preemption here would
983 * be complicated. Fortunately, there's no good reason to try
984 * to handle preemption here.
986 * R/EBX contains the GSBASE related information depending on the
987 * availability of the FSGSBASE instructions:
990 * N 0 -> SWAPGS on exit
991 * 1 -> no SWAPGS on exit
993 * Y User space GSBASE, must be restored unconditionally
996 * R15 - old SPEC_CTRL
998 SYM_CODE_START_LOCAL(paranoid_exit)
1002 * Must restore IBRS state before both CR3 and %GS since we need access
1003 * to the per-CPU x86_spec_ctrl_shadow variable.
1005 IBRS_EXIT save_reg=%r15
1008 * The order of operations is important. RESTORE_CR3 requires
1011 * NB to anyone to try to optimize this code: this code does
1012 * not execute at all for exceptions from user mode. Those
1013 * exceptions go through error_return instead.
1015 RESTORE_CR3 scratch_reg=%rax save_reg=%r14
1017 /* Handle the three GSBASE cases */
1018 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
1020 /* With FSGSBASE enabled, unconditionally restore GSBASE */
1022 jmp restore_regs_and_return_to_kernel
1024 .Lparanoid_exit_checkgs:
1025 /* On non-FSGSBASE systems, conditionally do SWAPGS */
1027 jnz restore_regs_and_return_to_kernel
1029 /* We are returning to a context with user GSBASE */
1031 jmp restore_regs_and_return_to_kernel
1032 SYM_CODE_END(paranoid_exit)
1035 * Switch GS and CR3 if needed.
1037 SYM_CODE_START(error_entry)
1041 PUSH_AND_CLEAR_REGS save_ret=1
1042 ENCODE_FRAME_POINTER 8
1044 testb $3, CS+8(%rsp)
1045 jz .Lerror_kernelspace
1048 * We entered from user mode or we're pretending to have entered
1049 * from user mode due to an IRET fault.
1052 FENCE_SWAPGS_USER_ENTRY
1053 /* We have user CR3. Change to kernel CR3. */
1054 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1056 UNTRAIN_RET_FROM_CALL
1058 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1059 /* Put us onto the real thread stack. */
1063 * There are two places in the kernel that can potentially fault with
1064 * usergs. Handle them here. B stepping K8s sometimes report a
1065 * truncated RIP for IRET exceptions returning to compat mode. Check
1066 * for these here too.
1068 .Lerror_kernelspace:
1069 leaq native_irq_return_iret(%rip), %rcx
1070 cmpq %rcx, RIP+8(%rsp)
1072 movl %ecx, %eax /* zero extend */
1073 cmpq %rax, RIP+8(%rsp)
1075 cmpq $.Lgs_change, RIP+8(%rsp)
1076 jne .Lerror_entry_done_lfence
1079 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1080 * gsbase and proceed. We'll fix up the exception and land in
1081 * .Lgs_change's error handler with kernel gsbase.
1086 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a
1087 * kernel or user gsbase.
1089 .Lerror_entry_done_lfence:
1090 FENCE_SWAPGS_KERNEL_ENTRY
1092 leaq 8(%rsp), %rax /* return pt_regs pointer */
1097 /* Fix truncated RIP */
1098 movq %rcx, RIP+8(%rsp)
1103 * We came from an IRET to user mode, so we have user
1104 * gsbase and CR3. Switch to kernel gsbase and CR3:
1107 FENCE_SWAPGS_USER_ENTRY
1108 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1110 UNTRAIN_RET_FROM_CALL
1113 * Pretend that the exception came from user mode: set up pt_regs
1114 * as if we faulted immediately after IRET.
1116 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1120 SYM_CODE_END(error_entry)
1122 SYM_CODE_START_LOCAL(error_return)
1124 DEBUG_ENTRY_ASSERT_IRQS_OFF
1126 jz restore_regs_and_return_to_kernel
1127 jmp swapgs_restore_regs_and_return_to_usermode
1128 SYM_CODE_END(error_return)
1131 * Runs on exception stack. Xen PV does not go through this path at all,
1132 * so we can use real assembly here.
1135 * %r14: Used to save/restore the CR3 of the interrupted context
1136 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1138 SYM_CODE_START(asm_exc_nmi)
1139 UNWIND_HINT_IRET_ENTRY
1143 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1144 * the iretq it performs will take us out of NMI context.
1145 * This means that we can have nested NMIs where the next
1146 * NMI is using the top of the stack of the previous NMI. We
1147 * can't let it execute because the nested NMI will corrupt the
1148 * stack of the previous NMI. NMI handlers are not re-entrant
1151 * To handle this case we do the following:
1152 * Check the a special location on the stack that contains
1153 * a variable that is set when NMIs are executing.
1154 * The interrupted task's stack is also checked to see if it
1156 * If the variable is not set and the stack is not the NMI
1158 * o Set the special variable on the stack
1159 * o Copy the interrupt frame into an "outermost" location on the
1161 * o Copy the interrupt frame into an "iret" location on the stack
1162 * o Continue processing the NMI
1163 * If the variable is set or the previous stack is the NMI stack:
1164 * o Modify the "iret" location to jump to the repeat_nmi
1165 * o return back to the first NMI
1167 * Now on exit of the first NMI, we first clear the stack variable
1168 * The NMI stack will tell any nested NMIs at that point that it is
1169 * nested. Then we pop the stack normally with iret, and if there was
1170 * a nested NMI that updated the copy interrupt stack frame, a
1171 * jump will be made to the repeat_nmi code that will handle the second
1174 * However, espfix prevents us from directly returning to userspace
1175 * with a single IRET instruction. Similarly, IRET to user mode
1176 * can fault. We therefore handle NMIs from user space like
1177 * other IST entries.
1183 /* Use %rdx as our temp variable throughout */
1186 testb $3, CS-RIP+8(%rsp)
1187 jz .Lnmi_from_kernel
1190 * NMI from user mode. We need to run on the thread stack, but we
1191 * can't go through the normal entry paths: NMIs are masked, and
1192 * we don't want to enable interrupts, because then we'll end
1193 * up in an awkward situation in which IRQs are on but NMIs
1196 * We also must not push anything to the stack before switching
1197 * stacks lest we corrupt the "NMI executing" variable.
1201 FENCE_SWAPGS_USER_ENTRY
1202 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1204 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
1205 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1206 pushq 5*8(%rdx) /* pt_regs->ss */
1207 pushq 4*8(%rdx) /* pt_regs->rsp */
1208 pushq 3*8(%rdx) /* pt_regs->flags */
1209 pushq 2*8(%rdx) /* pt_regs->cs */
1210 pushq 1*8(%rdx) /* pt_regs->rip */
1211 UNWIND_HINT_IRET_REGS
1212 pushq $-1 /* pt_regs->orig_ax */
1213 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1214 ENCODE_FRAME_POINTER
1220 * At this point we no longer need to worry about stack damage
1221 * due to nesting -- we're on the normal thread stack and we're
1222 * done with the NMI stack.
1230 * Return back to user mode. We must *not* do the normal exit
1231 * work, because we don't want to enable interrupts.
1233 jmp swapgs_restore_regs_and_return_to_usermode
1237 * Here's what our stack frame will look like:
1238 * +---------------------------------------------------------+
1240 * | original Return RSP |
1241 * | original RFLAGS |
1244 * +---------------------------------------------------------+
1245 * | temp storage for rdx |
1246 * +---------------------------------------------------------+
1247 * | "NMI executing" variable |
1248 * +---------------------------------------------------------+
1249 * | iret SS } Copied from "outermost" frame |
1250 * | iret Return RSP } on each loop iteration; overwritten |
1251 * | iret RFLAGS } by a nested NMI to force another |
1252 * | iret CS } iteration if needed. |
1254 * +---------------------------------------------------------+
1255 * | outermost SS } initialized in first_nmi; |
1256 * | outermost Return RSP } will not be changed before |
1257 * | outermost RFLAGS } NMI processing is done. |
1258 * | outermost CS } Copied to "iret" frame on each |
1259 * | outermost RIP } iteration. |
1260 * +---------------------------------------------------------+
1262 * +---------------------------------------------------------+
1264 * The "original" frame is used by hardware. Before re-enabling
1265 * NMIs, we need to be done with it, and we need to leave enough
1266 * space for the asm code here.
1268 * We return by executing IRET while RSP points to the "iret" frame.
1269 * That will either return for real or it will loop back into NMI
1272 * The "outermost" frame is copied to the "iret" frame on each
1273 * iteration of the loop, so each iteration starts with the "iret"
1274 * frame pointing to the final return target.
1278 * Determine whether we're a nested NMI.
1280 * If we interrupted kernel code between repeat_nmi and
1281 * end_repeat_nmi, then we are a nested NMI. We must not
1282 * modify the "iret" frame because it's being written by
1283 * the outer NMI. That's okay; the outer NMI handler is
1284 * about to about to call exc_nmi() anyway, so we can just
1285 * resume the outer NMI.
1288 movq $repeat_nmi, %rdx
1291 movq $end_repeat_nmi, %rdx
1297 * Now check "NMI executing". If it's set, then we're nested.
1298 * This will not detect if we interrupted an outer NMI just
1305 * Now test if the previous stack was an NMI stack. This covers
1306 * the case where we interrupt an outer NMI after it clears
1307 * "NMI executing" but before IRET. We need to be careful, though:
1308 * there is one case in which RSP could point to the NMI stack
1309 * despite there being no NMI active: naughty userspace controls
1310 * RSP at the very beginning of the SYSCALL targets. We can
1311 * pull a fast one on naughty userspace, though: we program
1312 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1313 * if it controls the kernel's RSP. We set DF before we clear
1317 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1318 cmpq %rdx, 4*8(%rsp)
1319 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1322 subq $EXCEPTION_STKSZ, %rdx
1323 cmpq %rdx, 4*8(%rsp)
1324 /* If it is below the NMI stack, it is a normal NMI */
1327 /* Ah, it is within the NMI stack. */
1329 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1330 jz first_nmi /* RSP was user controlled. */
1332 /* This is a nested NMI. */
1336 * Modify the "iret" frame to point to repeat_nmi, forcing another
1337 * iteration of NMI handling.
1340 leaq -10*8(%rsp), %rdx
1347 /* Put stack back */
1353 /* We are returning to kernel mode, so this cannot result in a fault. */
1360 /* Make room for "NMI executing". */
1363 /* Leave room for the "iret" frame */
1366 /* Copy the "original" frame to the "outermost" frame */
1370 UNWIND_HINT_IRET_REGS
1372 /* Everything up to here is safe from nested NMIs */
1374 #ifdef CONFIG_DEBUG_ENTRY
1376 * For ease of testing, unmask NMIs right away. Disabled by
1377 * default because IRET is very expensive.
1380 pushq %rsp /* RSP (minus 8 because of the previous push) */
1381 addq $8, (%rsp) /* Fix up RSP */
1383 pushq $__KERNEL_CS /* CS */
1385 iretq /* continues at repeat_nmi below */
1386 UNWIND_HINT_IRET_REGS
1391 ANNOTATE_NOENDBR // this code
1393 * If there was a nested NMI, the first NMI's iret will return
1394 * here. But NMIs are still enabled and we can take another
1395 * nested NMI. The nested NMI checks the interrupted RIP to see
1396 * if it is between repeat_nmi and end_repeat_nmi, and if so
1397 * it will just return, as we are about to repeat an NMI anyway.
1398 * This makes it safe to copy to the stack frame that a nested
1401 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1402 * we're repeating an NMI, gsbase has the same value that it had on
1403 * the first iteration. paranoid_entry will load the kernel
1404 * gsbase if needed before we call exc_nmi(). "NMI executing"
1407 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1410 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1411 * here must not modify the "iret" frame while we're writing to
1412 * it or it will end up containing garbage.
1420 ANNOTATE_NOENDBR // this code
1423 * Everything below this point can be preempted by a nested NMI.
1424 * If this happens, then the inner NMI will change the "iret"
1425 * frame to point back to repeat_nmi.
1427 pushq $-1 /* ORIG_RAX: no syscall to restart */
1430 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1431 * as we should not be calling schedule in NMI context.
1432 * Even with normal interrupts enabled. An NMI should not be
1433 * setting NEED_RESCHED or anything that normal interrupts and
1434 * exceptions might do.
1443 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1444 IBRS_EXIT save_reg=%r15
1446 /* Always restore stashed CR3 value (see paranoid_entry) */
1447 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1450 * The above invocation of paranoid_entry stored the GSBASE
1451 * related information in R/EBX depending on the availability
1454 * If FSGSBASE is enabled, restore the saved GSBASE value
1455 * unconditionally, otherwise take the conditional SWAPGS path.
1457 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE
1463 /* EBX == 0 -> invoke SWAPGS */
1474 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1475 * at the "iret" frame.
1480 * Clear "NMI executing". Set DF first so that we can easily
1481 * distinguish the remaining code between here and IRET from
1482 * the SYSCALL entry and exit paths.
1484 * We arguably should just inspect RIP instead, but I (Andy) wrote
1485 * this code when I had the misapprehension that Xen PV supported
1486 * NMIs, and Xen PV would break that approach.
1489 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1492 * iretq reads the "iret" frame and exits the NMI stack in a
1493 * single instruction. We are returning to kernel mode, so this
1494 * cannot result in a fault. Similarly, we don't need to worry
1495 * about espfix64 on the way back to kernel mode.
1498 SYM_CODE_END(asm_exc_nmi)
1500 #ifndef CONFIG_IA32_EMULATION
1502 * This handles SYSCALL from 32-bit code. There is no way to program
1503 * MSRs to fully disable 32-bit SYSCALL.
1505 SYM_CODE_START(ignore_sysret)
1506 UNWIND_HINT_END_OF_STACK
1510 SYM_CODE_END(ignore_sysret)
1513 .pushsection .text, "ax"
1515 SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead)
1517 /* Prevent any naive code from trying to unwind to our caller. */
1520 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax
1521 leaq -PTREGS_SIZE(%rax), %rsp
1525 SYM_CODE_END(rewind_stack_and_make_dead)