1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
17 #ifdef CONFIG_ROM_SIZE
19 filename = "u-boot.rom";
23 size = <CONFIG_ROM_SIZE>;
24 #ifdef CONFIG_HAVE_INTEL_ME
26 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
29 filename = CONFIG_INTEL_ME_FILE;
33 #ifdef CONFIG_HAVE_MICROCODE
34 u-boot-tpl-with-ucode-ptr {
35 offset = <CONFIG_TPL_TEXT_BASE>;
42 offset = <CONFIG_X86_OFFSET_SPL>;
45 offset = <CONFIG_X86_OFFSET_U_BOOT>;
47 #elif defined(CONFIG_SPL)
48 u-boot-spl-with-ucode-ptr {
49 offset = <CONFIG_X86_OFFSET_SPL>;
51 u-boot-dtb-with-ucode2 {
52 type = "u-boot-dtb-with-ucode";
55 offset = <CONFIG_X86_OFFSET_U_BOOT>;
58 # ifdef CONFIG_HAVE_MICROCODE
59 /* If there is no SPL then we need to put microcode in U-Boot */
60 u-boot-with-ucode-ptr {
61 offset = <CONFIG_X86_OFFSET_U_BOOT>;
65 offset = <CONFIG_X86_OFFSET_U_BOOT>;
69 #ifdef CONFIG_HAVE_MICROCODE
70 u-boot-dtb-with-ucode {
81 #ifdef CONFIG_HAVE_X86_FIT
87 #ifdef CONFIG_HAVE_MRC
89 offset = <CFG_X86_MRC_ADDR>;
92 #ifdef CONFIG_FSP_VERSION1
94 filename = CONFIG_FSP_FILE;
95 offset = <CONFIG_FSP_ADDR>;
98 #ifdef CONFIG_FSP_VERSION2
100 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
103 filename = CONFIG_IFWI_INPUT_FILE;
109 ifwi-subpart = "IBBP";
122 filename = CONFIG_FSP_FILE_M;
125 filename = CONFIG_FSP_FILE_S;
128 private_files: private-files {
132 #ifdef CONFIG_HAVE_CMC
134 filename = CONFIG_CMC_FILE;
135 offset = <CONFIG_CMC_ADDR>;
138 #ifdef CONFIG_HAVE_VGA_BIOS
140 filename = CONFIG_VGA_BIOS_FILE;
141 offset = <CONFIG_VGA_BIOS_ADDR>;
144 #ifdef CONFIG_HAVE_VBT
146 filename = CONFIG_VBT_FILE;
147 offset = <CONFIG_VBT_ADDR>;
150 #ifdef CONFIG_HAVE_REFCODE
152 offset = <CFG_X86_REFCODE_ADDR>;
157 offset = <CONFIG_SYS_X86_START16>;
160 offset = <CONFIG_RESET_VEC_LOC>;
162 #elif defined(CONFIG_SPL)
164 offset = <CONFIG_SYS_X86_START16>;
167 offset = <CONFIG_RESET_VEC_LOC>;
171 offset = <CONFIG_SYS_X86_START16>;
174 offset = <CONFIG_RESET_VEC_LOC>;