arch/x86/dts/u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <config.h>
   8
   9 / {
  10         binman {
  11                 multiple-images;
  12                 rom: rom {
  13                 };
  14         };
  15 };
  16
  17 #ifdef CONFIG_ROM_SIZE
  18 &rom {
  19         filename = "u-boot.rom";
  20         end-at-4gb;
  21         sort-by-offset;
  22         pad-byte = <0xff>;
  23         size = <CONFIG_ROM_SIZE>;
  24 #ifdef CONFIG_HAVE_INTEL_ME
  25         intel-descriptor {
  26                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
  27         };
  28         intel-me {
  29                 filename = CONFIG_INTEL_ME_FILE;
  30         };
  31 #endif
  32 #ifdef CONFIG_TPL
  33 #ifdef CONFIG_HAVE_MICROCODE
  34         u-boot-tpl-with-ucode-ptr {
  35                 offset = <CONFIG_TPL_TEXT_BASE>;
  36         };
  37         u-boot-tpl-dtb {
  38         };
  39 #endif
  40         u-boot-spl {
  41                 type = "u-boot-spl";
  42                 offset = <CONFIG_X86_OFFSET_SPL>;
  43         };
  44         u-boot {
  45                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  46         };
  47 #elif defined(CONFIG_SPL)
  48         u-boot-spl-with-ucode-ptr {
  49                 offset = <CONFIG_X86_OFFSET_SPL>;
  50         };
  51         u-boot-dtb-with-ucode2 {
  52                 type = "u-boot-dtb-with-ucode";
  53         };
  54         u-boot {
  55                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  56         };
  57 #else
  58 # ifdef CONFIG_HAVE_MICROCODE
  59         /* If there is no SPL then we need to put microcode in U-Boot */
  60         u-boot-with-ucode-ptr {
  61                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  62         };
  63 # else
  64         u-boot-nodtb {
  65                 offset = <CONFIG_X86_OFFSET_U_BOOT>;
  66         };
  67 # endif
  68 #endif
  69 #ifdef CONFIG_HAVE_MICROCODE
  70         u-boot-dtb-with-ucode {
  71         };
  72         u-boot-ucode {
  73                 align = <16>;
  74         };
  75 #else
  76         u-boot-dtb {
  77         };
  78 #endif
  79         fdtmap {
  80         };
  81 #ifdef CONFIG_HAVE_X86_FIT
  82         intel-fit {
  83         };
  84         intel-fit-ptr {
  85         };
  86 #endif
  87 #ifdef CONFIG_HAVE_MRC
  88         intel-mrc {
  89                 offset = <CFG_X86_MRC_ADDR>;
  90         };
  91 #endif
  92 #ifdef CONFIG_FSP_VERSION1
  93         intel-fsp {
  94                 filename = CONFIG_FSP_FILE;
  95                 offset = <CONFIG_FSP_ADDR>;
  96         };
  97 #endif
  98 #ifdef CONFIG_FSP_VERSION2
  99         intel-descriptor {
 100                 filename = CONFIG_FLASH_DESCRIPTOR_FILE;
 101         };
 102         intel-ifwi {
 103                 filename = CONFIG_IFWI_INPUT_FILE;
 104                 convert-fit;
 105
 106                 section {
 107                         size = <0x8000>;
 108                         ifwi-replace;
 109                         ifwi-subpart = "IBBP";
 110                         ifwi-entry = "IBBL";
 111                         u-boot-tpl {
 112                         };
 113                         x86-start16-tpl {
 114                                 offset = <0x7800>;
 115                         };
 116                         x86-reset16-tpl {
 117                                 offset = <0x7ff0>;
 118                         };
 119                 };
 120         };
 121         intel-fsp-m {
 122                 filename = CONFIG_FSP_FILE_M;
 123         };
 124         intel-fsp-s {
 125                 filename = CONFIG_FSP_FILE_S;
 126         };
 127 #endif
 128         private_files: private-files {
 129                 type = "files";
 130                 pattern = "*.dat";
 131         };
 132 #ifdef CONFIG_HAVE_CMC
 133         intel-cmc {
 134                 filename = CONFIG_CMC_FILE;
 135                 offset = <CONFIG_CMC_ADDR>;
 136         };
 137 #endif
 138 #ifdef CONFIG_HAVE_VGA_BIOS
 139         intel-vga {
 140                 filename = CONFIG_VGA_BIOS_FILE;
 141                 offset = <CONFIG_VGA_BIOS_ADDR>;
 142         };
 143 #endif
 144 #ifdef CONFIG_HAVE_VBT
 145         intel-vbt {
 146                 filename = CONFIG_VBT_FILE;
 147                 offset = <CONFIG_VBT_ADDR>;
 148         };
 149 #endif
 150 #ifdef CONFIG_HAVE_REFCODE
 151         intel-refcode {
 152                 offset = <CFG_X86_REFCODE_ADDR>;
 153         };
 154 #endif
 155 #ifdef CONFIG_TPL
 156         x86-start16-tpl {
 157                 offset = <CONFIG_SYS_X86_START16>;
 158         };
 159         x86-reset16-tpl {
 160                 offset = <CONFIG_RESET_VEC_LOC>;
 161         };
 162 #elif defined(CONFIG_SPL)
 163         x86-start16-spl {
 164                 offset = <CONFIG_SYS_X86_START16>;
 165         };
 166         x86-reset16-spl {
 167                 offset = <CONFIG_RESET_VEC_LOC>;
 168         };
 169 #else
 170         x86-start16 {
 171                 offset = <CONFIG_SYS_X86_START16>;
 172         };
 173         x86-reset16 {
 174                 offset = <CONFIG_RESET_VEC_LOC>;
 175         };
 176 #endif
 177         image-header {
 178                 location = "end";
 179         };
 180 };
 181 #endif