arch/x86/dts/minnowmax.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "serial.dtsi"
  14 /include/ "rtc.dtsi"
  15
  16 / {
  17         model = "Intel Minnowboard Max";
  18         compatible = "intel,minnowmax", "intel,baytrail";
  19
  20         aliases {
  21                 serial0 = &serial;
  22                 spi0 = "/spi";
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         pch_pinctrl {
  30                 compatible = "intel,x86-pinctrl";
  31                 io-base = <0x4c>;
  32
  33                 pin_usb_host_en0@0 {
  34                         gpio-offset = <0x80 8>;
  35                         pad-offset = <0x260>;
  36                         mode-gpio;
  37                         output-value = <1>;
  38                         direction = <PIN_OUTPUT>;
  39                 };
  40
  41                 pin_usb_host_en1@0 {
  42                         gpio-offset = <0x80 9>;
  43                         pad-offset = <0x258>;
  44                         mode-gpio;
  45                         output-value = <1>;
  46                         direction = <PIN_OUTPUT>;
  47                 };
  48         };
  49
  50         gpioa {
  51                 compatible = "intel,ich6-gpio";
  52                 u-boot,dm-pre-reloc;
  53                 reg = <0 0x20>;
  54                 bank-name = "A";
  55         };
  56
  57         gpiob {
  58                 compatible = "intel,ich6-gpio";
  59                 u-boot,dm-pre-reloc;
  60                 reg = <0x20 0x20>;
  61                 bank-name = "B";
  62         };
  63
  64         gpioc {
  65                 compatible = "intel,ich6-gpio";
  66                 u-boot,dm-pre-reloc;
  67                 reg = <0x40 0x20>;
  68                 bank-name = "C";
  69         };
  70
  71         gpiod {
  72                 compatible = "intel,ich6-gpio";
  73                 u-boot,dm-pre-reloc;
  74                 reg = <0x60 0x20>;
  75                 bank-name = "D";
  76         };
  77
  78         gpioe {
  79                 compatible = "intel,ich6-gpio";
  80                 u-boot,dm-pre-reloc;
  81                 reg = <0x80 0x20>;
  82                 bank-name = "E";
  83         };
  84
  85         gpiof {
  86                 compatible = "intel,ich6-gpio";
  87                 u-boot,dm-pre-reloc;
  88                 reg = <0xA0 0x20>;
  89                 bank-name = "F";
  90         };
  91
  92         chosen {
  93                 stdout-path = "/serial";
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 cpu@0 {
 101                         device_type = "cpu";
 102                         compatible = "intel,baytrail-cpu";
 103                         reg = <0>;
 104                         intel,apic-id = <0>;
 105                 };
 106
 107                 cpu@1 {
 108                         device_type = "cpu";
 109                         compatible = "intel,baytrail-cpu";
 110                         reg = <1>;
 111                         intel,apic-id = <4>;
 112                 };
 113
 114         };
 115
 116         pci {
 117                 compatible = "intel,pci-baytrail", "pci-x86";
 118                 #address-cells = <3>;
 119                 #size-cells = <2>;
 120                 u-boot,dm-pre-reloc;
 121                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 122                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 123                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 124
 125                 irq-router@1f,0 {
 126                         reg = <0x0000f800 0 0 0 0>;
 127                         compatible = "intel,irq-router";
 128                         intel,pirq-config = "ibase";
 129                         intel,ibase-offset = <0x50>;
 130                         intel,pirq-link = <8 8>;
 131                         intel,pirq-mask = <0xdee0>;
 132                         intel,pirq-routing = <
 133                                 /* BayTrail PCI devices */
 134                                 PCI_BDF(0, 2, 0) INTA PIRQA
 135                                 PCI_BDF(0, 3, 0) INTA PIRQA
 136                                 PCI_BDF(0, 16, 0) INTA PIRQA
 137                                 PCI_BDF(0, 17, 0) INTA PIRQA
 138                                 PCI_BDF(0, 18, 0) INTA PIRQA
 139                                 PCI_BDF(0, 19, 0) INTA PIRQA
 140                                 PCI_BDF(0, 20, 0) INTA PIRQA
 141                                 PCI_BDF(0, 21, 0) INTA PIRQA
 142                                 PCI_BDF(0, 22, 0) INTA PIRQA
 143                                 PCI_BDF(0, 23, 0) INTA PIRQA
 144                                 PCI_BDF(0, 24, 0) INTA PIRQA
 145                                 PCI_BDF(0, 24, 1) INTC PIRQC
 146                                 PCI_BDF(0, 24, 2) INTD PIRQD
 147                                 PCI_BDF(0, 24, 3) INTB PIRQB
 148                                 PCI_BDF(0, 24, 4) INTA PIRQA
 149                                 PCI_BDF(0, 24, 5) INTC PIRQC
 150                                 PCI_BDF(0, 24, 6) INTD PIRQD
 151                                 PCI_BDF(0, 24, 7) INTB PIRQB
 152                                 PCI_BDF(0, 26, 0) INTA PIRQA
 153                                 PCI_BDF(0, 27, 0) INTA PIRQA
 154                                 PCI_BDF(0, 28, 0) INTA PIRQA
 155                                 PCI_BDF(0, 28, 1) INTB PIRQB
 156                                 PCI_BDF(0, 28, 2) INTC PIRQC
 157                                 PCI_BDF(0, 28, 3) INTD PIRQD
 158                                 PCI_BDF(0, 29, 0) INTA PIRQA
 159                                 PCI_BDF(0, 30, 0) INTA PIRQA
 160                                 PCI_BDF(0, 30, 1) INTD PIRQD
 161                                 PCI_BDF(0, 30, 2) INTB PIRQB
 162                                 PCI_BDF(0, 30, 3) INTC PIRQC
 163                                 PCI_BDF(0, 30, 4) INTD PIRQD
 164                                 PCI_BDF(0, 30, 5) INTB PIRQB
 165                                 PCI_BDF(0, 31, 3) INTB PIRQB
 166
 167                                 /* PCIe root ports downstream interrupts */
 168                                 PCI_BDF(1, 0, 0) INTA PIRQA
 169                                 PCI_BDF(1, 0, 0) INTB PIRQB
 170                                 PCI_BDF(1, 0, 0) INTC PIRQC
 171                                 PCI_BDF(1, 0, 0) INTD PIRQD
 172                                 PCI_BDF(2, 0, 0) INTA PIRQB
 173                                 PCI_BDF(2, 0, 0) INTB PIRQC
 174                                 PCI_BDF(2, 0, 0) INTC PIRQD
 175                                 PCI_BDF(2, 0, 0) INTD PIRQA
 176                                 PCI_BDF(3, 0, 0) INTA PIRQC
 177                                 PCI_BDF(3, 0, 0) INTB PIRQD
 178                                 PCI_BDF(3, 0, 0) INTC PIRQA
 179                                 PCI_BDF(3, 0, 0) INTD PIRQB
 180                                 PCI_BDF(4, 0, 0) INTA PIRQD
 181                                 PCI_BDF(4, 0, 0) INTB PIRQA
 182                                 PCI_BDF(4, 0, 0) INTC PIRQB
 183                                 PCI_BDF(4, 0, 0) INTD PIRQC
 184                         >;
 185                 };
 186         };
 187
 188         fsp {
 189                 compatible = "intel,baytrail-fsp";
 190                 fsp,mrc-init-tseg-size = <0>;
 191                 fsp,mrc-init-mmio-size = <0x800>;
 192                 fsp,mrc-init-spd-addr1 = <0xa0>;
 193                 fsp,mrc-init-spd-addr2 = <0xa2>;
 194                 fsp,emmc-boot-mode = <2>;
 195                 fsp,enable-sdio;
 196                 fsp,enable-sdcard;
 197                 fsp,enable-hsuart1;
 198                 fsp,enable-spi;
 199                 fsp,enable-sata;
 200                 fsp,sata-mode = <1>;
 201                 fsp,enable-lpe;
 202                 fsp,lpss-sio-enable-pci-mode;
 203                 fsp,enable-dma0;
 204                 fsp,enable-dma1;
 205                 fsp,enable-i2c0;
 206                 fsp,enable-i2c1;
 207                 fsp,enable-i2c2;
 208                 fsp,enable-i2c3;
 209                 fsp,enable-i2c4;
 210                 fsp,enable-i2c5;
 211                 fsp,enable-i2c6;
 212                 fsp,enable-pwm0;
 213                 fsp,enable-pwm1;
 214                 fsp,igd-dvmt50-pre-alloc = <2>;
 215                 fsp,aperture-size = <2>;
 216                 fsp,gtt-size = <2>;
 217                 fsp,serial-debug-port-address = <0x3f8>;
 218                 fsp,serial-debug-port-type = <1>;
 219                 fsp,scc-enable-pci-mode;
 220                 fsp,os-selection = <4>;
 221                 fsp,emmc45-ddr50-enabled;
 222                 fsp,emmc45-retune-timer-value = <8>;
 223                 fsp,enable-igd;
 224                 fsp,enable-memory-down;
 225                 fsp,memory-down-params {
 226                         compatible = "intel,baytrail-fsp-mdp";
 227                         fsp,dram-speed = <1>;
 228                         fsp,dram-type = <1>;
 229                         fsp,dimm-0-enable;
 230                         fsp,dimm-width = <1>;
 231                         fsp,dimm-density = <2>;
 232                         fsp,dimm-bus-width = <3>;
 233                         fsp,dimm-sides = <0>;
 234                         fsp,dimm-tcl = <0xb>;
 235                         fsp,dimm-trpt-rcd = <0xb>;
 236                         fsp,dimm-twr = <0xc>;
 237                         fsp,dimm-twtr = <6>;
 238                         fsp,dimm-trrd = <6>;
 239                         fsp,dimm-trtp = <6>;
 240                         fsp,dimm-tfaw = <0x14>;
 241                 };
 242         };
 243
 244         spi {
 245                 #address-cells = <1>;
 246                 #size-cells = <0>;
 247                 compatible = "intel,ich-spi";
 248                 spi-flash@0 {
 249                         reg = <0>;
 250                         compatible = "stmicro,n25q064a", "spi-flash";
 251                         memory-map = <0xff800000 0x00800000>;
 252                 };
 253         };
 254
 255         microcode {
 256                 update@0 {
 257 #include "microcode/m0130673322.dtsi"
 258                 };
 259         };
 260
 261 };