2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
15 /include/ "tsc_timer.dtsi"
18 model = "Intel Minnowboard Max";
19 compatible = "intel,minnowmax", "intel,baytrail";
31 compatible = "intel,x86-pinctrl";
36 gpio-offset = <0x80 0>;
40 direction = <PIN_OUTPUT>;
45 gpio-offset = <0x80 1>;
49 direction = <PIN_OUTPUT>;
54 gpio-offset = <0x80 2>;
58 direction = <PIN_OUTPUT>;
62 gpio-offset = <0x80 8>;
66 direction = <PIN_OUTPUT>;
70 gpio-offset = <0x80 9>;
74 direction = <PIN_OUTPUT>;
78 * As of today, the latest version FSP (gold4) for BayTrail
79 * misses the PAD configuration of the SD controller's Card
80 * Detect signal. The default PAD value for the CD pin sets
81 * the pin to work in GPIO mode, which causes card detect
82 * status cannot be reflected by the Present State register
83 * in the SD controller (bit 16 & bit 18 are always zero).
85 * Configure this pin to function 1 (SD controller).
94 stdout-path = "/serial";
103 compatible = "intel,baytrail-cpu";
110 compatible = "intel,baytrail-cpu";
118 compatible = "intel,pci-baytrail", "pci-x86";
119 #address-cells = <3>;
122 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
123 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
124 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
127 reg = <0x0000f800 0 0 0 0>;
128 compatible = "pci8086,0f1c", "intel,pch9";
129 #address-cells = <1>;
133 compatible = "intel,irq-router";
134 intel,pirq-config = "ibase";
135 intel,ibase-offset = <0x50>;
136 intel,actl-addr = <0>;
137 intel,pirq-link = <8 8>;
138 intel,pirq-mask = <0xdee0>;
139 intel,pirq-routing = <
140 /* BayTrail PCI devices */
141 PCI_BDF(0, 2, 0) INTA PIRQA
142 PCI_BDF(0, 3, 0) INTA PIRQA
143 PCI_BDF(0, 16, 0) INTA PIRQA
144 PCI_BDF(0, 17, 0) INTA PIRQA
145 PCI_BDF(0, 18, 0) INTA PIRQA
146 PCI_BDF(0, 19, 0) INTA PIRQA
147 PCI_BDF(0, 20, 0) INTA PIRQA
148 PCI_BDF(0, 21, 0) INTA PIRQA
149 PCI_BDF(0, 22, 0) INTA PIRQA
150 PCI_BDF(0, 23, 0) INTA PIRQA
151 PCI_BDF(0, 24, 0) INTA PIRQA
152 PCI_BDF(0, 24, 1) INTC PIRQC
153 PCI_BDF(0, 24, 2) INTD PIRQD
154 PCI_BDF(0, 24, 3) INTB PIRQB
155 PCI_BDF(0, 24, 4) INTA PIRQA
156 PCI_BDF(0, 24, 5) INTC PIRQC
157 PCI_BDF(0, 24, 6) INTD PIRQD
158 PCI_BDF(0, 24, 7) INTB PIRQB
159 PCI_BDF(0, 26, 0) INTA PIRQA
160 PCI_BDF(0, 27, 0) INTA PIRQA
161 PCI_BDF(0, 28, 0) INTA PIRQA
162 PCI_BDF(0, 28, 1) INTB PIRQB
163 PCI_BDF(0, 28, 2) INTC PIRQC
164 PCI_BDF(0, 28, 3) INTD PIRQD
165 PCI_BDF(0, 29, 0) INTA PIRQA
166 PCI_BDF(0, 30, 0) INTA PIRQA
167 PCI_BDF(0, 30, 1) INTD PIRQD
168 PCI_BDF(0, 30, 2) INTB PIRQB
169 PCI_BDF(0, 30, 3) INTC PIRQC
170 PCI_BDF(0, 30, 4) INTD PIRQD
171 PCI_BDF(0, 30, 5) INTB PIRQB
172 PCI_BDF(0, 31, 3) INTB PIRQB
175 * PCIe root ports downstream
178 PCI_BDF(1, 0, 0) INTA PIRQA
179 PCI_BDF(1, 0, 0) INTB PIRQB
180 PCI_BDF(1, 0, 0) INTC PIRQC
181 PCI_BDF(1, 0, 0) INTD PIRQD
182 PCI_BDF(2, 0, 0) INTA PIRQB
183 PCI_BDF(2, 0, 0) INTB PIRQC
184 PCI_BDF(2, 0, 0) INTC PIRQD
185 PCI_BDF(2, 0, 0) INTD PIRQA
186 PCI_BDF(3, 0, 0) INTA PIRQC
187 PCI_BDF(3, 0, 0) INTB PIRQD
188 PCI_BDF(3, 0, 0) INTC PIRQA
189 PCI_BDF(3, 0, 0) INTD PIRQB
190 PCI_BDF(4, 0, 0) INTA PIRQD
191 PCI_BDF(4, 0, 0) INTB PIRQA
192 PCI_BDF(4, 0, 0) INTC PIRQB
193 PCI_BDF(4, 0, 0) INTD PIRQC
198 #address-cells = <1>;
200 compatible = "intel,ich9-spi";
202 #address-cells = <1>;
205 compatible = "stmicro,n25q064a",
207 memory-map = <0xff800000 0x00800000>;
209 label = "rw-mrc-cache";
210 reg = <0x006f0000 0x00010000>;
216 compatible = "intel,ich6-gpio";
223 compatible = "intel,ich6-gpio";
230 compatible = "intel,ich6-gpio";
237 compatible = "intel,ich6-gpio";
244 compatible = "intel,ich6-gpio";
251 compatible = "intel,ich6-gpio";
260 compatible = "intel,baytrail-fsp";
261 fsp,mrc-init-tseg-size = <0>;
262 fsp,mrc-init-mmio-size = <0x800>;
263 fsp,mrc-init-spd-addr1 = <0xa0>;
264 fsp,mrc-init-spd-addr2 = <0xa2>;
265 fsp,emmc-boot-mode = <1>;
273 fsp,lpss-sio-enable-pci-mode;
285 fsp,igd-dvmt50-pre-alloc = <2>;
286 fsp,aperture-size = <2>;
288 fsp,serial-debug-port-address = <0x3f8>;
289 fsp,serial-debug-port-type = <1>;
290 fsp,scc-enable-pci-mode;
291 fsp,os-selection = <4>;
292 fsp,emmc45-ddr50-enabled;
293 fsp,emmc45-retune-timer-value = <8>;
295 fsp,enable-memory-down;
296 fsp,memory-down-params {
297 compatible = "intel,baytrail-fsp-mdp";
298 fsp,dram-speed = <1>;
301 fsp,dimm-width = <1>;
302 fsp,dimm-density = <2>;
303 fsp,dimm-bus-width = <3>;
304 fsp,dimm-sides = <0>;
305 fsp,dimm-tcl = <0xb>;
306 fsp,dimm-trpt-rcd = <0xb>;
307 fsp,dimm-twr = <0xc>;
311 fsp,dimm-tfaw = <0x14>;
317 #include "microcode/m0130673325.dtsi"
320 #include "microcode/m0130679907.dtsi"