arch/x86/dts/galileo.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/mrc/quark.h>
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "reset.dtsi"
  13 /include/ "rtc.dtsi"
  14
  15 #include "tsc_timer.dtsi"
  16
  17 / {
  18         model = "Intel Galileo";
  19         compatible = "intel,galileo", "intel,quark";
  20
  21         aliases {
  22                 spi0 = &spi;
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         chosen {
  30                 stdout-path = &pciuart0;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "cpu-x86";
  40                         reg = <0>;
  41                         intel,apic-id = <0>;
  42                 };
  43         };
  44
  45         mrc {
  46                 compatible = "intel,quark-mrc";
  47                 flags = <MRC_FLAG_SCRAMBLE_EN>;
  48                 dram-width = <DRAM_WIDTH_X8>;
  49                 dram-speed = <DRAM_FREQ_800>;
  50                 dram-type = <DRAM_TYPE_DDR3>;
  51                 rank-mask = <DRAM_RANK(0)>;
  52                 chan-mask = <DRAM_CHANNEL(0)>;
  53                 chan-width = <DRAM_CHANNEL_WIDTH_X16>;
  54                 addr-mode = <DRAM_ADDR_MODE0>;
  55                 refresh-rate = <DRAM_REFRESH_RATE_785US>;
  56                 sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
  57                 ron-value = <DRAM_RON_34OHM>;
  58                 rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
  59                 rd-odt-value = <DRAM_RD_ODT_OFF>;
  60                 dram-density = <DRAM_DENSITY_1G>;
  61                 dram-cl = <6>;
  62                 dram-ras = <0x0000927c>;
  63                 dram-wtr = <0x00002710>;
  64                 dram-rrd = <0x00002710>;
  65                 dram-faw = <0x00009c40>;
  66         };
  67
  68         pci {
  69                 #address-cells = <3>;
  70                 #size-cells = <2>;
  71                 compatible = "pci-x86";
  72                 bootph-all;
  73                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
  74                           0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
  75                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  76
  77                 pciuart0: uart@14,5 {
  78                         compatible = "pci8086,0936.00",
  79                                         "pci8086,0936",
  80                                         "pciclass,070002",
  81                                         "pciclass,0700",
  82                                         "ns16550";
  83                         bootph-all;
  84                         reg = <0x0000a500 0x0 0x0 0x0 0x0
  85                                0x0200a510 0x0 0x0 0x0 0x0>;
  86                         reg-shift = <2>;
  87                         clock-frequency = <44236800>;
  88                         current-speed = <115200>;
  89                 };
  90
  91                 pch@1f,0 {
  92                         reg = <0x0000f800 0 0 0 0>;
  93                         compatible = "intel,pch7";
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96
  97                         irq-router {
  98                                 compatible = "intel,irq-router";
  99                                 intel,pirq-config = "pci";
 100                                 intel,actl-addr = <0x58>;
 101                                 intel,pirq-link = <0x60 8>;
 102                                 intel,pirq-mask = <0xdef8>;
 103                                 intel,pirq-routing = <
 104                                         PCI_BDF(0, 20, 0) INTA PIRQE
 105                                         PCI_BDF(0, 20, 1) INTB PIRQF
 106                                         PCI_BDF(0, 20, 2) INTC PIRQG
 107                                         PCI_BDF(0, 20, 3) INTD PIRQH
 108                                         PCI_BDF(0, 20, 4) INTA PIRQE
 109                                         PCI_BDF(0, 20, 5) INTB PIRQF
 110                                         PCI_BDF(0, 20, 6) INTC PIRQG
 111                                         PCI_BDF(0, 20, 7) INTD PIRQH
 112                                         PCI_BDF(0, 21, 0) INTA PIRQE
 113                                         PCI_BDF(0, 21, 1) INTB PIRQF
 114                                         PCI_BDF(0, 21, 2) INTC PIRQG
 115                                         PCI_BDF(0, 23, 0) INTA PIRQA
 116                                         PCI_BDF(0, 23, 1) INTB PIRQB
 117
 118                                         /* PCIe root ports downstream interrupts */
 119                                         PCI_BDF(1, 0, 0) INTA PIRQA
 120                                         PCI_BDF(1, 0, 0) INTB PIRQB
 121                                         PCI_BDF(1, 0, 0) INTC PIRQC
 122                                         PCI_BDF(1, 0, 0) INTD PIRQD
 123                                         PCI_BDF(2, 0, 0) INTA PIRQB
 124                                         PCI_BDF(2, 0, 0) INTB PIRQC
 125                                         PCI_BDF(2, 0, 0) INTC PIRQD
 126                                         PCI_BDF(2, 0, 0) INTD PIRQA
 127                                 >;
 128                         };
 129
 130                         spi: spi {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                                 compatible = "intel,ich7-spi";
 134                                 spi-flash@0 {
 135                                         #size-cells = <1>;
 136                                         #address-cells = <1>;
 137                                         reg = <0>;
 138                                         compatible = "winbond,w25q64",
 139                                                 "jedec,spi-nor";
 140                                         memory-map = <0xff800000 0x00800000>;
 141                                         rw-mrc-cache {
 142                                                 label = "rw-mrc-cache";
 143                                                 reg = <0x00010000 0x00010000>;
 144                                         };
 145                                 };
 146                         };
 147
 148                         gpioa {
 149                                 compatible = "intel,ich6-gpio";
 150                                 bootph-all;
 151                                 reg = <0 0x20>;
 152                                 bank-name = "A";
 153                         };
 154
 155                         gpiob {
 156                                 compatible = "intel,ich6-gpio";
 157                                 bootph-all;
 158                                 reg = <0x20 0x20>;
 159                                 bank-name = "B";
 160                         };
 161                 };
 162         };
 163
 164         smbios {
 165                 compatible = "u-boot,sysinfo-smbios";
 166
 167                 /*
 168                  * Override the default product name U-Boot reports in the
 169                  * SMBIOS table, to be compatible with the Intel provided UEFI
 170                  * BIOS, as Linux kernel drivers
 171                  * (drivers/mfd/intel_quark_i2c_gpio.c and
 172                  * drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
 173                  * it to do different board level configuration.
 174                  *
 175                  * This can be "Galileo" for GEN1 Galileo board.
 176                  */
 177                 smbios {
 178                         system {
 179                                 product = "GalileoGen2";
 180                         };
 181
 182                         baseboard {
 183                                 product = "GalileoGen2";
 184                         };
 185
 186                         chassis {
 187                                 product = "GalileoGen2";
 188                         };
 189                 };
 190         };
 191
 192 };