1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8 #include <dt-bindings/interrupt-router/intel-irq.h>
10 /include/ "skeleton.dtsi"
11 /include/ "serial.dtsi"
12 /include/ "keyboard.dtsi"
13 /include/ "pcspkr.dtsi"
14 /include/ "reset.dtsi"
17 #include "tsc_timer.dtsi"
18 #include "smbios.dtsi"
21 model = "Intel Crown Bay";
22 compatible = "intel,crownbay", "intel,queensbay";
38 compatible = "cpu-x86";
45 compatible = "cpu-x86";
54 * By default the legacy superio serial port is used as the
55 * U-Boot serial console. If we want to use UART from Topcliff
56 * PCH as the console, change this property to &pciuart#.
58 * For example, stdout-path = &pciuart0 will use the first
59 * UART on Topcliff PCH.
61 stdout-path = "/serial";
66 #include "microcode/m0220661105_cv.dtsi"
73 compatible = "pci-x86";
75 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
76 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
77 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
82 compatible = "pci-bridge";
84 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
89 compatible = "pci-bridge";
91 reg = <0x00010000 0x0 0x0 0x0 0x0>;
94 compatible = "pci8086,8811.00",
100 reg = <0x00025100 0x0 0x0 0x0 0x0
101 0x01025110 0x0 0x0 0x0 0x0>;
103 clock-frequency = <1843200>;
104 current-speed = <115200>;
108 compatible = "pci8086,8812.00",
114 reg = <0x00025200 0x0 0x0 0x0 0x0
115 0x01025210 0x0 0x0 0x0 0x0>;
117 clock-frequency = <1843200>;
118 current-speed = <115200>;
122 compatible = "pci8086,8813.00",
128 reg = <0x00025300 0x0 0x0 0x0 0x0
129 0x01025310 0x0 0x0 0x0 0x0>;
131 clock-frequency = <1843200>;
132 current-speed = <115200>;
136 compatible = "pci8086,8814.00",
142 reg = <0x00025400 0x0 0x0 0x0 0x0
143 0x01025410 0x0 0x0 0x0 0x0>;
145 clock-frequency = <1843200>;
146 current-speed = <115200>;
152 reg = <0x0000f800 0 0 0 0>;
153 compatible = "intel,pch7";
154 #address-cells = <1>;
158 compatible = "intel,irq-router";
159 intel,pirq-config = "pci";
160 intel,actl-addr = <0x58>;
161 intel,pirq-link = <0x60 8>;
162 intel,pirq-mask = <0xcee0>;
163 intel,pirq-routing = <
164 /* TunnelCreek PCI devices */
165 PCI_BDF(0, 2, 0) INTA PIRQE
166 PCI_BDF(0, 3, 0) INTA PIRQF
167 PCI_BDF(0, 23, 0) INTA PIRQA
168 PCI_BDF(0, 23, 0) INTB PIRQB
169 PCI_BDF(0, 23, 0) INTC PIRQC
170 PCI_BDF(0, 23, 0) INTD PIRQD
171 PCI_BDF(0, 24, 0) INTA PIRQB
172 PCI_BDF(0, 24, 0) INTB PIRQC
173 PCI_BDF(0, 24, 0) INTC PIRQD
174 PCI_BDF(0, 24, 0) INTD PIRQA
175 PCI_BDF(0, 25, 0) INTA PIRQC
176 PCI_BDF(0, 25, 0) INTB PIRQD
177 PCI_BDF(0, 25, 0) INTC PIRQA
178 PCI_BDF(0, 25, 0) INTD PIRQB
179 PCI_BDF(0, 26, 0) INTA PIRQD
180 PCI_BDF(0, 26, 0) INTB PIRQA
181 PCI_BDF(0, 26, 0) INTC PIRQB
182 PCI_BDF(0, 26, 0) INTD PIRQC
183 PCI_BDF(0, 27, 0) INTA PIRQG
185 * Topcliff PCI devices
187 * Note on the Crown Bay board, Topcliff
188 * chipset is connected to TunnelCreek
189 * PCIe port 0, so its bus number is 1
190 * for its PCIe port and 2 for its PCI
191 * devices per U-Boot current PCI bus
192 * enumeration algorithm.
194 PCI_BDF(1, 0, 0) INTA PIRQA
195 PCI_BDF(2, 0, 1) INTA PIRQA
196 PCI_BDF(2, 0, 2) INTA PIRQA
197 PCI_BDF(2, 2, 0) INTB PIRQD
198 PCI_BDF(2, 2, 1) INTB PIRQD
199 PCI_BDF(2, 2, 2) INTB PIRQD
200 PCI_BDF(2, 2, 3) INTB PIRQD
201 PCI_BDF(2, 2, 4) INTB PIRQD
202 PCI_BDF(2, 4, 0) INTC PIRQC
203 PCI_BDF(2, 4, 1) INTC PIRQC
204 PCI_BDF(2, 6, 0) INTD PIRQB
205 PCI_BDF(2, 8, 0) INTA PIRQA
206 PCI_BDF(2, 8, 1) INTA PIRQA
207 PCI_BDF(2, 8, 2) INTA PIRQA
208 PCI_BDF(2, 8, 3) INTA PIRQA
209 PCI_BDF(2, 10, 0) INTB PIRQD
210 PCI_BDF(2, 10, 1) INTB PIRQD
211 PCI_BDF(2, 10, 2) INTB PIRQD
212 PCI_BDF(2, 10, 3) INTB PIRQD
213 PCI_BDF(2, 10, 4) INTB PIRQD
214 PCI_BDF(2, 12, 0) INTC PIRQC
215 PCI_BDF(2, 12, 1) INTC PIRQC
216 PCI_BDF(2, 12, 2) INTC PIRQC
217 PCI_BDF(2, 12, 3) INTC PIRQC
218 PCI_BDF(2, 12, 4) INTC PIRQC
223 #address-cells = <1>;
225 compatible = "intel,ich7-spi";
228 compatible = "sst,25vf016b",
230 memory-map = <0xffe00000 0x00200000>;
235 compatible = "intel,ich6-gpio";
242 compatible = "intel,ich6-gpio";