2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
15 model = "Intel Crown Bay";
16 compatible = "intel,crownbay", "intel,queensbay";
32 compatible = "cpu-x86";
39 compatible = "cpu-x86";
47 compatible = "intel,ich6-gpio";
54 compatible = "intel,ich6-gpio";
62 * By default the legacy superio serial port is used as the
63 * U-Boot serial console. If we want to use UART from Topcliff
64 * PCH as the console, change this property to &pciuart#.
66 * For example, stdout-path = &pciuart0 will use the first
67 * UART on Topcliff PCH.
69 stdout-path = "/serial";
75 compatible = "intel,ich-spi";
78 compatible = "sst,25vf016b", "spi-flash";
79 memory-map = <0xffe00000 0x00200000>;
85 #include "microcode/m0220661105_cv.dtsi"
92 compatible = "intel,pci";
98 compatible = "intel,pci";
102 #address-cells = <3>;
104 compatible = "intel,pci";
108 compatible = "pci8086,8811.00",
113 reg = <0x00025100 0x0 0x0 0x0 0x0
114 0x01025110 0x0 0x0 0x0 0x0>;
116 clock-frequency = <1843200>;
117 current-speed = <115200>;
121 compatible = "pci8086,8812.00",
126 reg = <0x00025200 0x0 0x0 0x0 0x0
127 0x01025210 0x0 0x0 0x0 0x0>;
129 clock-frequency = <1843200>;
130 current-speed = <115200>;
134 compatible = "pci8086,8813.00",
139 reg = <0x00025300 0x0 0x0 0x0 0x0
140 0x01025310 0x0 0x0 0x0 0x0>;
142 clock-frequency = <1843200>;
143 current-speed = <115200>;
147 compatible = "pci8086,8814.00",
152 reg = <0x00025400 0x0 0x0 0x0 0x0
153 0x01025410 0x0 0x0 0x0 0x0>;
155 clock-frequency = <1843200>;
156 current-speed = <115200>;
162 reg = <0x0000f800 0 0 0 0>;
163 compatible = "intel,irq-router";
164 intel,pirq-config = "pci";
165 intel,pirq-link = <0x60 8>;
166 intel,pirq-mask = <0xdee0>;
167 intel,pirq-routing = <
168 /* TunnelCreek PCI devices */
169 PCI_BDF(0, 2, 0) INTA PIRQE
170 PCI_BDF(0, 3, 0) INTA PIRQF
171 PCI_BDF(0, 23, 0) INTA PIRQE
172 PCI_BDF(0, 24, 0) INTA PIRQF
173 PCI_BDF(0, 25, 0) INTA PIRQG
174 PCI_BDF(0, 26, 0) INTA PIRQH
175 PCI_BDF(0, 27, 0) INTA PIRQG
177 * Topcliff PCI devices
179 * Note on the Crown Bay board, Topcliff chipset
180 * is connected to TunnelCreek PCIe port 0, so
181 * its bus number is 1 for its PCIe port and 2
182 * for its PCI devices per U-Boot currnet PCI
183 * bus enumeration algorithm.
185 PCI_BDF(1, 0, 0) INTA PIRQA
186 PCI_BDF(2, 0, 1) INTA PIRQA
187 PCI_BDF(2, 0, 2) INTA PIRQA
188 PCI_BDF(2, 2, 0) INTB PIRQB
189 PCI_BDF(2, 2, 1) INTB PIRQB
190 PCI_BDF(2, 2, 2) INTB PIRQB
191 PCI_BDF(2, 2, 3) INTB PIRQB
192 PCI_BDF(2, 2, 4) INTB PIRQB
193 PCI_BDF(2, 4, 0) INTC PIRQC
194 PCI_BDF(2, 4, 1) INTC PIRQC
195 PCI_BDF(2, 6, 0) INTD PIRQD
196 PCI_BDF(2, 8, 0) INTA PIRQA
197 PCI_BDF(2, 8, 1) INTA PIRQA
198 PCI_BDF(2, 8, 2) INTA PIRQA
199 PCI_BDF(2, 8, 3) INTA PIRQA
200 PCI_BDF(2, 10, 0) INTB PIRQB
201 PCI_BDF(2, 10, 1) INTB PIRQB
202 PCI_BDF(2, 10, 2) INTB PIRQB
203 PCI_BDF(2, 10, 3) INTB PIRQB
204 PCI_BDF(2, 10, 4) INTB PIRQB
205 PCI_BDF(2, 12, 0) INTC PIRQC
206 PCI_BDF(2, 12, 1) INTC PIRQC
207 PCI_BDF(2, 12, 2) INTC PIRQC
208 PCI_BDF(2, 12, 3) INTC PIRQC
209 PCI_BDF(2, 12, 4) INTC PIRQC