arch/x86/dts/conga-qeval20-qa3-e3845.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /dts-v1/;
   9
  10 #include <dt-bindings/gpio/x86-gpio.h>
  11 #include <dt-bindings/interrupt-router/intel-irq.h>
  12
  13 /include/ "skeleton.dtsi"
  14 /include/ "serial.dtsi"
  15 /include/ "rtc.dtsi"
  16 /include/ "tsc_timer.dtsi"
  17
  18 / {
  19         model = "congatec-QEVAL20-QA3-E3845";
  20         compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
  21
  22         aliases {
  23                 serial0 = &serial;
  24                 spi0 = &spi;
  25         };
  26
  27         config {
  28                 silent_console = <0>;
  29         };
  30
  31         pch_pinctrl {
  32                 compatible = "intel,x86-pinctrl";
  33                 reg = <0 0>;
  34
  35                 /*
  36                  * As of today, the latest version FSP (gold4) for BayTrail
  37                  * misses the PAD configuration of the SD controller's Card
  38                  * Detect signal. The default PAD value for the CD pin sets
  39                  * the pin to work in GPIO mode, which causes card detect
  40                  * status cannot be reflected by the Present State register
  41                  * in the SD controller (bit 16 & bit 18 are always zero).
  42                  *
  43                  * Configure this pin to function 1 (SD controller).
  44                  */
  45                 sdmmc3_cd@0 {
  46                         pad-offset = <0x3a0>;
  47                         mode-func = <1>;
  48                 };
  49
  50                 /* Add SMBus PAD configuration */
  51                 smbus_clk@0 {
  52                         pad-offset = <0x580>;
  53                         mode-func = <1>;
  54                 };
  55
  56                 smbus_data@0 {
  57                         pad-offset = <0x5a0>;
  58                         mode-func = <1>;
  59                 };
  60         };
  61
  62         chosen {
  63                 stdout-path = "/serial";
  64         };
  65
  66         cpus {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69
  70                 cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "intel,baytrail-cpu";
  73                         reg = <0>;
  74                         intel,apic-id = <0>;
  75                 };
  76
  77                 cpu@1 {
  78                         device_type = "cpu";
  79                         compatible = "intel,baytrail-cpu";
  80                         reg = <1>;
  81                         intel,apic-id = <2>;
  82                 };
  83
  84                 cpu@2 {
  85                         device_type = "cpu";
  86                         compatible = "intel,baytrail-cpu";
  87                         reg = <2>;
  88                         intel,apic-id = <4>;
  89                 };
  90
  91                 cpu@3 {
  92                         device_type = "cpu";
  93                         compatible = "intel,baytrail-cpu";
  94                         reg = <3>;
  95                         intel,apic-id = <6>;
  96                 };
  97         };
  98
  99         pci {
 100                 compatible = "intel,pci-baytrail", "pci-x86";
 101                 #address-cells = <3>;
 102                 #size-cells = <2>;
 103                 u-boot,dm-pre-reloc;
 104                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 105                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 106                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 107
 108                 pch@1f,0 {
 109                         reg = <0x0000f800 0 0 0 0>;
 110                         compatible = "pci8086,0f1c", "intel,pch9";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113
 114                         irq-router {
 115                                 compatible = "intel,irq-router";
 116                                 intel,pirq-config = "ibase";
 117                                 intel,ibase-offset = <0x50>;
 118                                 intel,actl-addr = <0>;
 119                                 intel,pirq-link = <8 8>;
 120                                 intel,pirq-mask = <0xdee0>;
 121                                 intel,pirq-routing = <
 122                                         /* BayTrail PCI devices */
 123                                         PCI_BDF(0, 2, 0) INTA PIRQA
 124                                         PCI_BDF(0, 3, 0) INTA PIRQA
 125                                         PCI_BDF(0, 16, 0) INTA PIRQA
 126                                         PCI_BDF(0, 17, 0) INTA PIRQA
 127                                         PCI_BDF(0, 18, 0) INTA PIRQA
 128                                         PCI_BDF(0, 19, 0) INTA PIRQA
 129                                         PCI_BDF(0, 20, 0) INTA PIRQA
 130                                         PCI_BDF(0, 21, 0) INTA PIRQA
 131                                         PCI_BDF(0, 22, 0) INTA PIRQA
 132                                         PCI_BDF(0, 23, 0) INTA PIRQA
 133                                         PCI_BDF(0, 24, 0) INTA PIRQA
 134                                         PCI_BDF(0, 24, 1) INTC PIRQC
 135                                         PCI_BDF(0, 24, 2) INTD PIRQD
 136                                         PCI_BDF(0, 24, 3) INTB PIRQB
 137                                         PCI_BDF(0, 24, 4) INTA PIRQA
 138                                         PCI_BDF(0, 24, 5) INTC PIRQC
 139                                         PCI_BDF(0, 24, 6) INTD PIRQD
 140                                         PCI_BDF(0, 24, 7) INTB PIRQB
 141                                         PCI_BDF(0, 26, 0) INTA PIRQA
 142                                         PCI_BDF(0, 27, 0) INTA PIRQA
 143                                         PCI_BDF(0, 28, 0) INTA PIRQA
 144                                         PCI_BDF(0, 28, 1) INTB PIRQB
 145                                         PCI_BDF(0, 28, 2) INTC PIRQC
 146                                         PCI_BDF(0, 28, 3) INTD PIRQD
 147                                         PCI_BDF(0, 29, 0) INTA PIRQA
 148                                         PCI_BDF(0, 30, 0) INTA PIRQA
 149                                         PCI_BDF(0, 30, 1) INTD PIRQD
 150                                         PCI_BDF(0, 30, 2) INTB PIRQB
 151                                         PCI_BDF(0, 30, 3) INTC PIRQC
 152                                         PCI_BDF(0, 30, 4) INTD PIRQD
 153                                         PCI_BDF(0, 30, 5) INTB PIRQB
 154                                         PCI_BDF(0, 31, 3) INTB PIRQB
 155
 156                                         /*
 157                                          * PCIe root ports downstream
 158                                          * interrupts
 159                                          */
 160                                         PCI_BDF(1, 0, 0) INTA PIRQA
 161                                         PCI_BDF(1, 0, 0) INTB PIRQB
 162                                         PCI_BDF(1, 0, 0) INTC PIRQC
 163                                         PCI_BDF(1, 0, 0) INTD PIRQD
 164                                         PCI_BDF(2, 0, 0) INTA PIRQB
 165                                         PCI_BDF(2, 0, 0) INTB PIRQC
 166                                         PCI_BDF(2, 0, 0) INTC PIRQD
 167                                         PCI_BDF(2, 0, 0) INTD PIRQA
 168                                         PCI_BDF(3, 0, 0) INTA PIRQC
 169                                         PCI_BDF(3, 0, 0) INTB PIRQD
 170                                         PCI_BDF(3, 0, 0) INTC PIRQA
 171                                         PCI_BDF(3, 0, 0) INTD PIRQB
 172                                         PCI_BDF(4, 0, 0) INTA PIRQD
 173                                         PCI_BDF(4, 0, 0) INTB PIRQA
 174                                         PCI_BDF(4, 0, 0) INTC PIRQB
 175                                         PCI_BDF(4, 0, 0) INTD PIRQC
 176                                 >;
 177                         };
 178
 179                         spi: spi {
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 compatible = "intel,ich9-spi";
 183                                 spi-flash@0 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <1>;
 186                                         reg = <0>;
 187                                         compatible = "stmicro,n25q064a",
 188                                                 "spi-flash";
 189                                         memory-map = <0xff800000 0x00800000>;
 190                                         rw-mrc-cache {
 191                                                 label = "rw-mrc-cache";
 192                                                 reg = <0x006f0000 0x00010000>;
 193                                         };
 194                                 };
 195                         };
 196
 197                         gpioa {
 198                                 compatible = "intel,ich6-gpio";
 199                                 u-boot,dm-pre-reloc;
 200                                 reg = <0 0x20>;
 201                                 bank-name = "A";
 202                                 use-lvl-write-cache;
 203                         };
 204
 205                         gpiob {
 206                                 compatible = "intel,ich6-gpio";
 207                                 u-boot,dm-pre-reloc;
 208                                 reg = <0x20 0x20>;
 209                                 bank-name = "B";
 210                                 use-lvl-write-cache;
 211                         };
 212
 213                         gpioc {
 214                                 compatible = "intel,ich6-gpio";
 215                                 u-boot,dm-pre-reloc;
 216                                 reg = <0x40 0x20>;
 217                                 bank-name = "C";
 218                                 use-lvl-write-cache;
 219                         };
 220
 221                         gpiod {
 222                                 compatible = "intel,ich6-gpio";
 223                                 u-boot,dm-pre-reloc;
 224                                 reg = <0x60 0x20>;
 225                                 bank-name = "D";
 226                                 use-lvl-write-cache;
 227                         };
 228
 229                         gpioe {
 230                                 compatible = "intel,ich6-gpio";
 231                                 u-boot,dm-pre-reloc;
 232                                 reg = <0x80 0x20>;
 233                                 bank-name = "E";
 234                                 use-lvl-write-cache;
 235                         };
 236
 237                         gpiof {
 238                                 compatible = "intel,ich6-gpio";
 239                                 u-boot,dm-pre-reloc;
 240                                 reg = <0xA0 0x20>;
 241                                 bank-name = "F";
 242                                 use-lvl-write-cache;
 243                         };
 244                 };
 245         };
 246
 247         fsp {
 248                 compatible = "intel,baytrail-fsp";
 249                 fsp,mrc-init-tseg-size = <0>;
 250                 fsp,mrc-init-mmio-size = <0x800>;
 251                 fsp,mrc-init-spd-addr1 = <0xa0>;
 252                 fsp,mrc-init-spd-addr2 = <0xa2>;
 253                 fsp,emmc-boot-mode = <1>;
 254                 fsp,enable-sdio;
 255                 fsp,enable-sdcard;
 256                 fsp,enable-hsuart1;
 257                 fsp,enable-spi;
 258                 fsp,enable-sata;
 259                 fsp,sata-mode = <1>;
 260                 fsp,enable-lpe;
 261                 fsp,lpss-sio-enable-pci-mode;
 262                 fsp,enable-dma0;
 263                 fsp,enable-dma1;
 264                 fsp,enable-pwm0;
 265                 fsp,enable-pwm1;
 266                 fsp,igd-dvmt50-pre-alloc = <2>;
 267                 fsp,aperture-size = <2>;
 268                 fsp,gtt-size = <2>;
 269                 fsp,scc-enable-pci-mode;
 270                 fsp,os-selection = <4>;
 271                 fsp,emmc45-ddr50-enabled;
 272                 fsp,emmc45-retune-timer-value = <8>;
 273                 fsp,enable-igd;
 274                 fsp,enable-memory-down;
 275                 fsp,memory-down-params {
 276                         compatible = "intel,baytrail-fsp-mdp";
 277                         fsp,dram-speed = <2>;           /* 2=1333MHz */
 278                         fsp,dram-type = <1>;            /* 1=DDR3L */
 279                         fsp,dimm-0-enable;
 280                         fsp,dimm-1-enable;
 281                         fsp,dimm-width = <1>;           /* 1=x16, 2=x32 */
 282                         fsp,dimm-density = <2>;         /* 2=4Gbit */
 283                         fsp,dimm-bus-width = <3>;       /* 3=64bits */
 284                         fsp,dimm-sides = <0>;           /* 0=1 ranks -> 0x2b */
 285
 286                         /* These following values might need a re-visit */
 287                         fsp,dimm-tcl = <8>;
 288                         fsp,dimm-trpt-rcd = <8>;
 289                         fsp,dimm-twr = <8>;
 290                         fsp,dimm-twtr = <4>;
 291                         fsp,dimm-trrd = <6>;
 292                         fsp,dimm-trtp = <4>;
 293                         fsp,dimm-tfaw = <22>;
 294                 };
 295         };
 296
 297         microcode {
 298                 update@0 {
 299 #include "microcode/m0130673325.dtsi"
 300                 };
 301                 update@1 {
 302 #include "microcode/m0130679907.dtsi"
 303                 };
 304         };
 305 };