arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "reset.dtsi"
   6 /include/ "rtc.dtsi"
   7
   8 #include "tsc_timer.dtsi"
   9 #include "smbios.dtsi"
  10
  11 / {
  12         model = "Google Panther";
  13         compatible = "google,panther", "intel,haswell";
  14
  15         aliases {
  16                 spi0 = &spi;
  17         };
  18
  19         config {
  20                 silent-console = <0>;
  21                 no-keyboard;
  22         };
  23
  24         chosen {
  25                 stdout-path = "/serial";
  26         };
  27
  28         pci {
  29                 compatible = "pci-x86";
  30                 #address-cells = <3>;
  31                 #size-cells = <2>;
  32                 bootph-all;
  33                 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  34                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  35                         0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  36
  37                 pch@1f,0 {
  38                         reg = <0x0000f800 0 0 0 0>;
  39                         compatible = "intel,pch9";
  40                         #address-cells = <1>;
  41                         #size-cells = <1>;
  42
  43                         spi: spi {
  44                                 #address-cells = <1>;
  45                                 #size-cells = <0>;
  46                                 compatible = "intel,ich9-spi";
  47                                 spi-flash@0 {
  48                                         #size-cells = <1>;
  49                                         #address-cells = <1>;
  50                                         reg = <0>;
  51                                         m25p,fast-read;
  52                                         compatible = "winbond,w25q64",
  53                                                 "jedec,spi-nor";
  54                                         memory-map = <0xff800000 0x00800000>;
  55                                         rw-mrc-cache {
  56                                                 label = "rw-mrc-cache";
  57                                                 reg = <0x003e0000 0x00010000>;
  58                                         };
  59                                 };
  60                         };
  61
  62                         gpioa {
  63                                 compatible = "intel,ich6-gpio";
  64                                 bootph-all;
  65                                 reg = <0 0x10>;
  66                                 bank-name = "A";
  67                         };
  68
  69                         gpiob {
  70                                 compatible = "intel,ich6-gpio";
  71                                 bootph-all;
  72                                 reg = <0x30 0x10>;
  73                                 bank-name = "B";
  74                         };
  75
  76                         gpioc {
  77                                 compatible = "intel,ich6-gpio";
  78                                 bootph-all;
  79                                 reg = <0x40 0x10>;
  80                                 bank-name = "C";
  81                         };
  82                 };
  83         };
  84
  85         tpm {
  86                 reg = <0xfed40000 0x5000>;
  87                 compatible = "infineon,slb9635lpc";
  88         };
  89
  90 };