arch/x86/dts/chromebook_coral.dts

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/x86-gpio.h>
   5
   6 /include/ "skeleton.dtsi"
   7 /include/ "keyboard.dtsi"
   8 /include/ "reset.dtsi"
   9 /include/ "rtc.dtsi"
  10 /include/ "tsc_timer.dtsi"
  11
  12 #ifdef CONFIG_CHROMEOS_VBOOT
  13 #include "chromeos-x86.dtsi"
  14 #include "flashmap-x86-ro.dtsi"
  15 #include "flashmap-16mb-rw.dtsi"
  16 #endif
  17
  18 #include <dt-bindings/clock/intel-clock.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20 #include <dt-bindings/interrupt-controller/x86-irq.h>
  21 #include <asm/e820.h>
  22 #include <asm/intel_pinctrl_defs.h>
  23 #include <asm/arch-apollolake/cpu.h>
  24 #include <asm/arch-apollolake/gpe.h>
  25 #include <asm/arch-apollolake/gpio.h>
  26 #include <asm/arch-apollolake/iomap.h>
  27 #include <asm/arch-apollolake/pm.h>
  28 #include <dt-bindings/clock/intel-clock.h>
  29 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
  30 #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
  31 #include <dt-bindings/sound/nhlt.h>
  32
  33 / {
  34         model = "Google Coral";
  35         compatible = "google,coral", "intel,apollolake";
  36
  37         aliases {
  38                 cros-ec0 = &cros_ec;
  39                 fsp = &fsp_s;
  40                 spi0 = &spi;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 mmc1 = &sdmmc;
  50         };
  51
  52         board: board {
  53                 compatible = "google,coral";
  54                 recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
  55                 write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
  56                 phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
  57                 smbios {
  58                         /* Type 1 table */
  59                         system {
  60                                 manufacturer = "Google";
  61                                 product = "Coral";
  62                                 version = "rev2";
  63                                 serial = "123456789";
  64                                 sku = "sku3";
  65                                 family = "Google_Coral";
  66                         };
  67
  68                         /* Type 2 table */
  69                         baseboard {
  70                                 manufacturer = "Google";
  71                                 product = "Coral";
  72                                 asset-tag = "ABC123";
  73                         };
  74
  75                         /* Type 3 table */
  76                         chassis {
  77                                 manufacturer = "Google";
  78                         };
  79                 };
  80         };
  81
  82         config {
  83                silent_console = <0>;
  84         };
  85
  86         chosen {
  87                 stdout-path = &serial;
  88                 e820-entries = /bits/ 64 <
  89                         IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
  90                         MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
  91                 u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3
  92                         &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5
  93                         &sdmmc &maxim_codec &wifi &da_codec &tpm
  94                         &elan_touchscreen &raydium_touchscreen
  95                         &elan_touchpad &synaptics_touchpad &wacom_digitizer>;
  96                 u-boot,acpi-dsdt-order = <&board &lpc>;
  97         };
  98
  99         clk: clock {
 100                 compatible = "intel,apl-clk";
 101                 #clock-cells = <1>;
 102         };
 103
 104         cpus {
 105                 u-boot,dm-pre-reloc;
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108
 109                 cpu_0: cpu@0 {
 110                         u-boot,dm-pre-reloc;
 111                         device_type = "cpu";
 112                         compatible = "intel,apl-cpu";
 113                         reg = <0>;
 114                         intel,apic-id = <0>;
 115                 };
 116
 117                 cpu_1: cpu@1 {
 118                         device_type = "cpu";
 119                         compatible = "intel,apl-cpu";
 120                         reg = <1>;
 121                         intel,apic-id = <2>;
 122                 };
 123
 124                 cpu_2: cpu@2 {
 125                         device_type = "cpu";
 126                         compatible = "intel,apl-cpu";
 127                         reg = <2>;
 128                         intel,apic-id = <4>;
 129                 };
 130
 131                 cpu_3: cpu@3 {
 132                         device_type = "cpu";
 133                         compatible = "intel,apl-cpu";
 134                         reg = <3>;
 135                         intel,apic-id = <6>;
 136                 };
 137
 138         };
 139
 140         acpi_gpe: general-purpose-events {
 141                 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 142                 compatible = "intel,acpi-gpe";
 143                 interrupt-controller;
 144                 #interrupt-cells = <2>;
 145         };
 146
 147         keyboard {
 148                 intel,duplicate-por;
 149         };
 150
 151         pci {
 152                 compatible = "pci-x86";
 153                 #address-cells = <3>;
 154                 #size-cells = <2>;
 155                 u-boot,dm-pre-reloc;
 156                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 157                         0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
 158                         0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 159                 u-boot,skip-auto-config-until-reloc;
 160
 161                 host_bridge: host-bridge@0,0 {
 162                         u-boot,dm-pre-reloc;
 163                         reg = <0x00000000 0 0 0 0>;
 164                         compatible = "intel,apl-hostbridge";
 165                         pciex-region-size = <0x10000000>;
 166                         fspm,training-delay = <21>;
 167                         /*
 168                          * Parameters used by the FSP-S binary blob. This is
 169                          * really unfortunate since these parameters mostly
 170                          * relate to drivers but we need them in one place. We
 171                          * could put them in the driver nodes easily, but then
 172                          * would have to scan each node to find them. So just
 173                          * dump them here for now.
 174                          */
 175                         fsp_s: fsp-s {
 176                         };
 177
 178                         nhlt {
 179                                 intel,dmic-channels = <4>;
 180                         };
 181                 };
 182
 183                 punit@0,1 {
 184                         u-boot,dm-pre-reloc;
 185                         reg = <0x00000800 0 0 0 0>;
 186                         compatible = "intel,apl-punit";
 187                 };
 188
 189                 gma@2,0 {
 190                         reg = <0x00001000 0 0 0 0>;
 191                         compatible = "fsp-fb";
 192                 };
 193
 194                 p2sb: p2sb@d,0 {
 195                         u-boot,dm-pre-reloc;
 196                         reg = <0x02006810 0 0 0 0>;
 197                         compatible = "intel,p2sb";
 198                         early-regs = <IOMAP_P2SB_BAR 0x100000>;
 199                         pci,no-autoconfig;
 200
 201                         n {
 202                                 compatible = "intel,apl-pinctrl";
 203                                 u-boot,dm-pre-reloc;
 204                                 intel,p2sb-port-id = <PID_GPIO_N>;
 205                                 acpi,path = "\\_SB.GPO0";
 206                                 gpio_n: gpio-n {
 207                                         compatible = "intel,gpio";
 208                                         u-boot,dm-pre-reloc;
 209                                         gpio-controller;
 210                                         #gpio-cells = <2>;
 211                                         linux-name = "INT3452:00";
 212                                 };
 213                         };
 214
 215                         nw {
 216                                 u-boot,dm-pre-reloc;
 217                                 compatible = "intel,apl-pinctrl";
 218                                 intel,p2sb-port-id = <PID_GPIO_NW>;
 219                                 #gpio-cells = <2>;
 220                                 acpi,path = "\\_SB.GPO1";
 221                                 gpio_nw: gpio-nw {
 222                                         compatible = "intel,gpio";
 223                                         u-boot,dm-pre-reloc;
 224                                         gpio-controller;
 225                                         #gpio-cells = <2>;
 226                                         linux-name = "INT3452:01";
 227                                 };
 228                         };
 229
 230                         w {
 231                                 u-boot,dm-pre-reloc;
 232                                 compatible = "intel,apl-pinctrl";
 233                                 intel,p2sb-port-id = <PID_GPIO_W>;
 234                                 #gpio-cells = <2>;
 235                                 acpi,path = "\\_SB.GPO2";
 236                                 gpio_w: gpio-w {
 237                                         compatible = "intel,gpio";
 238                                         u-boot,dm-pre-reloc;
 239                                         gpio-controller;
 240                                         #gpio-cells = <2>;
 241                                         linux-name = "INT3452:02";
 242                                 };
 243                         };
 244
 245                         sw {
 246                                 u-boot,dm-pre-reloc;
 247                                 compatible = "intel,apl-pinctrl";
 248                                 intel,p2sb-port-id = <PID_GPIO_SW>;
 249                                 #gpio-cells = <2>;
 250                                 acpi,path = "\\_SB.GPO3";
 251                                 gpio_sw: gpio-sw {
 252                                         compatible = "intel,gpio";
 253                                         u-boot,dm-pre-reloc;
 254                                         gpio-controller;
 255                                         #gpio-cells = <2>;
 256                                         linux-name = "INT3452:03";
 257                                 };
 258                         };
 259
 260                         itss {
 261                                 u-boot,dm-pre-reloc;
 262                                 compatible = "intel,itss";
 263                                 intel,p2sb-port-id = <PID_ITSS>;
 264                                 intel,pmc-routes = <
 265                                         PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
 266                                         PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
 267                                         PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
 268                                         PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
 269                                         PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
 270                                         PMC_GPE_N_31_0 GPIO_GPE_N_31_0
 271                                         PMC_GPE_N_63_32 GPIO_GPE_N_63_32
 272                                         PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
 273                         };
 274                 };
 275
 276                 pmc@d,1 {
 277                         u-boot,dm-pre-reloc;
 278                         reg = <0x6900 0 0 0 0>;
 279
 280                         /*
 281                          * Values for BAR0, BAR2 and ACPI_BASE for when PCI
 282                          * auto-configure is not available
 283                          */
 284                         early-regs = <0xfe042000 0x2000
 285                                 0xfe044000 0x2000
 286                                 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 287                         compatible = "intel,apl-pmc";
 288                         gpe0-dwx-mask = <0xf>;
 289                         gpe0-dwx-shift-base = <4>;
 290
 291                         /*
 292                          * GPE configuration
 293                          * Note that GPE events called out in ASL code rely on
 294                          * this route, i.e., if this route changes then the
 295                          * affected GPE * offset bits also need to be changed.
 296                          * This sets the PMC register GPE_CFG fields.
 297                          */
 298                         gpe0-dw = <PMC_GPE_N_31_0
 299                                 PMC_GPE_N_63_32
 300                                 PMC_GPE_SW_31_0>;
 301                         gpe0-sts = <0x20>;
 302                         gpe0-en = <0x30>;
 303                 };
 304
 305                 audio@e,0 {
 306                         reg = <0x7000 0 0 0 0>;
 307                         compatible = "simple-bus";
 308                         acpi,name = "HDAS";
 309                         i2s {
 310                                 compatible = "fred";
 311                         };
 312                         maxim_codec: maxim-codec {
 313                                 compatible = "maxim,max98357a";
 314                                 acpi,ddn = "Maxim Integrated 98357A Amplifier";
 315                                 sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>;
 316                                 sdmode-delay = <5>;
 317                                 acpi,name = "MAXM";
 318                                 acpi,hid = "MX98357A";
 319                                 acpi,audio-link = <AUDIO_LINK_SSP5>;
 320                         };
 321                 };
 322
 323                 spi: fast-spi@d,2 {
 324                         u-boot,dm-pre-reloc;
 325                         reg = <0x02006a10 0 0 0 0>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         compatible = "intel,fast-spi";
 329                         early-regs = <IOMAP_SPI_BASE 0x1000>;
 330                         intel,hardware-seq = <1>;
 331
 332                         fwstore_spi: spi-flash@0 {
 333                                 #size-cells = <1>;
 334                                 #address-cells = <1>;
 335                                 u-boot,dm-pre-reloc;
 336                                 reg = <0>;
 337                                 compatible = "winbond,w25q128fw",
 338                                          "jedec,spi-nor";
 339                                 rw-mrc-cache {
 340                                         label = "rw-mrc-cache";
 341                                         reg = <0x008e0000 0x00010000>;
 342                                         u-boot,dm-pre-reloc;
 343                                 };
 344                                 rw-var-mrc-cache {
 345                                         label = "rw-mrc-cache";
 346                                         reg = <0x008f0000 0x0001000>;
 347                                         u-boot,dm-pre-reloc;
 348                                 };
 349                         };
 350                 };
 351
 352                 /* WiFi */
 353                 pcie-a0@14,0 {
 354                         reg = <0x0000a000 0 0 0 0>;
 355                         acpi,name = "RP01";
 356                         wifi: wifi {
 357                                 compatible = "intel,generic-wifi";
 358                                 acpi,ddn = "Intel WiFi";
 359                                 acpi,name = "WF00";
 360                                 acpi,wake = <GPE0_DW3_00>;
 361                                 interrupts-extended = <&acpi_gpe 0x3c 0>;
 362                         };
 363                 };
 364
 365                 i2c_0: i2c2@16,0 {
 366                         compatible = "intel,apl-i2c";
 367                         reg = <0x0200b010 0 0 0 0>;
 368                         clocks = <&clk CLK_I2C>;
 369                         i2c-scl-rising-time-ns = <104>;
 370                         i2c-scl-falling-time-ns = <52>;
 371                         clock-frequency = <400000>;
 372                         i2c,speeds = <100000 400000 1000000>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         da_codec: da-codec {
 376                                 reg = <0x1a>;
 377                                 compatible = "dlg,da7219";
 378                                 interrupts-extended = <&acpi_gpe GPIO_116_IRQ
 379                                         (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
 380                                 acpi,name = "DLG7";
 381                                 acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec";
 382                                 acpi,audio-link = <AUDIO_LINK_SSP1>;
 383                                 dlg,micbias-lvl = <2600>;
 384                                 dlg,mic-amp-in-sel = "diff";
 385                                 da7219_aad {
 386                                         dlg,btn-cfg = <50>;
 387                                         dlg,mic-det-thr = <500>;
 388                                         dlg,jack-ins-deb = <20>;
 389                                         dlg,jack-det-rate = "32ms_64ms";
 390                                         dlg,jack-rem-deb = <1>;
 391                                         dlg,a-d-btn-thr = <0xa>;
 392                                         dlg,d-b-btn-thr = <0x16>;
 393                                         dlg,b-c-btn-thr = <0x21>;
 394                                         dlg,c-mic-btn-thr = <0x3e>;
 395                                         dlg,btn-avg = <4>;
 396                                         dlg,adc-1bit-rpt = <1>;
 397                                 };
 398                         };
 399                 };
 400
 401                 i2c_1: i2c2@16,1 {
 402                         compatible = "intel,apl-i2c";
 403                         reg = <0x0200b110 0 0 0 0>;
 404                         clocks = <&clk CLK_I2C>;
 405                         clock-frequency = <400000>;
 406                         i2c,speeds = <100000 400000 1000000 3400000>;
 407                         i2c-scl-rising-time-ns = <52>;
 408                         i2c-scl-falling-time-ns = <52>;
 409                 };
 410
 411                 i2c_2: i2c2@16,2 {
 412                         compatible = "intel,apl-i2c";
 413                         reg = <0x0200b210 0 0 0 0>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         clock-frequency = <400000>;
 417                         i2c,speeds = <100000 400000 1000000>;
 418                         clocks = <&clk CLK_I2C>;
 419                         i2c-scl-rising-time-ns = <57>;
 420                         i2c-scl-falling-time-ns = <28>;
 421                         tpm: tpm@50 {
 422                                 reg = <0x50>;
 423                                 compatible = "google,cr50";
 424                                 u-boot,i2c-offset-len = <0>;
 425                                 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 426                                 interrupts-extended = <&acpi_gpe GPIO_28_IRQ
 427                                          IRQ_TYPE_EDGE_FALLING>;
 428                                 acpi,hid = "GOOG0005";
 429                                 acpi,ddn = "I2C TPM";
 430                                 acpi,name = "TPMI";
 431                         };
 432                 };
 433
 434                 i2c_3: i2c2@16,3 {
 435                         compatible = "intel,apl-i2c";
 436                         reg = <0x0200b310 0 0 0 0>;
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         clocks = <&clk CLK_I2C>;
 440                         i2c-scl-rising-time-ns = <76>;
 441                         i2c-scl-falling-time-ns = <164>;
 442                         clock-frequency = <400000>;
 443                         i2c,speeds = <100000 400000>;
 444                         elan_touchscreen: elan-touchscreen@10 {
 445                                 compatible = "i2c-chip";
 446                                 reg = <0x10>;
 447                                 acpi,hid = "ELAN0001";
 448                                 acpi,ddn = "ELAN Touchscreen";
 449                                 interrupts-extended = <&acpi_gpe GPIO_21_IRQ
 450                                         IRQ_TYPE_EDGE_FALLING>;
 451                                 linux,probed;
 452                                 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
 453                                 reset-delay-ms = <20>;
 454                                 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
 455                                 enable-delay-ms = <1>;
 456                                 acpi,has-power-resource;
 457                         };
 458
 459                         raydium_touchscreen: raydium-touchscreen@39 {
 460                                 compatible = "i2c-chip";
 461                                 reg = <0x39>;
 462                                 acpi,hid = "RAYD0001";
 463                                 acpi,ddn = "Raydium Touchscreen";
 464                                 interrupts-extended = <&acpi_gpe GPIO_21_IRQ
 465                                         IRQ_TYPE_EDGE_FALLING>;
 466                                 linux,probed;
 467                                 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
 468                                 reset-delay-ms = <1>;
 469                                 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
 470                                 enable-delay-ms = <50>;
 471                                 acpi,has-power-resource;
 472                         };
 473                 };
 474
 475                 i2c_4: i2c2@17,0 {
 476                         compatible = "intel,apl-i2c";
 477                         reg = <0x0200b810 0 0 0 0>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         clocks = <&clk CLK_I2C>;
 481                         i2c-sda-hold-time-ns = <350>;
 482                         i2c-scl-rising-time-ns = <114>;
 483                         i2c-scl-falling-time-ns = <164>;
 484                         clock-frequency = <400000>;
 485                         i2c,speeds = <100000 400000>;
 486                         elan_touchpad: elan-touchpad@15 {
 487                                 compatible = "i2c-chip";
 488                                 reg = <0x15>;
 489                                 u-boot,i2c-offset-len = <0>;
 490                                 acpi,hid = "ELAN0000";
 491                                 acpi,ddn = "ELAN Touchpad";
 492                                 interrupts-extended = <&acpi_gpe GPIO_18_IRQ
 493                                          IRQ_TYPE_EDGE_FALLING>;
 494                                 acpi,wake = <GPE0_DW1_15>;
 495                                 linux,probed;
 496                         };
 497                         synaptics_touchpad: synaptics-touchpad@2c {
 498                                 compatible = "hid-over-i2c";
 499                                 reg = <0x2c>;
 500                                 acpi,hid = "PNP0C50";
 501                                 acpi,ddn = "Synaptics Touchpad";
 502                                 interrupts-extended = <&acpi_gpe GPIO_18_IRQ
 503                                          IRQ_TYPE_EDGE_FALLING>;
 504                                 acpi,wake = <GPE0_DW1_15>;
 505                                 linux,probed;
 506                                 hid-descr-addr = <0x20>;
 507                         };
 508                 };
 509
 510                 i2c_5: i2c2@17,1 {
 511                         compatible = "intel,apl-i2c";
 512                         reg = <0x0200b910 0 0 0 0>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         clocks = <&clk CLK_I2C>;
 516                         i2c-scl-rising-time-ns = <76>;
 517                         i2c-scl-falling-time-ns = <164>;
 518                         clock-frequency = <400000>;
 519                         i2c,speeds = <100000 400000 1000000>;
 520                         wacom_digitizer: wacom-digitizer@9 {
 521                                 compatible = "hid-over-i2c";
 522                                 reg = <0x9>;
 523                                 acpi,hid = "WCOM50C1";
 524                                 acpi,ddn = "WCOM Digitizer";
 525                                 interrupts-extended = <&acpi_gpe GPIO_13_IRQ
 526                                         (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
 527                                 hid-descr-addr = <0x1>;
 528                         };
 529                 };
 530
 531                 i2c_6: i2c2@17,2 {
 532                         compatible = "intel,apl-i2c";
 533                         reg = <0x0200ba10 0 0 0 0>;
 534                         clocks = <&clk CLK_I2C>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c_7: i2c2@17,3 {
 539                         compatible = "intel,apl-i2c";
 540                         reg = <0x0200bb10 0 0 0 0>;
 541                         clocks = <&clk CLK_I2C>;
 542                         status = "disabled";
 543                 };
 544
 545                 serial: serial@18,2 {
 546                         reg = <0x0200c210 0 0 0 0>;
 547                         u-boot,dm-pre-reloc;
 548                         compatible = "intel,apl-ns16550";
 549                         early-regs = <0xde000000 0x20>;
 550                         reg-shift = <2>;
 551                         clock-frequency = <1843200>;
 552                         current-speed = <115200>;
 553                         acpi,name = "URT3";
 554                         pci,no-autoconfig;
 555                 };
 556
 557                 sdmmc: sdmmc@1b,0 {
 558                         reg = <0x0000d800 0 0 0 0>;
 559                         compatible = "intel,apl-sd";
 560                         cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>;
 561                         acpi,name = "SDCD";
 562                 };
 563
 564                 pch: pch@1f,0 {
 565                         reg = <0x0000f800 0 0 0 0>;
 566                         compatible = "intel,apl-pch";
 567                         u-boot,dm-pre-reloc;
 568                         #address-cells = <1>;
 569                         #size-cells = <1>;
 570
 571                         lpc: lpc {
 572                                 compatible = "intel,apl-lpc";
 573                                 #address-cells = <1>;
 574                                 #size-cells = <0>;
 575                                 u-boot,dm-pre-reloc;
 576                                 cros_ec: cros-ec {
 577                                         u-boot,dm-pre-reloc;
 578                                         compatible = "google,cros-ec-lpc";
 579                                         reg = <0x204 1 0x200 1 0x880 0x80>;
 580
 581                                         /*
 582                                          * Describes the flash memory within
 583                                          * the EC
 584                                          */
 585                                         #address-cells = <1>;
 586                                         #size-cells = <1>;
 587                                         flash@8000000 {
 588                                                 reg = <0x08000000 0x20000>;
 589                                                 erase-value = <0xff>;
 590                                         };
 591                                 };
 592                         };
 593                 };
 594         };
 595
 596 };
 597
 598 &host_bridge {
 599         /*
 600          * PL1 override 12000 mW: the energy calculation is wrong with the
 601          * current VR solution. Experiments show that SoC TDP max (6W) can be
 602          * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
 603          */
 604         tdp-pl-override-mw = <12000 15000>;
 605
 606         early-pads = <
 607                 /* These two are for the debug UART */
 608                 GPIO_46 /* UART2 RX */
 609                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 610                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 611
 612                 GPIO_47 /* UART2 TX */
 613                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 614                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 615
 616                 GPIO_75 /* I2S1_BCLK -- PCH_WP */
 617                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
 618                         (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
 619
 620                 /* I2C2 - TPM  */
 621                 GPIO_128 /* LPSS_I2C2_SDA */
 622                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 623                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 624                 GPIO_129 /* LPSS_I2C2_SCL */
 625                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 626                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 627                 GPIO_28 /* TPM IRQ */
 628                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 629                                 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
 630                                 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
 631                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
 632
 633                 /*
 634                  * WLAN_PE_RST - default to deasserted just in case FSP
 635                  * misbehaves
 636                  */
 637                 GPIO_122  /* SIO_SPI_2_RXD */
 638                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 639                                 PAD_CFG0_RX_DISABLE | 0)
 640                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 641
 642                 /* LPC */
 643                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 644                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 645                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 646                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 647                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 648                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 649                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 650                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 651                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 652                 >;
 653
 654         fspm,package = <PACKAGE_BGA>;
 655         fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
 656         fspm,memory-down = <MEMORY_DOWN_YES>;
 657         fspm,scrambler-support = <1>;
 658         fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
 659         fspm,channel-hash-mask = <0x36>;
 660         fspm,slice-hash-mask = <0x9>;
 661         fspm,dual-rank-support-enable = <1>;
 662         fspm,low-memory-max-value = <2048>;
 663         fspm,ch0-rank-enable = <1>;
 664         fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
 665         fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 666         fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
 667                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 668         fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 669         fspm,ch1-rank-enable = <1>;
 670         fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
 671         fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 672         fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
 673                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 674         fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 675         fspm,ch2-rank-enable = <1>;
 676         fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
 677         fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 678         fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
 679                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 680         fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 681         fspm,ch3-rank-enable = <1>;
 682         fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
 683         fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 684         fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
 685                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 686         fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 687         fspm,fspm,skip-cse-rbp = <1>;
 688
 689         fspm,ch-bit-swizzling = /bits/ 8 <
 690                 /* LP4_PHYS_CH0A */
 691
 692                 /* DQA[0:7] pins of LPDDR4 module */
 693                 6 7 5 4 3 1 0 2
 694                 /* DQA[8:15] pins of LPDDR4 module */
 695                 12 10 11 13 14 8 9 15
 696                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 697                 16 22 23 20 18 17 19 21
 698                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 699                 30 28 29 25 24 26 27 31
 700
 701                 /* LP4_PHYS_CH0B */
 702                 /* DQA[0:7] pins of LPDDR4 module */
 703                 7 3 5 2 6 0 1 4
 704                 /* DQA[8:15] pins of LPDDR4 module */
 705                  9 14 12 13 10 11 8 15
 706                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 707                 20 22 23 16 19 17 18 21
 708                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 709                 28 24 26 27 29 30 31 25
 710
 711                 /* LP4_PHYS_CH1A */
 712
 713                 /* DQA[0:7] pins of LPDDR4 module */
 714                 2 1 6 7 5 4 3 0
 715                 /* DQA[8:15] pins of LPDDR4 module */
 716                 11 10 8 9 12 15 13 14
 717                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 718                 17 23 19 16 21 22 20 18
 719                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 720                 31 29 26 25 28 27 24 30
 721
 722                 /* LP4_PHYS_CH1B */
 723
 724                 /* DQA[0:7] pins of LPDDR4 module */
 725                 4 3 7 5 6 1 0 2
 726                 /* DQA[8:15] pins of LPDDR4 module */
 727                 15 9 8 11 14 13 12 10
 728                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 729                 20 23 22 21 18 19 16 17
 730                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 731                 25 28 30 31 26 27 24 29>;
 732
 733         fspm,dimm0-spd-address = <0>;
 734         fspm,dimm1-spd-address = <0>;
 735         fspm,skip-cse-rbp = <1>;
 736         fspm,enable-s3-heci2 = <0>;
 737 };
 738
 739 &fsp_s {
 740         u-boot,dm-pre-proper;
 741
 742         fsps,ish-enable = <0>;
 743         fsps,enable-sata = <0>;
 744         fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
 745         fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
 746         fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
 747         fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
 748         fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
 749         fsps,sdio-enabled = <0>;
 750
 751         /* Disable unused clkreq of PCIe root ports */
 752         fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
 753                 CLKREQ_DISABLED
 754                 CLKREQ_DISABLED
 755                 CLKREQ_DISABLED
 756                 CLKREQ_DISABLED
 757                 CLKREQ_DISABLED>;
 758
 759         /*
 760          * GPIO for PERST_0
 761          * If the Board has PERST_0 signal, assign the GPIO
 762          * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
 763          *
 764          * This are not used yet, so comment them out for now.
 765          *
 766          * prt0-gpio = <GPIO_122>;
 767          *
 768          * GPIO for SD card detect
 769          * sdcard-cd-gpio = <GPIO_177>;
 770          */
 771
 772         /*
 773          * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
 774          * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
 775          *
 776          * EMMC TX DATA Delay 1
 777          * Refer to EDS-Vol2-22.3
 778          * [14:8] steps of delay for HS400, each 125ps
 779          * [6:0] steps of delay for SDR104/HS200, each 125ps
 780
 781         /*
 782          * EMMC TX DATA Delay 2
 783          * Refer to EDS-Vol2-22.3.
 784          * [30:24] steps of delay for SDR50, each 125ps
 785          * [22:16] steps of delay for DDR50, each 125ps
 786          * [14:8] steps of delay for SDR25/HS50, each 125ps
 787          * [6:0] steps of delay for SDR12, each 125ps
 788          */
 789
 790         /*
 791          * EMMC RX CMD/DATA Delay 1
 792          * Refer to EDS-Vol2-22.3.
 793          * [30:24] steps of delay for SDR50, each 125ps
 794          * [22:16] steps of delay for DDR50, each 125ps
 795          * [14:8] steps of delay for SDR25/HS50, each 125ps
 796          * [6:0] steps of delay for SDR12, each 125ps
 797          */
 798
 799         /*
 800          * EMMC RX CMD/DATA Delay 2
 801          * Refer to EDS-Vol2-22.3.
 802          * [17:16] stands for Rx Clock before Output Buffer
 803          * [14:8] steps of delay for Auto Tuning Mode, each 125ps
 804          * [6:0] steps of delay for HS200, each 125ps
 805          */
 806         /* Enable DPTF */
 807         fsps,dptf-enabled;
 808         fsps,emmc-tx-data-cntl1 = <0x0c16>;
 809         fsps,emmc-tx-data-cntl2 = <0x28162828>;
 810         fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
 811         fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
 812
 813         /* Enable Audio Clock and Power gating */
 814         fsps,hd-audio-clk-gate = <1>;
 815         fsps,hd-audio-pwr-gate = <1>;
 816         fsps,bios-cfg-lock-down = <1>;
 817
 818         /* Enable WiFi */
 819         fsps,pcie-root-port-en = [01 00 00 00 00 00];
 820         fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
 821
 822         fsps,skip-mp-init = <1>;
 823         fsps,spi-eiss = <0>;
 824         fsps,rtc-lock = <0>;
 825
 826         fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
 827         fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
 828
 829         fsps,lpss-s0ix-enable = <1>;
 830         fsps,usb-otg = <0>;
 831         fsps,monitor-mwait-enable = <0>;
 832
 833         /*
 834          * TODO(sjg@chromium.org): Move this to the I2C nodes
 835          * Intel Common SoC Config
 836          *+-------------------+---------------------------+
 837          *| Field             |  Value                    |
 838          *+-------------------+---------------------------+
 839          *| I2C0              | Audio                     |
 840          *| I2C2              | TPM                       |
 841          *| I2C3              | Touchscreen               |
 842          *| I2C4              | Trackpad                  |
 843          *| I2C5              | Digitizer                 |
 844          *+-------------------+---------------------------+
 845          *
 846         common_soc_config" = "{
 847                 .i2c[0] = {
 848                         .speed = I2C_SPEED_FAST,
 849                         .rise-time-ns = 104,
 850                         .fall-time-ns = 52,
 851                 },
 852                 .i2c[2] = {
 853                         .early_init = 1,
 854                         .speed = I2C_SPEED_FAST,
 855                         .rise-time-ns = 57,
 856                         .fall-time-ns = 28,
 857                 },
 858                 .i2c[3] = {
 859                         .speed = I2C_SPEED_FAST,
 860                         .rise-time-ns = 76,
 861                         .fall-time-ns = 164,
 862                 },
 863                 .i2c[4] = {
 864                         .speed = I2C_SPEED_FAST,
 865                         .rise-time-ns = 114,
 866                         .fall-time-ns = 164,
 867                         .data_hold_time_ns = 350,
 868                 },
 869                 .i2c[5] = {
 870                         .speed = I2C_SPEED_FAST,
 871                         .rise-time-ns = 152,
 872                         .fall-time-ns = 30,
 873                 },
 874         }"
 875         */
 876
 877         /* Minimum SLP S3 assertion width 28ms */
 878         slp-s3-assertion-width-usecs = <28000>;
 879
 880         pads = <
 881                 /* PCIE_WAKE[0:3]_N */
 882                 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
 883                 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP)      /* Unused */
 884                 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP)      /* Unused */
 885                 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP)      /* Unused */
 886
 887                 /* EMMC interface */
 888                 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
 889                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
 890                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
 891                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
 892                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
 893                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
 894                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
 895                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
 896                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
 897                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
 898                 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
 899
 900                 /* SDIO -- unused */
 901                 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP)      /* SDIO_CLK */
 902                 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP)      /* SDIO_D0 */
 903                 /* Configure SDIO to enable power gating */
 904                 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
 905                 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP)      /* SDIO_D2 */
 906                 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP)      /* SDIO_D3 */
 907                 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP)      /* SDIO_CMD */
 908
 909                 /* SDCARD */
 910                 /* Pull down clock by 20K */
 911                 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
 912                 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
 913                 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
 914                 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
 915                 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
 916                 /* Card detect is active LOW with external pull up */
 917                 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
 918                 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
 919                 /* CLK feedback, internal signal, needs 20K pull down */
 920                 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
 921                 /* No h/w write proect for uSD cards, pull down by 20K */
 922                 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
 923                 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
 924                 PAD_CFG_GPO(GPIO_183, 0, DEEP)           /* SDIO_PWR_DOWN_N */
 925
 926                 /* SMBus -- unused */
 927                 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP)    /* SMB_ALERT _N */
 928                 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP)       /* SMB_CLK */
 929                 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP)      /* SMB_DATA */
 930
 931                 /* LPC */
 932                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 933                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 934                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 935                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 936                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 937                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 938                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 939                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 940                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 941
 942                 /* I2C0 - Audio */
 943                 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
 944                 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
 945
 946                 /* I2C1 - NFC with external pulls */
 947                 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
 948                 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
 949
 950                 /* I2C2 - TPM  */
 951                 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
 952                 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
 953
 954                 /* I2C3 - touch */
 955                 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
 956                 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
 957
 958                 /* I2C4 - trackpad */
 959                 /* LPSS_I2C4_SDA */
 960                 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
 961                 /* LPSS_I2C4_SCL */
 962                 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
 963
 964                 /* I2C5 -- pen with external pulls  */
 965                 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
 966                 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
 967
 968                 /* I2C6-7 -- unused */
 969                 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP)      /* LPSS_I2C6_SDA */
 970                 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP)      /* LPSS_I2C6_SCL */
 971                 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP)      /* LPSS_I2C7_SDA */
 972                 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP)      /* LPSS_I2C7_SCL */
 973
 974                 /* Audio Amp - I2S6 */
 975                 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
 976                 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
 977                 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP)      /* ISH_GPIO_2 - unused */
 978                 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
 979
 980                 /* NFC Reset */
 981                 PAD_CFG_GPO(GPIO_150, 1, DEEP)           /* ISH_GPIO_4 */
 982
 983                 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP)      /* ISH_GPIO_5 - unused */
 984
 985                 /* Touch enable */
 986                 PAD_CFG_GPO(GPIO_152, 1, DEEP)           /* ISH_GPIO_6 */
 987
 988                 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP)      /* ISH_GPIO_7 - unused */
 989                 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP)      /* ISH_GPIO_8 - unused */
 990                 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP)      /* ISH_GPIO_9 - unused */
 991
 992                 /* PCIE_CLKREQ[0:3]_N */
 993                 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1)    /* WLAN with external pull */
 994                 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP)      /* unused */
 995                 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP)      /* unused */
 996                 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP)      /* unused */
 997
 998                 /* OSC_CLK_OUT_[0:4] -- unused */
 999                 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
1000                 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
1001                 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
1002                 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
1003                 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
1004
1005                 /* PMU Signals */
1006                 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
1007                 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
1008                 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
1009                 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
1010                 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
1011                 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
1012                 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
1013                 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
1014                 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
1015                 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP)         /* EN_PP3300_EMMC */
1016                 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
1017                 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
1018
1019                 /* DDI[0:1] SDA and SCL -- unused */
1020                 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP)      /* HV_DDI0_DDC_SDA */
1021                 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP)      /* HV_DDI0_DDC_SCL */
1022                 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP)      /* HV_DDI1_DDC_SDA */
1023                 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP)      /* HV_DDI1_DDC_SCL */
1024
1025                 /* MIPI I2C -- unused */
1026                 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP)      /* MIPI_I2C_SDA */
1027                 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP)      /* MIPI_I2C_SCL */
1028
1029                 /* Panel 0 control */
1030                 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
1031                 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
1032                 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
1033
1034                 /* Panel 1 control -- unused */
1035                 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
1036                 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
1037                 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
1038
1039                 /* Hot plug detect */
1040                 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
1041                 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
1042
1043                 /* MDSI signals -- unused */
1044                 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP)      /* MDSI_A_TE */
1045                 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP)      /* MDSI_A_TE */
1046
1047                 /* USB overcurrent pins */
1048                 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
1049                 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
1050
1051                 /* PMC SPI -- almost entirely unused */
1052                 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
1053                 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
1054                 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
1055                 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
1056                 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
1057                 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
1058
1059                 /* PMIC Signals Unused signals related to an old PMIC interface */
1060                 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
1061                 PAD_CFG_GPI(GPIO_213, NONE, DEEP)        /* unused external pull */
1062                 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP)      /* unused */
1063                 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP)      /* unused */
1064                 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
1065                 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP)    /* unused */
1066                 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
1067                 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
1068                 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
1069
1070                 /* I2S1 -- largely unused */
1071                 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP)      /* I2S1_MCLK */
1072                 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP)      /* I2S1_BCLK -- PCH_WP */
1073                 PAD_CFG_GPO(GPIO_76, 0, DEEP)           /* I2S1_WS_SYNC -- SPK_PA_EN */
1074                 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP)      /* I2S1_SDI */
1075                 PAD_CFG_GPO(GPIO_78, 1, DEEP)           /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
1076
1077                 /* DMIC or I2S4 */
1078                 /* AVS_DMIC_CLK_A1 */
1079                 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
1080                 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
1081                 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1)  /* AVS_DMIC_DATA_1 */
1082                 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP)       /* unused -- strap */
1083                 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
1084
1085                 /* I2S2 -- Headset amp */
1086                 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1)   /* AVS_I2S2_MCLK */
1087                 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1)   /* AVS_I2S2_BCLK */
1088                 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1)   /* AVS_I2S2_SW_SYNC */
1089                 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDI */
1090                 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDO */
1091
1092                 /* I2S3 -- largely unused */
1093                 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP)       /* unused */
1094                 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP)       /* GPS_HOST_WAKE */
1095                 PAD_CFG_GPO(GPIO_91, 1, DEEP)            /* GPS_EN */
1096                 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP)       /* unused -- strap */
1097
1098                 /* Fast SPI */
1099                 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
1100                 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP)                              /* FST_SPI_CS1_B -- unused */
1101                 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
1102                 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_MISO_IO1 */
1103                 PAD_CFG_GPI(GPIO_101, NONE, DEEP)                               /* FST_IO2 -- MEM_CONFIG0 */
1104                 PAD_CFG_GPI(GPIO_102, NONE, DEEP)                               /* FST_IO3 -- MEM_CONFIG1 */
1105                 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_CLK */
1106                 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
1107                 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE)        /* FST_SPI_CS2_N */
1108
1109                 /* SIO_SPI_0 - Used for FP */
1110                 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_CLK */
1111                 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_FS0 */
1112                 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_RXD */
1113                 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_TXD */
1114
1115                 /* SIO_SPI_1 -- largely unused */
1116                 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP)      /* SIO_SPI_1_CLK */
1117                 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP)      /* SIO_SPI_1_FS0 */
1118                 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP)      /* SIO_SPI_1_FS1 */
1119                 /* Headset interrupt */
1120                 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
1121                 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP)      /* SIO_SPI_1_TXD */
1122
1123                 /* SIO_SPI_2 -- unused */
1124                 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP)      /* SIO_SPI_2_CLK */
1125                 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP)      /* SIO_SPI_2_FS0 */
1126                 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP)      /* SIO_SPI_2_FS1 */
1127                 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP)      /* SIO_SPI_2_FS2 */
1128                 /* WLAN_PE_RST - default to deasserted */
1129                 PAD_CFG_GPO(GPIO_122, 0, DEEP)           /* SIO_SPI_2_RXD */
1130                 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP)      /* SIO_SPI_2_TXD */
1131
1132                 /* Debug tracing */
1133                 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
1134                 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
1135                 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
1136                 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL)        /* FP_INT */
1137                 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
1138                 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
1139                 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
1140                 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
1141                 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
1142
1143                 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
1144                 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP)       /* Board phase enforcement */
1145                 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI  */
1146                 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP)       /* unused */
1147                 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
1148                 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
1149                 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE)    /* TRACKPAD_INT_1V8_ODL */
1150                 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP)       /* unused */
1151                 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP)       /* 1 vs 4 DMIC config */
1152                 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
1153                 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP)       /* unused */
1154                 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
1155                 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
1156                 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
1157                 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP)       /* unused */
1158                 PAD_CFG_GPI(GPIO_24, NONE, DEEP)         /* PEN_PDCT_ODL */
1159                 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP)       /* unused */
1160                 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP)       /* unused */
1161                 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP)       /* unused */
1162                 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
1163                 PAD_CFG_GPO(GPIO_29, 1, DEEP)            /* FP reset */
1164                 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
1165                 PAD_CFG_GPO(GPIO_31, 0, DEEP)            /* NFC FW DL */
1166                 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5)     /* SUS_CLK2 */
1167                 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
1168                 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP)       /* unused */
1169                 PAD_CFG_GPO(GPIO_35, 0, DEEP)            /* PEN_RESET - active high */
1170                 PAD_CFG_GPO(GPIO_36, 0, DEEP)            /* touch reset */
1171                 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP)       /* unused */
1172
1173                 /* LPSS_UART[0:2] */
1174                 PAD_CFG_GPI(GPIO_38, NONE, DEEP)         /* LPSS_UART0_RXD - MEM_CONFIG2*/
1175                 /* Next 2 are straps */
1176                 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP)       /* LPSS_UART0_TXD - unused */
1177                 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP)       /* LPSS_UART0_RTS - unused */
1178                 PAD_CFG_GPI(GPIO_41, NONE, DEEP)         /* LPSS_UART0_CTS - EC_IN_RW */
1179                 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1)   /* LPSS_UART1_RXD */
1180                 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1)   /* LPSS_UART1_TXD */
1181                 PAD_CFG_GPO(GPIO_44, 1, DEEP)    /* GPS_RST_ODL */
1182                 PAD_CFG_GPI(GPIO_45, NONE, DEEP)         /* LPSS_UART1_CTS - MEM_CONFIG3 */
1183                 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1)   /* LPSS_UART2_RXD */
1184                 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
1185                 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP)       /* LPSS_UART2_RTS - unused */
1186                 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
1187
1188                 /* Camera interface -- completely unused */
1189                 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP)       /* GP_CAMERASB00 */
1190                 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP)       /* GP_CAMERASB01 */
1191                 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP)       /* GP_CAMERASB02 */
1192                 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP)       /* GP_CAMERASB03 */
1193                 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP)       /* GP_CAMERASB04 */
1194                 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP)       /* GP_CAMERASB05 */
1195                 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP)       /* GP_CAMERASB06 */
1196                 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP)       /* GP_CAMERASB07 */
1197                 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP)       /* GP_CAMERASB08 */
1198                 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP)       /* GP_CAMERASB09 */
1199                 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP)       /* GP_CAMERASB10 */
1200                 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)       /* GP_CAMERASB11 */
1201         >;
1202 };