arch/x86/dts/chromebook_coral.dts

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /dts-v1/;
   3
   4 #include <dt-bindings/gpio/x86-gpio.h>
   5
   6 /include/ "skeleton.dtsi"
   7 /include/ "keyboard.dtsi"
   8 /include/ "reset.dtsi"
   9 /include/ "rtc.dtsi"
  10 /include/ "tsc_timer.dtsi"
  11
  12 #ifdef CONFIG_CHROMEOS_VBOOT
  13 #include "chromeos-x86.dtsi"
  14 #include "flashmap-x86-ro.dtsi"
  15 #include "flashmap-16mb-rw.dtsi"
  16 #endif
  17
  18 #include <dt-bindings/clock/intel-clock.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20 #include <dt-bindings/interrupt-controller/x86-irq.h>
  21 #include <asm/e820.h>
  22 #include <asm/intel_pinctrl_defs.h>
  23 #include <asm/arch-apollolake/cpu.h>
  24 #include <asm/arch-apollolake/gpe.h>
  25 #include <asm/arch-apollolake/gpio.h>
  26 #include <asm/arch-apollolake/iomap.h>
  27 #include <asm/arch-apollolake/pm.h>
  28 #include <dt-bindings/clock/intel-clock.h>
  29 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
  30 #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
  31 #include <dt-bindings/sound/nhlt.h>
  32
  33 / {
  34         model = "Google Coral";
  35         compatible = "google,coral", "intel,apollolake";
  36
  37         aliases {
  38                 cros-ec0 = &cros_ec;
  39                 fsp = &fsp_s;
  40                 spi0 = &spi;
  41                 i2c0 = &i2c_0;
  42                 i2c1 = &i2c_1;
  43                 i2c2 = &i2c_2;
  44                 i2c3 = &i2c_3;
  45                 i2c4 = &i2c_4;
  46                 i2c5 = &i2c_5;
  47                 i2c6 = &i2c_6;
  48                 i2c7 = &i2c_7;
  49                 mmc1 = &sdmmc;
  50         };
  51
  52         board: board {
  53                 compatible = "google,coral";
  54                 recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
  55                 write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
  56                 phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
  57                 smbios {
  58                         manufacturer = "Google";
  59                         product = "Coral";
  60                         version = "rev2";
  61                         serial = "123456789";
  62                         sku = "sku3";
  63                         family = "Google_Coral";
  64                 };
  65         };
  66
  67         config {
  68                silent_console = <0>;
  69         };
  70
  71         chosen {
  72                 stdout-path = &serial;
  73                 e820-entries = /bits/ 64 <
  74                         IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
  75                         MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
  76                 u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3
  77                         &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5
  78                         &sdmmc &maxim_codec &wifi &da_codec &tpm
  79                         &elan_touchscreen &raydium_touchscreen
  80                         &elan_touchpad &synaptics_touchpad &wacom_digitizer>;
  81                 u-boot,acpi-dsdt-order = <&board &lpc>;
  82         };
  83
  84         clk: clock {
  85                 compatible = "intel,apl-clk";
  86                 #clock-cells = <1>;
  87         };
  88
  89         cpus {
  90                 u-boot,dm-pre-reloc;
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 cpu_0: cpu@0 {
  95                         u-boot,dm-pre-reloc;
  96                         device_type = "cpu";
  97                         compatible = "intel,apl-cpu";
  98                         reg = <0>;
  99                         intel,apic-id = <0>;
 100                 };
 101
 102                 cpu_1: cpu@1 {
 103                         device_type = "cpu";
 104                         compatible = "intel,apl-cpu";
 105                         reg = <1>;
 106                         intel,apic-id = <2>;
 107                 };
 108
 109                 cpu_2: cpu@2 {
 110                         device_type = "cpu";
 111                         compatible = "intel,apl-cpu";
 112                         reg = <2>;
 113                         intel,apic-id = <4>;
 114                 };
 115
 116                 cpu_3: cpu@3 {
 117                         device_type = "cpu";
 118                         compatible = "intel,apl-cpu";
 119                         reg = <3>;
 120                         intel,apic-id = <6>;
 121                 };
 122
 123         };
 124
 125         acpi_gpe: general-purpose-events {
 126                 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 127                 compatible = "intel,acpi-gpe";
 128                 interrupt-controller;
 129                 #interrupt-cells = <2>;
 130         };
 131
 132         keyboard {
 133                 intel,duplicate-por;
 134         };
 135
 136         pci {
 137                 compatible = "pci-x86";
 138                 #address-cells = <3>;
 139                 #size-cells = <2>;
 140                 u-boot,dm-pre-reloc;
 141                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 142                         0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
 143                         0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 144                 u-boot,skip-auto-config-until-reloc;
 145
 146                 host_bridge: host-bridge@0,0 {
 147                         u-boot,dm-pre-reloc;
 148                         reg = <0x00000000 0 0 0 0>;
 149                         compatible = "intel,apl-hostbridge";
 150                         pciex-region-size = <0x10000000>;
 151                         fspm,training-delay = <21>;
 152                         /*
 153                          * Parameters used by the FSP-S binary blob. This is
 154                          * really unfortunate since these parameters mostly
 155                          * relate to drivers but we need them in one place. We
 156                          * could put them in the driver nodes easily, but then
 157                          * would have to scan each node to find them. So just
 158                          * dump them here for now.
 159                          */
 160                         fsp_s: fsp-s {
 161                         };
 162
 163                         nhlt {
 164                                 intel,dmic-channels = <4>;
 165                         };
 166                 };
 167
 168                 punit@0,1 {
 169                         u-boot,dm-pre-reloc;
 170                         reg = <0x00000800 0 0 0 0>;
 171                         compatible = "intel,apl-punit";
 172                 };
 173
 174                 gma@2,0 {
 175                         reg = <0x00001000 0 0 0 0>;
 176                         compatible = "fsp-fb";
 177                 };
 178
 179                 p2sb: p2sb@d,0 {
 180                         u-boot,dm-pre-reloc;
 181                         reg = <0x02006810 0 0 0 0>;
 182                         compatible = "intel,p2sb";
 183                         early-regs = <IOMAP_P2SB_BAR 0x100000>;
 184                         pci,no-autoconfig;
 185
 186                         n {
 187                                 compatible = "intel,apl-pinctrl";
 188                                 u-boot,dm-pre-reloc;
 189                                 intel,p2sb-port-id = <PID_GPIO_N>;
 190                                 acpi,path = "\\_SB.GPO0";
 191                                 gpio_n: gpio-n {
 192                                         compatible = "intel,gpio";
 193                                         u-boot,dm-pre-reloc;
 194                                         gpio-controller;
 195                                         #gpio-cells = <2>;
 196                                         linux-name = "INT3452:00";
 197                                 };
 198                         };
 199
 200                         nw {
 201                                 u-boot,dm-pre-reloc;
 202                                 compatible = "intel,apl-pinctrl";
 203                                 intel,p2sb-port-id = <PID_GPIO_NW>;
 204                                 #gpio-cells = <2>;
 205                                 acpi,path = "\\_SB.GPO1";
 206                                 gpio_nw: gpio-nw {
 207                                         compatible = "intel,gpio";
 208                                         u-boot,dm-pre-reloc;
 209                                         gpio-controller;
 210                                         #gpio-cells = <2>;
 211                                         linux-name = "INT3452:01";
 212                                 };
 213                         };
 214
 215                         w {
 216                                 u-boot,dm-pre-reloc;
 217                                 compatible = "intel,apl-pinctrl";
 218                                 intel,p2sb-port-id = <PID_GPIO_W>;
 219                                 #gpio-cells = <2>;
 220                                 acpi,path = "\\_SB.GPO2";
 221                                 gpio_w: gpio-w {
 222                                         compatible = "intel,gpio";
 223                                         u-boot,dm-pre-reloc;
 224                                         gpio-controller;
 225                                         #gpio-cells = <2>;
 226                                         linux-name = "INT3452:02";
 227                                 };
 228                         };
 229
 230                         sw {
 231                                 u-boot,dm-pre-reloc;
 232                                 compatible = "intel,apl-pinctrl";
 233                                 intel,p2sb-port-id = <PID_GPIO_SW>;
 234                                 #gpio-cells = <2>;
 235                                 acpi,path = "\\_SB.GPO3";
 236                                 gpio_sw: gpio-sw {
 237                                         compatible = "intel,gpio";
 238                                         u-boot,dm-pre-reloc;
 239                                         gpio-controller;
 240                                         #gpio-cells = <2>;
 241                                         linux-name = "INT3452:03";
 242                                 };
 243                         };
 244
 245                         itss {
 246                                 u-boot,dm-pre-reloc;
 247                                 compatible = "intel,itss";
 248                                 intel,p2sb-port-id = <PID_ITSS>;
 249                                 intel,pmc-routes = <
 250                                         PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
 251                                         PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
 252                                         PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
 253                                         PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
 254                                         PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
 255                                         PMC_GPE_N_31_0 GPIO_GPE_N_31_0
 256                                         PMC_GPE_N_63_32 GPIO_GPE_N_63_32
 257                                         PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
 258                         };
 259                 };
 260
 261                 pmc@d,1 {
 262                         u-boot,dm-pre-reloc;
 263                         reg = <0x6900 0 0 0 0>;
 264
 265                         /*
 266                          * Values for BAR0, BAR2 and ACPI_BASE for when PCI
 267                          * auto-configure is not available
 268                          */
 269                         early-regs = <0xfe042000 0x2000
 270                                 0xfe044000 0x2000
 271                                 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
 272                         compatible = "intel,apl-pmc";
 273                         gpe0-dwx-mask = <0xf>;
 274                         gpe0-dwx-shift-base = <4>;
 275
 276                         /*
 277                          * GPE configuration
 278                          * Note that GPE events called out in ASL code rely on
 279                          * this route, i.e., if this route changes then the
 280                          * affected GPE * offset bits also need to be changed.
 281                          * This sets the PMC register GPE_CFG fields.
 282                          */
 283                         gpe0-dw = <PMC_GPE_N_31_0
 284                                 PMC_GPE_N_63_32
 285                                 PMC_GPE_SW_31_0>;
 286                         gpe0-sts = <0x20>;
 287                         gpe0-en = <0x30>;
 288                 };
 289
 290                 audio@e,0 {
 291                         reg = <0x7000 0 0 0 0>;
 292                         compatible = "simple-bus";
 293                         acpi,name = "HDAS";
 294                         i2s {
 295                                 compatible = "fred";
 296                         };
 297                         maxim_codec: maxim-codec {
 298                                 compatible = "maxim,max98357a";
 299                                 acpi,ddn = "Maxim Integrated 98357A Amplifier";
 300                                 sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>;
 301                                 sdmode-delay = <5>;
 302                                 acpi,name = "MAXM";
 303                                 acpi,hid = "MX98357A";
 304                                 acpi,audio-link = <AUDIO_LINK_SSP5>;
 305                         };
 306                 };
 307
 308                 spi: fast-spi@d,2 {
 309                         u-boot,dm-pre-reloc;
 310                         reg = <0x02006a10 0 0 0 0>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         compatible = "intel,fast-spi";
 314                         early-regs = <IOMAP_SPI_BASE 0x1000>;
 315                         intel,hardware-seq = <1>;
 316
 317                         fwstore_spi: spi-flash@0 {
 318                                 #size-cells = <1>;
 319                                 #address-cells = <1>;
 320                                 u-boot,dm-pre-reloc;
 321                                 reg = <0>;
 322                                 compatible = "winbond,w25q128fw",
 323                                          "jedec,spi-nor";
 324                                 rw-mrc-cache {
 325                                         label = "rw-mrc-cache";
 326                                         reg = <0x008e0000 0x00010000>;
 327                                         u-boot,dm-pre-reloc;
 328                                 };
 329                                 rw-var-mrc-cache {
 330                                         label = "rw-mrc-cache";
 331                                         reg = <0x008f0000 0x0001000>;
 332                                         u-boot,dm-pre-reloc;
 333                                 };
 334                         };
 335                 };
 336
 337                 /* WiFi */
 338                 pcie-a0@14,0 {
 339                         reg = <0x0000a000 0 0 0 0>;
 340                         acpi,name = "RP01";
 341                         wifi: wifi {
 342                                 compatible = "intel,generic-wifi";
 343                                 acpi,ddn = "Intel WiFi";
 344                                 acpi,name = "WF00";
 345                                 acpi,wake = <GPE0_DW3_00>;
 346                                 interrupts-extended = <&acpi_gpe 0x3c 0>;
 347                         };
 348                 };
 349
 350                 i2c_0: i2c2@16,0 {
 351                         compatible = "intel,apl-i2c";
 352                         reg = <0x0200b010 0 0 0 0>;
 353                         clocks = <&clk CLK_I2C>;
 354                         i2c-scl-rising-time-ns = <104>;
 355                         i2c-scl-falling-time-ns = <52>;
 356                         clock-frequency = <400000>;
 357                         i2c,speeds = <100000 400000 1000000>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         da_codec: da-codec {
 361                                 reg = <0x1a>;
 362                                 compatible = "dlg,da7219";
 363                                 interrupts-extended = <&acpi_gpe GPIO_116_IRQ
 364                                         (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
 365                                 acpi,name = "DLG7";
 366                                 acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec";
 367                                 acpi,audio-link = <AUDIO_LINK_SSP1>;
 368                                 dlg,micbias-lvl = <2600>;
 369                                 dlg,mic-amp-in-sel = "diff";
 370                                 da7219_aad {
 371                                         dlg,btn-cfg = <50>;
 372                                         dlg,mic-det-thr = <500>;
 373                                         dlg,jack-ins-deb = <20>;
 374                                         dlg,jack-det-rate = "32ms_64ms";
 375                                         dlg,jack-rem-deb = <1>;
 376                                         dlg,a-d-btn-thr = <0xa>;
 377                                         dlg,d-b-btn-thr = <0x16>;
 378                                         dlg,b-c-btn-thr = <0x21>;
 379                                         dlg,c-mic-btn-thr = <0x3e>;
 380                                         dlg,btn-avg = <4>;
 381                                         dlg,adc-1bit-rpt = <1>;
 382                                 };
 383                         };
 384                 };
 385
 386                 i2c_1: i2c2@16,1 {
 387                         compatible = "intel,apl-i2c";
 388                         reg = <0x0200b110 0 0 0 0>;
 389                         clocks = <&clk CLK_I2C>;
 390                         clock-frequency = <400000>;
 391                         i2c,speeds = <100000 400000 1000000 3400000>;
 392                         i2c-scl-rising-time-ns = <52>;
 393                         i2c-scl-falling-time-ns = <52>;
 394                 };
 395
 396                 i2c_2: i2c2@16,2 {
 397                         compatible = "intel,apl-i2c";
 398                         reg = <0x0200b210 0 0 0 0>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         clock-frequency = <400000>;
 402                         i2c,speeds = <100000 400000 1000000>;
 403                         clocks = <&clk CLK_I2C>;
 404                         i2c-scl-rising-time-ns = <57>;
 405                         i2c-scl-falling-time-ns = <28>;
 406                         tpm: tpm@50 {
 407                                 reg = <0x50>;
 408                                 compatible = "google,cr50";
 409                                 u-boot,i2c-offset-len = <0>;
 410                                 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
 411                                 interrupts-extended = <&acpi_gpe GPIO_28_IRQ
 412                                          IRQ_TYPE_EDGE_FALLING>;
 413                                 acpi,hid = "GOOG0005";
 414                                 acpi,ddn = "I2C TPM";
 415                                 acpi,name = "TPMI";
 416                         };
 417                 };
 418
 419                 i2c_3: i2c2@16,3 {
 420                         compatible = "intel,apl-i2c";
 421                         reg = <0x0200b310 0 0 0 0>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         clocks = <&clk CLK_I2C>;
 425                         i2c-scl-rising-time-ns = <76>;
 426                         i2c-scl-falling-time-ns = <164>;
 427                         clock-frequency = <400000>;
 428                         i2c,speeds = <100000 400000>;
 429                         elan_touchscreen: elan-touchscreen@10 {
 430                                 compatible = "i2c-chip";
 431                                 reg = <0x10>;
 432                                 acpi,hid = "ELAN0001";
 433                                 acpi,ddn = "ELAN Touchscreen";
 434                                 interrupts-extended = <&acpi_gpe GPIO_21_IRQ
 435                                         IRQ_TYPE_EDGE_FALLING>;
 436                                 linux,probed;
 437                                 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
 438                                 reset-delay-ms = <20>;
 439                                 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
 440                                 enable-delay-ms = <1>;
 441                                 acpi,has-power-resource;
 442                         };
 443
 444                         raydium_touchscreen: raydium-touchscreen@39 {
 445                                 compatible = "i2c-chip";
 446                                 reg = <0x39>;
 447                                 acpi,hid = "RAYD0001";
 448                                 acpi,ddn = "Raydium Touchscreen";
 449                                 interrupts-extended = <&acpi_gpe GPIO_21_IRQ
 450                                         IRQ_TYPE_EDGE_FALLING>;
 451                                 linux,probed;
 452                                 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
 453                                 reset-delay-ms = <1>;
 454                                 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
 455                                 enable-delay-ms = <50>;
 456                                 acpi,has-power-resource;
 457                         };
 458                 };
 459
 460                 i2c_4: i2c2@17,0 {
 461                         compatible = "intel,apl-i2c";
 462                         reg = <0x0200b810 0 0 0 0>;
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         clocks = <&clk CLK_I2C>;
 466                         i2c-sda-hold-time-ns = <350>;
 467                         i2c-scl-rising-time-ns = <114>;
 468                         i2c-scl-falling-time-ns = <164>;
 469                         clock-frequency = <400000>;
 470                         i2c,speeds = <100000 400000>;
 471                         elan_touchpad: elan-touchpad@15 {
 472                                 compatible = "i2c-chip";
 473                                 reg = <0x15>;
 474                                 u-boot,i2c-offset-len = <0>;
 475                                 acpi,hid = "ELAN0000";
 476                                 acpi,ddn = "ELAN Touchpad";
 477                                 interrupts-extended = <&acpi_gpe GPIO_18_IRQ
 478                                          IRQ_TYPE_EDGE_FALLING>;
 479                                 acpi,wake = <GPE0_DW1_15>;
 480                                 linux,probed;
 481                         };
 482                         synaptics_touchpad: synaptics-touchpad@2c {
 483                                 compatible = "hid-over-i2c";
 484                                 reg = <0x2c>;
 485                                 acpi,hid = "PNP0C50";
 486                                 acpi,ddn = "Synaptics Touchpad";
 487                                 interrupts-extended = <&acpi_gpe GPIO_18_IRQ
 488                                          IRQ_TYPE_EDGE_FALLING>;
 489                                 acpi,wake = <GPE0_DW1_15>;
 490                                 linux,probed;
 491                                 hid-descr-addr = <0x20>;
 492                         };
 493                 };
 494
 495                 i2c_5: i2c2@17,1 {
 496                         compatible = "intel,apl-i2c";
 497                         reg = <0x0200b910 0 0 0 0>;
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         clocks = <&clk CLK_I2C>;
 501                         i2c-scl-rising-time-ns = <76>;
 502                         i2c-scl-falling-time-ns = <164>;
 503                         clock-frequency = <400000>;
 504                         i2c,speeds = <100000 400000 1000000>;
 505                         wacom_digitizer: wacom-digitizer@9 {
 506                                 compatible = "hid-over-i2c";
 507                                 reg = <0x9>;
 508                                 acpi,hid = "WCOM50C1";
 509                                 acpi,ddn = "WCOM Digitizer";
 510                                 interrupts-extended = <&acpi_gpe GPIO_13_IRQ
 511                                         (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
 512                                 hid-descr-addr = <0x1>;
 513                         };
 514                 };
 515
 516                 i2c_6: i2c2@17,2 {
 517                         compatible = "intel,apl-i2c";
 518                         reg = <0x0200ba10 0 0 0 0>;
 519                         clocks = <&clk CLK_I2C>;
 520                         status = "disabled";
 521                 };
 522
 523                 i2c_7: i2c2@17,3 {
 524                         compatible = "intel,apl-i2c";
 525                         reg = <0x0200bb10 0 0 0 0>;
 526                         clocks = <&clk CLK_I2C>;
 527                         status = "disabled";
 528                 };
 529
 530                 serial: serial@18,2 {
 531                         reg = <0x0200c210 0 0 0 0>;
 532                         u-boot,dm-pre-reloc;
 533                         compatible = "intel,apl-ns16550";
 534                         early-regs = <0xde000000 0x20>;
 535                         reg-shift = <2>;
 536                         clock-frequency = <1843200>;
 537                         current-speed = <115200>;
 538                         acpi,name = "URT3";
 539                         pci,no-autoconfig;
 540                 };
 541
 542                 sdmmc: sdmmc@1b,0 {
 543                         reg = <0x0000d800 0 0 0 0>;
 544                         compatible = "intel,apl-sd";
 545                         cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>;
 546                         acpi,name = "SDCD";
 547                 };
 548
 549                 pch: pch@1f,0 {
 550                         reg = <0x0000f800 0 0 0 0>;
 551                         compatible = "intel,apl-pch";
 552                         u-boot,dm-pre-reloc;
 553                         #address-cells = <1>;
 554                         #size-cells = <1>;
 555
 556                         lpc: lpc {
 557                                 compatible = "intel,apl-lpc";
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 u-boot,dm-pre-reloc;
 561                                 cros_ec: cros-ec {
 562                                         u-boot,dm-pre-reloc;
 563                                         compatible = "google,cros-ec-lpc";
 564                                         reg = <0x204 1 0x200 1 0x880 0x80>;
 565
 566                                         /*
 567                                          * Describes the flash memory within
 568                                          * the EC
 569                                          */
 570                                         #address-cells = <1>;
 571                                         #size-cells = <1>;
 572                                         flash@8000000 {
 573                                                 reg = <0x08000000 0x20000>;
 574                                                 erase-value = <0xff>;
 575                                         };
 576                                 };
 577                         };
 578                 };
 579         };
 580
 581 };
 582
 583 &host_bridge {
 584         /*
 585          * PL1 override 12000 mW: the energy calculation is wrong with the
 586          * current VR solution. Experiments show that SoC TDP max (6W) can be
 587          * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
 588          */
 589         tdp-pl-override-mw = <12000 15000>;
 590
 591         early-pads = <
 592                 /* These two are for the debug UART */
 593                 GPIO_46 /* UART2 RX */
 594                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 595                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 596
 597                 GPIO_47 /* UART2 TX */
 598                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 599                         (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 600
 601                 GPIO_75 /* I2S1_BCLK -- PCH_WP */
 602                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
 603                         (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
 604
 605                 /* I2C2 - TPM  */
 606                 GPIO_128 /* LPSS_I2C2_SDA */
 607                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 608                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 609                 GPIO_129 /* LPSS_I2C2_SCL */
 610                         (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
 611                         (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 612                 GPIO_28 /* TPM IRQ */
 613                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 614                                 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
 615                                 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
 616                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
 617
 618                 /*
 619                  * WLAN_PE_RST - default to deasserted just in case FSP
 620                  * misbehaves
 621                  */
 622                 GPIO_122  /* SIO_SPI_2_RXD */
 623                         (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
 624                                 PAD_CFG0_RX_DISABLE | 0)
 625                         (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
 626
 627                 /* LPC */
 628                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 629                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 630                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 631                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 632                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 633                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 634                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 635                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 636                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 637                 >;
 638
 639         fspm,package = <PACKAGE_BGA>;
 640         fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
 641         fspm,memory-down = <MEMORY_DOWN_YES>;
 642         fspm,scrambler-support = <1>;
 643         fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
 644         fspm,channel-hash-mask = <0x36>;
 645         fspm,slice-hash-mask = <0x9>;
 646         fspm,dual-rank-support-enable = <1>;
 647         fspm,low-memory-max-value = <2048>;
 648         fspm,ch0-rank-enable = <1>;
 649         fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
 650         fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 651         fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
 652                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 653         fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 654         fspm,ch1-rank-enable = <1>;
 655         fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
 656         fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 657         fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
 658                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 659         fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 660         fspm,ch2-rank-enable = <1>;
 661         fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
 662         fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 663         fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
 664                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 665         fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 666         fspm,ch3-rank-enable = <1>;
 667         fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
 668         fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
 669         fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
 670                            CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
 671         fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
 672         fspm,fspm,skip-cse-rbp = <1>;
 673
 674         fspm,ch-bit-swizzling = /bits/ 8 <
 675                 /* LP4_PHYS_CH0A */
 676
 677                 /* DQA[0:7] pins of LPDDR4 module */
 678                 6 7 5 4 3 1 0 2
 679                 /* DQA[8:15] pins of LPDDR4 module */
 680                 12 10 11 13 14 8 9 15
 681                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 682                 16 22 23 20 18 17 19 21
 683                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 684                 30 28 29 25 24 26 27 31
 685
 686                 /* LP4_PHYS_CH0B */
 687                 /* DQA[0:7] pins of LPDDR4 module */
 688                 7 3 5 2 6 0 1 4
 689                 /* DQA[8:15] pins of LPDDR4 module */
 690                  9 14 12 13 10 11 8 15
 691                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 692                 20 22 23 16 19 17 18 21
 693                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 694                 28 24 26 27 29 30 31 25
 695
 696                 /* LP4_PHYS_CH1A */
 697
 698                 /* DQA[0:7] pins of LPDDR4 module */
 699                 2 1 6 7 5 4 3 0
 700                 /* DQA[8:15] pins of LPDDR4 module */
 701                 11 10 8 9 12 15 13 14
 702                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 703                 17 23 19 16 21 22 20 18
 704                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 705                 31 29 26 25 28 27 24 30
 706
 707                 /* LP4_PHYS_CH1B */
 708
 709                 /* DQA[0:7] pins of LPDDR4 module */
 710                 4 3 7 5 6 1 0 2
 711                 /* DQA[8:15] pins of LPDDR4 module */
 712                 15 9 8 11 14 13 12 10
 713                 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
 714                 20 23 22 21 18 19 16 17
 715                 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
 716                 25 28 30 31 26 27 24 29>;
 717
 718         fspm,dimm0-spd-address = <0>;
 719         fspm,dimm1-spd-address = <0>;
 720         fspm,skip-cse-rbp = <1>;
 721         fspm,enable-s3-heci2 = <0>;
 722 };
 723
 724 &fsp_s {
 725         u-boot,dm-pre-proper;
 726
 727         fsps,ish-enable = <0>;
 728         fsps,enable-sata = <0>;
 729         fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
 730         fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
 731         fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
 732         fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
 733         fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
 734         fsps,sdio-enabled = <0>;
 735
 736         /* Disable unused clkreq of PCIe root ports */
 737         fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
 738                 CLKREQ_DISABLED
 739                 CLKREQ_DISABLED
 740                 CLKREQ_DISABLED
 741                 CLKREQ_DISABLED
 742                 CLKREQ_DISABLED>;
 743
 744         /*
 745          * GPIO for PERST_0
 746          * If the Board has PERST_0 signal, assign the GPIO
 747          * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
 748          *
 749          * This are not used yet, so comment them out for now.
 750          *
 751          * prt0-gpio = <GPIO_122>;
 752          *
 753          * GPIO for SD card detect
 754          * sdcard-cd-gpio = <GPIO_177>;
 755          */
 756
 757         /*
 758          * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
 759          * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
 760          *
 761          * EMMC TX DATA Delay 1
 762          * Refer to EDS-Vol2-22.3
 763          * [14:8] steps of delay for HS400, each 125ps
 764          * [6:0] steps of delay for SDR104/HS200, each 125ps
 765
 766         /*
 767          * EMMC TX DATA Delay 2
 768          * Refer to EDS-Vol2-22.3.
 769          * [30:24] steps of delay for SDR50, each 125ps
 770          * [22:16] steps of delay for DDR50, each 125ps
 771          * [14:8] steps of delay for SDR25/HS50, each 125ps
 772          * [6:0] steps of delay for SDR12, each 125ps
 773          */
 774
 775         /*
 776          * EMMC RX CMD/DATA Delay 1
 777          * Refer to EDS-Vol2-22.3.
 778          * [30:24] steps of delay for SDR50, each 125ps
 779          * [22:16] steps of delay for DDR50, each 125ps
 780          * [14:8] steps of delay for SDR25/HS50, each 125ps
 781          * [6:0] steps of delay for SDR12, each 125ps
 782          */
 783
 784         /*
 785          * EMMC RX CMD/DATA Delay 2
 786          * Refer to EDS-Vol2-22.3.
 787          * [17:16] stands for Rx Clock before Output Buffer
 788          * [14:8] steps of delay for Auto Tuning Mode, each 125ps
 789          * [6:0] steps of delay for HS200, each 125ps
 790          */
 791         /* Enable DPTF */
 792         fsps,dptf-enabled;
 793         fsps,emmc-tx-data-cntl1 = <0x0c16>;
 794         fsps,emmc-tx-data-cntl2 = <0x28162828>;
 795         fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
 796         fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
 797
 798         /* Enable Audio Clock and Power gating */
 799         fsps,hd-audio-clk-gate = <1>;
 800         fsps,hd-audio-pwr-gate = <1>;
 801         fsps,bios-cfg-lock-down = <1>;
 802
 803         /* Enable WiFi */
 804         fsps,pcie-root-port-en = [01 00 00 00 00 00];
 805         fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
 806
 807         fsps,skip-mp-init = <1>;
 808         fsps,spi-eiss = <0>;
 809         fsps,rtc-lock = <0>;
 810
 811         fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
 812         fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
 813
 814         fsps,lpss-s0ix-enable = <1>;
 815         fsps,usb-otg = <0>;
 816         fsps,monitor-mwait-enable = <0>;
 817
 818         /*
 819          * TODO(sjg@chromium.org): Move this to the I2C nodes
 820          * Intel Common SoC Config
 821          *+-------------------+---------------------------+
 822          *| Field             |  Value                    |
 823          *+-------------------+---------------------------+
 824          *| I2C0              | Audio                     |
 825          *| I2C2              | TPM                       |
 826          *| I2C3              | Touchscreen               |
 827          *| I2C4              | Trackpad                  |
 828          *| I2C5              | Digitizer                 |
 829          *+-------------------+---------------------------+
 830          *
 831         common_soc_config" = "{
 832                 .i2c[0] = {
 833                         .speed = I2C_SPEED_FAST,
 834                         .rise-time-ns = 104,
 835                         .fall-time-ns = 52,
 836                 },
 837                 .i2c[2] = {
 838                         .early_init = 1,
 839                         .speed = I2C_SPEED_FAST,
 840                         .rise-time-ns = 57,
 841                         .fall-time-ns = 28,
 842                 },
 843                 .i2c[3] = {
 844                         .speed = I2C_SPEED_FAST,
 845                         .rise-time-ns = 76,
 846                         .fall-time-ns = 164,
 847                 },
 848                 .i2c[4] = {
 849                         .speed = I2C_SPEED_FAST,
 850                         .rise-time-ns = 114,
 851                         .fall-time-ns = 164,
 852                         .data_hold_time_ns = 350,
 853                 },
 854                 .i2c[5] = {
 855                         .speed = I2C_SPEED_FAST,
 856                         .rise-time-ns = 152,
 857                         .fall-time-ns = 30,
 858                 },
 859         }"
 860         */
 861
 862         /* Minimum SLP S3 assertion width 28ms */
 863         slp-s3-assertion-width-usecs = <28000>;
 864
 865         pads = <
 866                 /* PCIE_WAKE[0:3]_N */
 867                 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
 868                 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP)      /* Unused */
 869                 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP)      /* Unused */
 870                 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP)      /* Unused */
 871
 872                 /* EMMC interface */
 873                 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
 874                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
 875                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
 876                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
 877                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
 878                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
 879                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
 880                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
 881                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
 882                 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
 883                 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
 884
 885                 /* SDIO -- unused */
 886                 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP)      /* SDIO_CLK */
 887                 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP)      /* SDIO_D0 */
 888                 /* Configure SDIO to enable power gating */
 889                 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
 890                 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP)      /* SDIO_D2 */
 891                 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP)      /* SDIO_D3 */
 892                 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP)      /* SDIO_CMD */
 893
 894                 /* SDCARD */
 895                 /* Pull down clock by 20K */
 896                 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
 897                 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
 898                 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
 899                 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
 900                 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
 901                 /* Card detect is active LOW with external pull up */
 902                 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
 903                 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
 904                 /* CLK feedback, internal signal, needs 20K pull down */
 905                 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
 906                 /* No h/w write proect for uSD cards, pull down by 20K */
 907                 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
 908                 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
 909                 PAD_CFG_GPO(GPIO_183, 0, DEEP)           /* SDIO_PWR_DOWN_N */
 910
 911                 /* SMBus -- unused */
 912                 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP)    /* SMB_ALERT _N */
 913                 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP)       /* SMB_CLK */
 914                 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP)      /* SMB_DATA */
 915
 916                 /* LPC */
 917                 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
 918                 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
 919                 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
 920                 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1)   /* LPC_AD0 */
 921                 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1)   /* LPC_AD1 */
 922                 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1)   /* LPC_AD2 */
 923                 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
 924                 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
 925                 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
 926
 927                 /* I2C0 - Audio */
 928                 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
 929                 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
 930
 931                 /* I2C1 - NFC with external pulls */
 932                 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
 933                 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
 934
 935                 /* I2C2 - TPM  */
 936                 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
 937                 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
 938
 939                 /* I2C3 - touch */
 940                 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
 941                 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
 942
 943                 /* I2C4 - trackpad */
 944                 /* LPSS_I2C4_SDA */
 945                 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
 946                 /* LPSS_I2C4_SCL */
 947                 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
 948
 949                 /* I2C5 -- pen with external pulls  */
 950                 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
 951                 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
 952
 953                 /* I2C6-7 -- unused */
 954                 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP)      /* LPSS_I2C6_SDA */
 955                 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP)      /* LPSS_I2C6_SCL */
 956                 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP)      /* LPSS_I2C7_SDA */
 957                 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP)      /* LPSS_I2C7_SCL */
 958
 959                 /* Audio Amp - I2S6 */
 960                 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
 961                 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
 962                 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP)      /* ISH_GPIO_2 - unused */
 963                 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
 964
 965                 /* NFC Reset */
 966                 PAD_CFG_GPO(GPIO_150, 1, DEEP)           /* ISH_GPIO_4 */
 967
 968                 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP)      /* ISH_GPIO_5 - unused */
 969
 970                 /* Touch enable */
 971                 PAD_CFG_GPO(GPIO_152, 1, DEEP)           /* ISH_GPIO_6 */
 972
 973                 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP)      /* ISH_GPIO_7 - unused */
 974                 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP)      /* ISH_GPIO_8 - unused */
 975                 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP)      /* ISH_GPIO_9 - unused */
 976
 977                 /* PCIE_CLKREQ[0:3]_N */
 978                 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1)    /* WLAN with external pull */
 979                 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP)      /* unused */
 980                 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP)      /* unused */
 981                 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP)      /* unused */
 982
 983                 /* OSC_CLK_OUT_[0:4] -- unused */
 984                 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
 985                 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
 986                 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
 987                 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
 988                 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
 989
 990                 /* PMU Signals */
 991                 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
 992                 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
 993                 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
 994                 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
 995                 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
 996                 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
 997                 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
 998                 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
 999                 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
1000                 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP)         /* EN_PP3300_EMMC */
1001                 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
1002                 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
1003
1004                 /* DDI[0:1] SDA and SCL -- unused */
1005                 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP)      /* HV_DDI0_DDC_SDA */
1006                 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP)      /* HV_DDI0_DDC_SCL */
1007                 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP)      /* HV_DDI1_DDC_SDA */
1008                 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP)      /* HV_DDI1_DDC_SCL */
1009
1010                 /* MIPI I2C -- unused */
1011                 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP)      /* MIPI_I2C_SDA */
1012                 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP)      /* MIPI_I2C_SCL */
1013
1014                 /* Panel 0 control */
1015                 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
1016                 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
1017                 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
1018
1019                 /* Panel 1 control -- unused */
1020                 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
1021                 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
1022                 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
1023
1024                 /* Hot plug detect */
1025                 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
1026                 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
1027
1028                 /* MDSI signals -- unused */
1029                 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP)      /* MDSI_A_TE */
1030                 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP)      /* MDSI_A_TE */
1031
1032                 /* USB overcurrent pins */
1033                 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
1034                 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
1035
1036                 /* PMC SPI -- almost entirely unused */
1037                 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
1038                 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
1039                 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
1040                 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
1041                 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
1042                 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
1043
1044                 /* PMIC Signals Unused signals related to an old PMIC interface */
1045                 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
1046                 PAD_CFG_GPI(GPIO_213, NONE, DEEP)        /* unused external pull */
1047                 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP)      /* unused */
1048                 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP)      /* unused */
1049                 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
1050                 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP)    /* unused */
1051                 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
1052                 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
1053                 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
1054
1055                 /* I2S1 -- largely unused */
1056                 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP)      /* I2S1_MCLK */
1057                 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP)      /* I2S1_BCLK -- PCH_WP */
1058                 PAD_CFG_GPO(GPIO_76, 0, DEEP)           /* I2S1_WS_SYNC -- SPK_PA_EN */
1059                 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP)      /* I2S1_SDI */
1060                 PAD_CFG_GPO(GPIO_78, 1, DEEP)           /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
1061
1062                 /* DMIC or I2S4 */
1063                 /* AVS_DMIC_CLK_A1 */
1064                 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
1065                 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
1066                 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1)  /* AVS_DMIC_DATA_1 */
1067                 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP)       /* unused -- strap */
1068                 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
1069
1070                 /* I2S2 -- Headset amp */
1071                 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1)   /* AVS_I2S2_MCLK */
1072                 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1)   /* AVS_I2S2_BCLK */
1073                 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1)   /* AVS_I2S2_SW_SYNC */
1074                 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDI */
1075                 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1)   /* AVS_I2S2_SDO */
1076
1077                 /* I2S3 -- largely unused */
1078                 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP)       /* unused */
1079                 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP)       /* GPS_HOST_WAKE */
1080                 PAD_CFG_GPO(GPIO_91, 1, DEEP)            /* GPS_EN */
1081                 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP)       /* unused -- strap */
1082
1083                 /* Fast SPI */
1084                 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
1085                 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP)                              /* FST_SPI_CS1_B -- unused */
1086                 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
1087                 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_MISO_IO1 */
1088                 PAD_CFG_GPI(GPIO_101, NONE, DEEP)                               /* FST_IO2 -- MEM_CONFIG0 */
1089                 PAD_CFG_GPI(GPIO_102, NONE, DEEP)                               /* FST_IO3 -- MEM_CONFIG1 */
1090                 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE)        /* FST_SPI_CLK */
1091                 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
1092                 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE)        /* FST_SPI_CS2_N */
1093
1094                 /* SIO_SPI_0 - Used for FP */
1095                 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_CLK */
1096                 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_FS0 */
1097                 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_RXD */
1098                 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1)                 /* SIO_SPI_0_TXD */
1099
1100                 /* SIO_SPI_1 -- largely unused */
1101                 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP)      /* SIO_SPI_1_CLK */
1102                 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP)      /* SIO_SPI_1_FS0 */
1103                 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP)      /* SIO_SPI_1_FS1 */
1104                 /* Headset interrupt */
1105                 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
1106                 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP)      /* SIO_SPI_1_TXD */
1107
1108                 /* SIO_SPI_2 -- unused */
1109                 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP)      /* SIO_SPI_2_CLK */
1110                 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP)      /* SIO_SPI_2_FS0 */
1111                 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP)      /* SIO_SPI_2_FS1 */
1112                 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP)      /* SIO_SPI_2_FS2 */
1113                 /* WLAN_PE_RST - default to deasserted */
1114                 PAD_CFG_GPO(GPIO_122, 0, DEEP)           /* SIO_SPI_2_RXD */
1115                 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP)      /* SIO_SPI_2_TXD */
1116
1117                 /* Debug tracing */
1118                 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
1119                 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
1120                 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
1121                 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL)        /* FP_INT */
1122                 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
1123                 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
1124                 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
1125                 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
1126                 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
1127
1128                 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
1129                 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP)       /* Board phase enforcement */
1130                 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI  */
1131                 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP)       /* unused */
1132                 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
1133                 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
1134                 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE)    /* TRACKPAD_INT_1V8_ODL */
1135                 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP)       /* unused */
1136                 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP)       /* 1 vs 4 DMIC config */
1137                 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
1138                 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP)       /* unused */
1139                 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
1140                 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
1141                 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
1142                 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP)       /* unused */
1143                 PAD_CFG_GPI(GPIO_24, NONE, DEEP)         /* PEN_PDCT_ODL */
1144                 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP)       /* unused */
1145                 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP)       /* unused */
1146                 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP)       /* unused */
1147                 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
1148                 PAD_CFG_GPO(GPIO_29, 1, DEEP)            /* FP reset */
1149                 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
1150                 PAD_CFG_GPO(GPIO_31, 0, DEEP)            /* NFC FW DL */
1151                 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5)     /* SUS_CLK2 */
1152                 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
1153                 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP)       /* unused */
1154                 PAD_CFG_GPO(GPIO_35, 0, DEEP)            /* PEN_RESET - active high */
1155                 PAD_CFG_GPO(GPIO_36, 0, DEEP)            /* touch reset */
1156                 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP)       /* unused */
1157
1158                 /* LPSS_UART[0:2] */
1159                 PAD_CFG_GPI(GPIO_38, NONE, DEEP)         /* LPSS_UART0_RXD - MEM_CONFIG2*/
1160                 /* Next 2 are straps */
1161                 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP)       /* LPSS_UART0_TXD - unused */
1162                 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP)       /* LPSS_UART0_RTS - unused */
1163                 PAD_CFG_GPI(GPIO_41, NONE, DEEP)         /* LPSS_UART0_CTS - EC_IN_RW */
1164                 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1)   /* LPSS_UART1_RXD */
1165                 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1)   /* LPSS_UART1_TXD */
1166                 PAD_CFG_GPO(GPIO_44, 1, DEEP)    /* GPS_RST_ODL */
1167                 PAD_CFG_GPI(GPIO_45, NONE, DEEP)         /* LPSS_UART1_CTS - MEM_CONFIG3 */
1168                 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1)   /* LPSS_UART2_RXD */
1169                 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
1170                 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP)       /* LPSS_UART2_RTS - unused */
1171                 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
1172
1173                 /* Camera interface -- completely unused */
1174                 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP)       /* GP_CAMERASB00 */
1175                 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP)       /* GP_CAMERASB01 */
1176                 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP)       /* GP_CAMERASB02 */
1177                 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP)       /* GP_CAMERASB03 */
1178                 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP)       /* GP_CAMERASB04 */
1179                 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP)       /* GP_CAMERASB05 */
1180                 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP)       /* GP_CAMERASB06 */
1181                 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP)       /* GP_CAMERASB07 */
1182                 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP)       /* GP_CAMERASB08 */
1183                 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP)       /* GP_CAMERASB09 */
1184                 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP)       /* GP_CAMERASB10 */
1185                 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)       /* GP_CAMERASB11 */
1186         >;
1187 };