1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
13 /include/ "skeleton.dtsi"
14 /include/ "serial.dtsi"
15 /include/ "reset.dtsi"
18 #include "tsc_timer.dtsi"
19 #include "smbios.dtsi"
22 model = "Advantech SOM-DB5800-SOM-6867";
23 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
35 compatible = "intel,x86-pinctrl";
78 stdout-path = "/serial";
87 compatible = "intel,baytrail-cpu";
94 compatible = "intel,baytrail-cpu";
101 compatible = "intel,baytrail-cpu";
108 compatible = "intel,baytrail-cpu";
116 compatible = "intel,pci-baytrail", "pci-x86";
117 #address-cells = <3>;
120 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
121 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
122 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
125 reg = <0x0000f800 0 0 0 0>;
126 compatible = "pci8086,0f1c", "intel,pch9";
127 #address-cells = <1>;
131 compatible = "intel,irq-router";
132 intel,pirq-config = "ibase";
133 intel,ibase-offset = <0x50>;
134 intel,actl-addr = <0>;
135 intel,pirq-link = <8 8>;
136 intel,pirq-mask = <0xdee0>;
137 intel,pirq-routing = <
138 /* BayTrail PCI devices */
139 PCI_BDF(0, 2, 0) INTA PIRQA
140 PCI_BDF(0, 3, 0) INTA PIRQA
141 PCI_BDF(0, 16, 0) INTA PIRQA
142 PCI_BDF(0, 17, 0) INTA PIRQA
143 PCI_BDF(0, 18, 0) INTA PIRQA
144 PCI_BDF(0, 19, 0) INTA PIRQA
145 PCI_BDF(0, 20, 0) INTA PIRQA
146 PCI_BDF(0, 21, 0) INTA PIRQA
147 PCI_BDF(0, 22, 0) INTA PIRQA
148 PCI_BDF(0, 23, 0) INTA PIRQA
149 PCI_BDF(0, 24, 0) INTA PIRQA
150 PCI_BDF(0, 24, 1) INTC PIRQC
151 PCI_BDF(0, 24, 2) INTD PIRQD
152 PCI_BDF(0, 24, 3) INTB PIRQB
153 PCI_BDF(0, 24, 4) INTA PIRQA
154 PCI_BDF(0, 24, 5) INTC PIRQC
155 PCI_BDF(0, 24, 6) INTD PIRQD
156 PCI_BDF(0, 24, 7) INTB PIRQB
157 PCI_BDF(0, 26, 0) INTA PIRQA
158 PCI_BDF(0, 27, 0) INTA PIRQA
159 PCI_BDF(0, 28, 0) INTA PIRQA
160 PCI_BDF(0, 28, 1) INTB PIRQB
161 PCI_BDF(0, 28, 2) INTC PIRQC
162 PCI_BDF(0, 28, 3) INTD PIRQD
163 PCI_BDF(0, 29, 0) INTA PIRQA
164 PCI_BDF(0, 30, 0) INTA PIRQA
165 PCI_BDF(0, 30, 1) INTD PIRQD
166 PCI_BDF(0, 30, 2) INTB PIRQB
167 PCI_BDF(0, 30, 3) INTC PIRQC
168 PCI_BDF(0, 30, 4) INTD PIRQD
169 PCI_BDF(0, 30, 5) INTB PIRQB
170 PCI_BDF(0, 31, 3) INTB PIRQB
173 * PCIe root ports downstream
176 PCI_BDF(1, 0, 0) INTA PIRQA
177 PCI_BDF(1, 0, 0) INTB PIRQB
178 PCI_BDF(1, 0, 0) INTC PIRQC
179 PCI_BDF(1, 0, 0) INTD PIRQD
180 PCI_BDF(2, 0, 0) INTA PIRQB
181 PCI_BDF(2, 0, 0) INTB PIRQC
182 PCI_BDF(2, 0, 0) INTC PIRQD
183 PCI_BDF(2, 0, 0) INTD PIRQA
184 PCI_BDF(3, 0, 0) INTA PIRQC
185 PCI_BDF(3, 0, 0) INTB PIRQD
186 PCI_BDF(3, 0, 0) INTC PIRQA
187 PCI_BDF(3, 0, 0) INTD PIRQB
188 PCI_BDF(4, 0, 0) INTA PIRQD
189 PCI_BDF(4, 0, 0) INTB PIRQA
190 PCI_BDF(4, 0, 0) INTC PIRQB
191 PCI_BDF(4, 0, 0) INTD PIRQC
196 #address-cells = <1>;
198 compatible = "intel,ich9-spi";
200 #address-cells = <1>;
204 compatible = "macronix,mx25l6405d",
206 memory-map = <0xff800000 0x00800000>;
208 label = "rw-mrc-cache";
209 reg = <0x006f0000 0x00010000>;
215 compatible = "intel,ich6-gpio";
223 compatible = "intel,ich6-gpio";
231 compatible = "intel,ich6-gpio";
239 compatible = "intel,ich6-gpio";
247 compatible = "intel,ich6-gpio";
255 compatible = "intel,ich6-gpio";
265 compatible = "intel,baytrail-fsp";
266 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
267 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
268 fsp,mrc-init-spd-addr1 = <0xa0>;
269 fsp,mrc-init-spd-addr2 = <0xa2>;
272 fsp,sata-mode = <SATA_MODE_AHCI>;
274 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
286 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
287 fsp,aperture-size = <APERTURE_SIZE_256MB>;
288 fsp,gtt-size = <GTT_SIZE_2MB>;
289 fsp,scc-mode = <SCC_MODE_PCI>;
290 fsp,os-selection = <OS_SELECTION_LINUX>;
296 #include "microcode/m0130673325.dtsi"
299 #include "microcode/m0130679907.dtsi"