arch/x86/dts/bayleybay.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <asm/arch-baytrail/fsp/fsp_configs.h>
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "keyboard.dtsi"
  14 /include/ "serial.dtsi"
  15 /include/ "reset.dtsi"
  16 /include/ "rtc.dtsi"
  17
  18 #include "tsc_timer.dtsi"
  19 #include "smbios.dtsi"
  20
  21 / {
  22         model = "Intel Bayley Bay";
  23         compatible = "intel,bayleybay", "intel,baytrail";
  24
  25         aliases {
  26                 serial0 = &serial;
  27                 spi0 = &spi;
  28         };
  29
  30         config {
  31                 silent_console = <0>;
  32         };
  33
  34         chosen {
  35                 stdout-path = "/serial";
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "intel,baytrail-cpu";
  45                         reg = <0>;
  46                         intel,apic-id = <0>;
  47                 };
  48
  49                 cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "intel,baytrail-cpu";
  52                         reg = <1>;
  53                         intel,apic-id = <2>;
  54                 };
  55
  56                 cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "intel,baytrail-cpu";
  59                         reg = <2>;
  60                         intel,apic-id = <4>;
  61                 };
  62
  63                 cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "intel,baytrail-cpu";
  66                         reg = <3>;
  67                         intel,apic-id = <6>;
  68                 };
  69         };
  70
  71         pch_pinctrl {
  72                 compatible = "intel,x86-pinctrl";
  73                 reg = <0 0>;
  74
  75                 /*
  76                  * As of today, the latest version FSP (gold4) for BayTrail
  77                  * misses the PAD configuration of the SD controller's Card
  78                  * Detect signal. The default PAD value for the CD pin sets
  79                  * the pin to work in GPIO mode, which causes card detect
  80                  * status cannot be reflected by the Present State register
  81                  * in the SD controller (bit 16 & bit 18 are always zero).
  82                  *
  83                  * Configure this pin to function 1 (SD controller).
  84                  */
  85                 sdmmc3_cd@0 {
  86                         pad-offset = <0x3a0>;
  87                         mode-func = <1>;
  88                 };
  89         };
  90
  91         pci {
  92                 compatible = "pci-x86";
  93                 #address-cells = <3>;
  94                 #size-cells = <2>;
  95                 bootph-all;
  96                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  97                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  98                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  99
 100                 pch@1f,0 {
 101                         reg = <0x0000f800 0 0 0 0>;
 102                         compatible = "intel,pch9";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105
 106                         irq-router {
 107                                 compatible = "intel,irq-router";
 108                                 intel,pirq-config = "ibase";
 109                                 intel,ibase-offset = <0x50>;
 110                                 intel,actl-addr = <0>;
 111                                 intel,pirq-link = <8 8>;
 112                                 intel,pirq-mask = <0xdee0>;
 113                                 intel,pirq-routing = <
 114                                         /* BayTrail PCI devices */
 115                                         PCI_BDF(0, 2, 0) INTA PIRQA
 116                                         PCI_BDF(0, 3, 0) INTA PIRQA
 117                                         PCI_BDF(0, 16, 0) INTA PIRQA
 118                                         PCI_BDF(0, 17, 0) INTA PIRQA
 119                                         PCI_BDF(0, 18, 0) INTA PIRQA
 120                                         PCI_BDF(0, 19, 0) INTA PIRQA
 121                                         PCI_BDF(0, 20, 0) INTA PIRQA
 122                                         PCI_BDF(0, 21, 0) INTA PIRQA
 123                                         PCI_BDF(0, 22, 0) INTA PIRQA
 124                                         PCI_BDF(0, 23, 0) INTA PIRQA
 125                                         PCI_BDF(0, 24, 0) INTA PIRQA
 126                                         PCI_BDF(0, 24, 1) INTC PIRQC
 127                                         PCI_BDF(0, 24, 2) INTD PIRQD
 128                                         PCI_BDF(0, 24, 3) INTB PIRQB
 129                                         PCI_BDF(0, 24, 4) INTA PIRQA
 130                                         PCI_BDF(0, 24, 5) INTC PIRQC
 131                                         PCI_BDF(0, 24, 6) INTD PIRQD
 132                                         PCI_BDF(0, 24, 7) INTB PIRQB
 133                                         PCI_BDF(0, 26, 0) INTA PIRQA
 134                                         PCI_BDF(0, 27, 0) INTA PIRQA
 135                                         PCI_BDF(0, 28, 0) INTA PIRQA
 136                                         PCI_BDF(0, 28, 1) INTB PIRQB
 137                                         PCI_BDF(0, 28, 2) INTC PIRQC
 138                                         PCI_BDF(0, 28, 3) INTD PIRQD
 139                                         PCI_BDF(0, 29, 0) INTA PIRQA
 140                                         PCI_BDF(0, 30, 0) INTA PIRQA
 141                                         PCI_BDF(0, 30, 1) INTD PIRQD
 142                                         PCI_BDF(0, 30, 2) INTB PIRQB
 143                                         PCI_BDF(0, 30, 3) INTC PIRQC
 144                                         PCI_BDF(0, 30, 4) INTD PIRQD
 145                                         PCI_BDF(0, 30, 5) INTB PIRQB
 146                                         PCI_BDF(0, 31, 3) INTB PIRQB
 147
 148                                         /*
 149                                          * PCIe root ports downstream
 150                                          * interrupts
 151                                          */
 152                                         PCI_BDF(1, 0, 0) INTA PIRQA
 153                                         PCI_BDF(1, 0, 0) INTB PIRQB
 154                                         PCI_BDF(1, 0, 0) INTC PIRQC
 155                                         PCI_BDF(1, 0, 0) INTD PIRQD
 156                                         PCI_BDF(2, 0, 0) INTA PIRQB
 157                                         PCI_BDF(2, 0, 0) INTB PIRQC
 158                                         PCI_BDF(2, 0, 0) INTC PIRQD
 159                                         PCI_BDF(2, 0, 0) INTD PIRQA
 160                                         PCI_BDF(3, 0, 0) INTA PIRQC
 161                                         PCI_BDF(3, 0, 0) INTB PIRQD
 162                                         PCI_BDF(3, 0, 0) INTC PIRQA
 163                                         PCI_BDF(3, 0, 0) INTD PIRQB
 164                                         PCI_BDF(4, 0, 0) INTA PIRQD
 165                                         PCI_BDF(4, 0, 0) INTB PIRQA
 166                                         PCI_BDF(4, 0, 0) INTC PIRQB
 167                                         PCI_BDF(4, 0, 0) INTD PIRQC
 168                                 >;
 169                         };
 170
 171                         spi: spi {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                                 compatible = "intel,ich9-spi";
 175                                 spi-flash@0 {
 176                                         #address-cells = <1>;
 177                                         #size-cells = <1>;
 178                                         reg = <0>;
 179                                         m25p,fast-read;
 180                                         compatible = "winbond,w25q64dw",
 181                                                 "jedec,spi-nor";
 182                                         memory-map = <0xff800000 0x00800000>;
 183                                         rw-mrc-cache {
 184                                                 label = "rw-mrc-cache";
 185                                                 reg = <0x006e0000 0x00010000>;
 186                                         };
 187                                 };
 188                         };
 189
 190                         gpioa {
 191                                 compatible = "intel,ich6-gpio";
 192                                 bootph-all;
 193                                 reg = <0 0x20>;
 194                                 bank-name = "A";
 195                                 use-lvl-write-cache;
 196                         };
 197
 198                         gpiob {
 199                                 compatible = "intel,ich6-gpio";
 200                                 bootph-all;
 201                                 reg = <0x20 0x20>;
 202                                 bank-name = "B";
 203                                 use-lvl-write-cache;
 204                         };
 205
 206                         gpioc {
 207                                 compatible = "intel,ich6-gpio";
 208                                 bootph-all;
 209                                 reg = <0x40 0x20>;
 210                                 bank-name = "C";
 211                                 use-lvl-write-cache;
 212                         };
 213
 214                         gpiod {
 215                                 compatible = "intel,ich6-gpio";
 216                                 bootph-all;
 217                                 reg = <0x60 0x20>;
 218                                 bank-name = "D";
 219                                 use-lvl-write-cache;
 220                         };
 221
 222                         gpioe {
 223                                 compatible = "intel,ich6-gpio";
 224                                 bootph-all;
 225                                 reg = <0x80 0x20>;
 226                                 bank-name = "E";
 227                                 use-lvl-write-cache;
 228                         };
 229
 230                         gpiof {
 231                                 compatible = "intel,ich6-gpio";
 232                                 bootph-all;
 233                                 reg = <0xA0 0x20>;
 234                                 bank-name = "F";
 235                                 use-lvl-write-cache;
 236                         };
 237                 };
 238         };
 239
 240         fsp {
 241                 compatible = "intel,baytrail-fsp";
 242                 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
 243                 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 244                 fsp,mrc-init-spd-addr1 = <0xa0>;
 245                 fsp,mrc-init-spd-addr2 = <0xa2>;
 246                 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
 247                 fsp,enable-sdio;
 248                 fsp,enable-sdcard;
 249                 fsp,enable-hsuart1;
 250                 fsp,enable-spi;
 251                 fsp,enable-sata;
 252                 fsp,sata-mode = <SATA_MODE_AHCI>;
 253                 fsp,lpe-mode = <LPE_MODE_PCI>;
 254                 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 255                 fsp,enable-dma0;
 256                 fsp,enable-dma1;
 257                 fsp,enable-i2c0;
 258                 fsp,enable-i2c1;
 259                 fsp,enable-i2c2;
 260                 fsp,enable-i2c3;
 261                 fsp,enable-i2c4;
 262                 fsp,enable-i2c5;
 263                 fsp,enable-i2c6;
 264                 fsp,enable-pwm0;
 265                 fsp,enable-pwm1;
 266                 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 267                 fsp,aperture-size = <APERTURE_SIZE_256MB>;
 268                 fsp,gtt-size = <GTT_SIZE_2MB>;
 269                 fsp,scc-mode = <SCC_MODE_PCI>;
 270                 fsp,os-selection = <OS_SELECTION_LINUX>;
 271                 fsp,emmc45-ddr50-enabled;
 272                 fsp,emmc45-retune-timer-value = <8>;
 273                 fsp,enable-igd;
 274         };
 275
 276         microcode {
 277                 update@0 {
 278 #include "microcode/m0230671117.dtsi"
 279                 };
 280                 update@1 {
 281 #include "microcode/m0130673325.dtsi"
 282                 };
 283                 update@2 {
 284 #include "microcode/m0130679907.dtsi"
 285                 };
 286         };
 287
 288 };