1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * 32-bit x86 Startup Code when running from SPL. This is the startup code in
4 * U-Boot proper, when SPL is used.
6 * Copyright 2018 Google, Inc
7 * Written by Simon Glass <sjg@chromium.org>
15 .type _start, @function
18 * If running from coreboot, CAR is no-longer available. Use the
19 * existing stack, which is large enough.
21 call locate_coreboot_table
23 jge use_existing_stack
25 movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax
26 #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
27 subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax
31 * We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
32 * already set up. This has the happy side-effect of putting gd in a
33 * new place separate from SPL, so the memset() in
34 * board_init_f_init_reserve() does not cause any problems (otherwise
35 * it would zero out the gd and crash)
37 /* Set up memory using the existing stack */
41 call board_init_f_alloc_reserve
44 call board_init_f_init_reserve
46 #ifdef CONFIG_DEBUG_UART
55 /* Should not return here */
58 .globl board_init_f_r_trampoline
59 .type board_init_f_r_trampoline, @function
60 board_init_f_r_trampoline:
62 * SPL has been executed and SDRAM has been initialised, U-Boot code
63 * has been copied into RAM, BSS has been cleared and relocation
64 * adjustments have been made. It is now time to jump into the in-RAM
67 * %eax = Address of top of new stack
70 /* Stack grows down from top of SDRAM */
73 /* Re-enter U-Boot by calling board_init_f_r() */
83 /* These next two fields are filled in by binman */
85 ucode_base: /* Declared in microcode.h */
86 .long 0 /* microcode base */
88 ucode_size: /* Declared in microcode.h */
89 .long 0 /* microcode size */