arch/x86/cpu/queensbay/tnc.c

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/irq.h>
  10 #include <asm/pci.h>
  11 #include <asm/post.h>
  12 #include <asm/arch/device.h>
  13 #include <asm/arch/tnc.h>
  14 #include <asm/fsp/fsp_support.h>
  15 #include <asm/processor.h>
  16
  17 static void unprotect_spi_flash(void)
  18 {
  19         u32 bc;
  20
  21         bc = x86_pci_read_config32(TNC_LPC, 0xd8);
  22         bc |= 0x1;      /* unprotect the flash */
  23         x86_pci_write_config32(TNC_LPC, 0xd8, bc);
  24 }
  25
  26 static void __maybe_unused disable_igd(void)
  27 {
  28         u32 gc;
  29
  30         gc = x86_pci_read_config32(TNC_IGD, IGD_GC);
  31         gc &= ~GMS_MASK;
  32         gc |= VGA_DISABLE;
  33         x86_pci_write_config32(TNC_IGD, IGD_GC, gc);
  34 }
  35
  36 int arch_cpu_init(void)
  37 {
  38         int ret;
  39
  40         post_code(POST_CPU_INIT);
  41 #ifdef CONFIG_SYS_X86_TSC_TIMER
  42         timer_set_base(rdtsc());
  43 #endif
  44
  45         ret = x86_cpu_init_f();
  46         if (ret)
  47                 return ret;
  48
  49         return 0;
  50 }
  51
  52 int arch_early_init_r(void)
  53 {
  54 #ifdef CONFIG_DISABLE_IGD
  55         disable_igd();
  56 #endif
  57
  58         return 0;
  59 }
  60
  61 void cpu_irq_init(void)
  62 {
  63         struct tnc_rcba *rcba;
  64         u32 base;
  65
  66         base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
  67         base &= ~MEM_BAR_EN;
  68         rcba = (struct tnc_rcba *)base;
  69
  70         /* Make sure all internal PCI devices are using INTA */
  71         writel(INTA, &rcba->d02ip);
  72         writel(INTA, &rcba->d03ip);
  73         writel(INTA, &rcba->d27ip);
  74         writel(INTA, &rcba->d31ip);
  75         writel(INTA, &rcba->d23ip);
  76         writel(INTA, &rcba->d24ip);
  77         writel(INTA, &rcba->d25ip);
  78         writel(INTA, &rcba->d26ip);
  79
  80         /*
  81          * Route TunnelCreek PCI device interrupt pin to PIRQ
  82          *
  83          * Since PCIe downstream ports received INTx are routed to PIRQ
  84          * A/B/C/D directly and not configurable, we have to route PCIe
  85          * root ports' INTx to PIRQ A/B/C/D as well. For other devices
  86          * on TunneCreek, route them to PIRQ E/F/G/H.
  87          */
  88         writew(PIRQE, &rcba->d02ir);
  89         writew(PIRQF, &rcba->d03ir);
  90         writew(PIRQG, &rcba->d27ir);
  91         writew(PIRQH, &rcba->d31ir);
  92         writew(PIRQA, &rcba->d23ir);
  93         writew(PIRQB, &rcba->d24ir);
  94         writew(PIRQC, &rcba->d25ir);
  95         writew(PIRQD, &rcba->d26ir);
  96 }
  97
  98 int arch_misc_init(void)
  99 {
 100         unprotect_spi_flash();
 101
 102         return pirq_init();
 103 }