2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
16 #include <asm/arch/device.h>
17 #include <asm/arch/msg_port.h>
18 #include <asm/arch/quark.h>
20 static struct pci_device_id mmc_supported[] = {
21 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
27 * This whole routine should be removed until we fully convert the ICH SPI
28 * driver to DM and make use of DT to pass the bios control register offset
30 static void unprotect_spi_flash(void)
34 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
35 bc |= 0x1; /* unprotect the flash */
36 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
39 static void quark_setup_bars(void)
41 /* GPIO - D31:F0:R44h */
42 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
43 CONFIG_GPIO_BASE | IO_BAR_EN);
45 /* ACPI PM1 Block - D31:F0:R48h */
46 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
47 CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
49 /* GPE0 - D31:F0:R4Ch */
50 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
51 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
53 /* WDT - D31:F0:R84h */
54 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
55 CONFIG_WDT_BASE | IO_BAR_EN);
57 /* RCBA - D31:F0:RF0h */
58 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
59 CONFIG_RCBA_BASE | MEM_BAR_EN);
61 /* ACPI P Block - Msg Port 04:R70h */
62 msg_port_write(MSG_PORT_RMU, PBLK_BA,
63 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
65 /* SPI DMA - Msg Port 04:R7Ah */
66 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
67 CONFIG_SPI_DMA_BASE | IO_BAR_EN);
70 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
71 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
72 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
73 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
76 static void quark_pcie_early_init(void)
81 * Step1: Assert PCIe signal PERST#
83 * The CPU interface to the PERST# signal is platform dependent.
84 * Call the board-specific codes to perform this task.
88 /* Step2: PHY common lane reset */
89 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
90 pcie_cfg |= PCIE_PHY_LANE_RST;
91 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
92 /* wait 1 ms for PHY common lane reset */
95 /* Step3: PHY sideband interface reset and controller main reset */
96 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
97 pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
98 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
99 /* wait 80ms for PLL to lock */
102 /* Step4: Controller sideband interface reset */
103 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
104 pcie_cfg |= PCIE_CTLR_SB_RST;
105 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
106 /* wait 20ms for controller sideband interface reset */
109 /* Step5: De-assert PERST# */
110 board_deassert_perst();
112 /* Step6: Controller primary interface reset */
113 pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
114 pcie_cfg |= PCIE_CTLR_PRI_RST;
115 msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
117 /* Mixer Load Lane 0 */
118 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0);
119 pcie_cfg &= ~((1 << 6) | (1 << 7));
120 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg);
122 /* Mixer Load Lane 1 */
123 pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1);
124 pcie_cfg &= ~((1 << 6) | (1 << 7));
125 msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg);
128 static void quark_usb_early_init(void)
132 /* The sequence below comes from Quark firmware writer guide */
134 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT);
136 usb |= ((1 << 6) | (1 << 7));
137 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, usb);
139 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_COMPBG);
140 usb &= ~((1 << 8) | (1 << 9));
141 usb |= ((1 << 7) | (1 << 10));
142 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_COMPBG, usb);
144 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
146 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
148 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
150 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
152 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
153 usb &= ~((1 << 3) | (1 << 4) | (1 << 5));
155 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
157 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
159 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
161 usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
163 msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
166 static void quark_enable_legacy_seg(void)
170 hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
171 hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
172 msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
175 int arch_cpu_init(void)
179 post_code(POST_CPU_INIT);
180 #ifdef CONFIG_SYS_X86_TSC_TIMER
181 timer_set_base(rdtsc());
184 ret = x86_cpu_init_f();
189 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
190 * which need be initialized with suggested values
195 * Initialize PCIe controller
197 * Quark SoC holds the PCIe controller in reset following a power on.
198 * U-Boot needs to release the PCIe controller from reset. The PCIe
199 * controller (D23:F0/F1) will not be visible in PCI configuration
200 * space and any access to its PCI configuration registers will cause
201 * system hang while it is held in reset.
203 quark_pcie_early_init();
205 /* Initialize USB2 PHY */
206 quark_usb_early_init();
208 /* Turn on legacy segments (A/B/E/F) decode to system RAM */
209 quark_enable_legacy_seg();
211 unprotect_spi_flash();
216 int print_cpuinfo(void)
218 post_code(POST_CPU_INFO);
219 return default_print_cpuinfo();
222 void reset_cpu(ulong addr)
228 int cpu_mmc_init(bd_t *bis)
230 return pci_mmc_init("Quark SDHCI", mmc_supported,
231 ARRAY_SIZE(mmc_supported));
234 int cpu_eth_init(bd_t *bis)
239 qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
240 ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
242 qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
243 ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
245 if (ret0 < 0 && ret1 < 0)
251 void cpu_irq_init(void)
253 struct quark_rcba *rcba;
256 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
258 rcba = (struct quark_rcba *)base;
261 * Route Quark PCI device interrupt pin to PIRQ
263 * Route device#23's INTA/B/C/D to PIRQA/B/C/D
264 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
266 writew(PIRQC, &rcba->rmu_ir);
267 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
269 writew(PIRQD, &rcba->core_ir);
270 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
274 int arch_misc_init(void)