arch/x86/cpu/quark/quark.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <mmc.h>
   9 #include <asm/io.h>
  10 #include <asm/pci.h>
  11 #include <asm/post.h>
  12 #include <asm/processor.h>
  13 #include <asm/arch/device.h>
  14 #include <asm/arch/msg_port.h>
  15 #include <asm/arch/quark.h>
  16
  17 static struct pci_device_id mmc_supported[] = {
  18         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
  19 };
  20
  21 /*
  22  * TODO:
  23  *
  24  * This whole routine should be removed until we fully convert the ICH SPI
  25  * driver to DM and make use of DT to pass the bios control register offset
  26  */
  27 static void unprotect_spi_flash(void)
  28 {
  29         u32 bc;
  30
  31         bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
  32         bc |= 0x1;      /* unprotect the flash */
  33         pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
  34 }
  35
  36 static void quark_setup_bars(void)
  37 {
  38         /* GPIO - D31:F0:R44h */
  39         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  40                                CONFIG_GPIO_BASE | IO_BAR_EN);
  41
  42         /* ACPI PM1 Block - D31:F0:R48h */
  43         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  44                                CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  45
  46         /* GPE0 - D31:F0:R4Ch */
  47         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  48                                CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  49
  50         /* WDT - D31:F0:R84h */
  51         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  52                                CONFIG_WDT_BASE | IO_BAR_EN);
  53
  54         /* RCBA - D31:F0:RF0h */
  55         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  56                                CONFIG_RCBA_BASE | MEM_BAR_EN);
  57
  58         /* ACPI P Block - Msg Port 04:R70h */
  59         msg_port_write(MSG_PORT_RMU, PBLK_BA,
  60                        CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  61
  62         /* SPI DMA - Msg Port 04:R7Ah */
  63         msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  64                        CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  65
  66         /* PCIe ECAM */
  67         msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
  68                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  69         msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
  70                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  71 }
  72
  73 int arch_cpu_init(void)
  74 {
  75         struct pci_controller *hose;
  76         int ret;
  77
  78         post_code(POST_CPU_INIT);
  79 #ifdef CONFIG_SYS_X86_TSC_TIMER
  80         timer_set_base(rdtsc());
  81 #endif
  82
  83         ret = x86_cpu_init_f();
  84         if (ret)
  85                 return ret;
  86
  87         ret = pci_early_init_hose(&hose);
  88         if (ret)
  89                 return ret;
  90
  91         /*
  92          * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
  93          * which need be initialized with suggested values
  94          */
  95         quark_setup_bars();
  96
  97         unprotect_spi_flash();
  98
  99         return 0;
 100 }
 101
 102 int print_cpuinfo(void)
 103 {
 104         post_code(POST_CPU_INFO);
 105         return default_print_cpuinfo();
 106 }
 107
 108 void reset_cpu(ulong addr)
 109 {
 110         /* cold reset */
 111         outb(0x08, PORT_RESET);
 112 }
 113
 114 int cpu_mmc_init(bd_t *bis)
 115 {
 116         return pci_mmc_init("Quark SDHCI", mmc_supported,
 117                             ARRAY_SIZE(mmc_supported));
 118 }