1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
29 #include <linux/log2.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
43 /* Prepare to adjust MTRRs */
44 void mtrr_open(struct mtrr_state *state, bool do_caches)
46 if (!gd->arch.has_mtrr)
50 state->enable_cache = dcache_status();
52 if (state->enable_cache)
55 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
56 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
59 /* Clean up after adjusting MTRRs, and enable them */
60 void mtrr_close(struct mtrr_state *state, bool do_caches)
62 if (!gd->arch.has_mtrr)
65 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
66 if (do_caches && state->enable_cache)
70 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
74 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
76 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
77 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
80 void mtrr_read_all(struct mtrr_info *info)
82 int reg_count = mtrr_get_var_count();
85 for (i = 0; i < reg_count; i++) {
86 info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
87 info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
91 void mtrr_write_all(struct mtrr_info *info)
93 int reg_count = mtrr_get_var_count();
94 struct mtrr_state state;
97 for (i = 0; i < reg_count; i++) {
98 mtrr_open(&state, true);
99 wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base);
100 wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask);
101 mtrr_close(&state, true);
105 static void write_mtrrs(void *arg)
107 struct mtrr_info *info = arg;
109 mtrr_write_all(info);
112 static void read_mtrrs(void *arg)
114 struct mtrr_info *info = arg;
120 * mtrr_copy_to_aps() - Copy the MTRRs from the boot CPU to other CPUs
122 * Return: 0 on success, -ve on failure
124 static int mtrr_copy_to_aps(void)
126 struct mtrr_info info;
129 ret = mp_run_on_cpus(MP_SELECT_BSP, read_mtrrs, &info);
133 return log_msg_ret("bsp", ret);
135 ret = mp_run_on_cpus(MP_SELECT_APS, write_mtrrs, &info);
137 return log_msg_ret("bsp", ret);
142 static int h_comp_mtrr(const void *p1, const void *p2)
144 const struct mtrr_request *req1 = p1;
145 const struct mtrr_request *req2 = p2;
147 s64 diff = req1->start - req2->start;
149 return diff < 0 ? -1 : diff > 0 ? 1 : 0;
152 int mtrr_commit(bool do_caches)
154 struct mtrr_request *req = gd->arch.mtrr_req;
155 struct mtrr_state state;
159 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
160 gd->arch.mtrr_req_count);
161 if (!gd->arch.has_mtrr)
165 mtrr_open(&state, do_caches);
166 debug("open done\n");
167 qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
168 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
169 set_var_mtrr(i, req->type, req->start, req->size);
171 /* Clear the ones that are unused */
173 for (; i < mtrr_get_var_count(); i++)
174 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
176 mtrr_close(&state, do_caches);
177 debug("mtrr done\n");
179 if (gd->flags & GD_FLG_RELOC) {
180 ret = mtrr_copy_to_aps();
182 return log_msg_ret("copy", ret);
188 int mtrr_add_request(int type, uint64_t start, uint64_t size)
190 struct mtrr_request *req;
193 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
194 if (!gd->arch.has_mtrr)
197 if (!is_power_of_2(size))
200 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
202 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
206 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
207 req->type, req->start, req->size);
208 mask = ~(req->size - 1);
209 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
210 mask |= MTRR_PHYS_MASK_VALID;
211 debug(" %016llx %016llx\n", req->start | req->type, mask);
216 int mtrr_get_var_count(void)
218 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
221 static int get_free_var_mtrr(void)
227 vcnt = mtrr_get_var_count();
229 /* Identify the first var mtrr which is not valid */
230 for (i = 0; i < vcnt; i++) {
231 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
232 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
236 /* No free var mtrr */
240 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
244 if (!is_power_of_2(size))
247 mtrr = get_free_var_mtrr();
251 set_var_mtrr(mtrr, type, start, size);
252 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);
257 /** enum mtrr_opcode - supported operations for mtrr_do_oper() */
264 * struct mtrr_oper - An MTRR operation to perform on a CPU
266 * @opcode: Indicates operation to perform
267 * @reg: MTRR reg number to select (0-7, -1 = all)
268 * @valid: Valid value to write for MTRR_OP_SET_VALID
269 * @base: Base value to write for MTRR_OP_SET
270 * @mask: Mask value to write for MTRR_OP_SET
273 enum mtrr_opcode opcode;
280 static void mtrr_do_oper(void *arg)
282 struct mtrr_oper *oper = arg;
285 switch (oper->opcode) {
286 case MTRR_OP_SET_VALID:
287 mask = native_read_msr(MTRR_PHYS_MASK_MSR(oper->reg));
289 mask |= MTRR_PHYS_MASK_VALID;
291 mask &= ~MTRR_PHYS_MASK_VALID;
292 wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), mask);
295 wrmsrl(MTRR_PHYS_BASE_MSR(oper->reg), oper->base);
296 wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), oper->mask);
301 static int mtrr_start_op(int cpu_select, struct mtrr_oper *oper)
303 struct mtrr_state state;
306 mtrr_open(&state, true);
307 ret = mp_run_on_cpus(cpu_select, mtrr_do_oper, oper);
308 mtrr_close(&state, true);
310 return log_msg_ret("run", ret);
315 int mtrr_set_valid(int cpu_select, int reg, bool valid)
317 struct mtrr_oper oper;
319 oper.opcode = MTRR_OP_SET_VALID;
323 return mtrr_start_op(cpu_select, &oper);
326 int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
328 struct mtrr_oper oper;
330 oper.opcode = MTRR_OP_SET;
335 return mtrr_start_op(cpu_select, &oper);
338 static void read_mtrrs_(void *arg)
340 struct mtrr_info *info = arg;
345 int mtrr_list(int reg_count, int cpu_select)
347 struct mtrr_info info;
351 printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
352 "Mask ||", "Size ||");
353 memset(&info, '\0', sizeof(info));
354 ret = mp_run_on_cpus(cpu_select, read_mtrrs_, &info);
356 return log_msg_ret("run", ret);
357 for (i = 0; i < reg_count; i++) {
358 const char *type = "Invalid";
359 u64 base, mask, size;
362 base = info.mtrr[i].base;
363 mask = info.mtrr[i].mask;
364 size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
365 size |= (1 << 12) - 1;
367 valid = mask & MTRR_PHYS_MASK_VALID;
368 type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
369 printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
370 valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
371 mask & ~MTRR_PHYS_MASK_VALID, size);
377 int mtrr_get_type_by_name(const char *typename)
381 for (i = 0; i < MTRR_TYPE_COUNT; i++) {
382 if (*typename == *mtrr_type_name[i])