1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
23 #include <asm/cache.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* Prepare to adjust MTRRs */
32 void mtrr_open(struct mtrr_state *state, bool do_caches)
34 if (!gd->arch.has_mtrr)
38 state->enable_cache = dcache_status();
40 if (state->enable_cache)
43 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
44 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
47 /* Clean up after adjusting MTRRs, and enable them */
48 void mtrr_close(struct mtrr_state *state, bool do_caches)
50 if (!gd->arch.has_mtrr)
53 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
54 if (do_caches && state->enable_cache)
58 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
62 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
64 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
65 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
68 void mtrr_read_all(struct mtrr_info *info)
70 int reg_count = mtrr_get_var_count();
73 for (i = 0; i < reg_count; i++) {
74 info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
75 info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
79 void mtrr_write_all(struct mtrr_info *info)
81 int reg_count = mtrr_get_var_count();
82 struct mtrr_state state;
85 for (i = 0; i < reg_count; i++) {
86 mtrr_open(&state, true);
87 wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base);
88 wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask);
89 mtrr_close(&state, true);
93 static void write_mtrrs(void *arg)
95 struct mtrr_info *info = arg;
100 static void read_mtrrs(void *arg)
102 struct mtrr_info *info = arg;
108 * mtrr_copy_to_aps() - Copy the MTRRs from the boot CPU to other CPUs
110 * @return 0 on success, -ve on failure
112 static int mtrr_copy_to_aps(void)
114 struct mtrr_info info;
117 ret = mp_run_on_cpus(MP_SELECT_BSP, read_mtrrs, &info);
121 return log_msg_ret("bsp", ret);
123 ret = mp_run_on_cpus(MP_SELECT_APS, write_mtrrs, &info);
125 return log_msg_ret("bsp", ret);
130 static int h_comp_mtrr(const void *p1, const void *p2)
132 const struct mtrr_request *req1 = p1;
133 const struct mtrr_request *req2 = p2;
135 s64 diff = req1->start - req2->start;
137 return diff < 0 ? -1 : diff > 0 ? 1 : 0;
140 int mtrr_commit(bool do_caches)
142 struct mtrr_request *req = gd->arch.mtrr_req;
143 struct mtrr_state state;
147 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
148 gd->arch.mtrr_req_count);
149 if (!gd->arch.has_mtrr)
153 mtrr_open(&state, do_caches);
154 debug("open done\n");
155 qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
156 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
157 set_var_mtrr(i, req->type, req->start, req->size);
159 /* Clear the ones that are unused */
161 for (; i < MTRR_MAX_COUNT; i++)
162 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
164 mtrr_close(&state, do_caches);
165 debug("mtrr done\n");
167 if (gd->flags & GD_FLG_RELOC) {
168 ret = mtrr_copy_to_aps();
170 return log_msg_ret("copy", ret);
176 int mtrr_add_request(int type, uint64_t start, uint64_t size)
178 struct mtrr_request *req;
181 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
182 if (!gd->arch.has_mtrr)
185 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
187 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
191 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
192 req->type, req->start, req->size);
193 mask = ~(req->size - 1);
194 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
195 mask |= MTRR_PHYS_MASK_VALID;
196 debug(" %016llx %016llx\n", req->start | req->type, mask);
201 int mtrr_get_var_count(void)
203 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
206 static int get_free_var_mtrr(void)
212 vcnt = mtrr_get_var_count();
214 /* Identify the first var mtrr which is not valid */
215 for (i = 0; i < vcnt; i++) {
216 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
217 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
221 /* No free var mtrr */
225 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
229 mtrr = get_free_var_mtrr();
233 set_var_mtrr(mtrr, type, start, size);
234 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);
239 /** enum mtrr_opcode - supported operations for mtrr_do_oper() */
246 * struct mtrr_oper - An MTRR operation to perform on a CPU
248 * @opcode: Indicates operation to perform
249 * @reg: MTRR reg number to select (0-7, -1 = all)
250 * @valid: Valid value to write for MTRR_OP_SET_VALID
251 * @base: Base value to write for MTRR_OP_SET
252 * @mask: Mask value to write for MTRR_OP_SET
255 enum mtrr_opcode opcode;
262 static void mtrr_do_oper(void *arg)
264 struct mtrr_oper *oper = arg;
267 switch (oper->opcode) {
268 case MTRR_OP_SET_VALID:
269 mask = native_read_msr(MTRR_PHYS_MASK_MSR(oper->reg));
271 mask |= MTRR_PHYS_MASK_VALID;
273 mask &= ~MTRR_PHYS_MASK_VALID;
274 wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), mask);
277 wrmsrl(MTRR_PHYS_BASE_MSR(oper->reg), oper->base);
278 wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), oper->mask);
283 static int mtrr_start_op(int cpu_select, struct mtrr_oper *oper)
285 struct mtrr_state state;
288 mtrr_open(&state, true);
289 ret = mp_run_on_cpus(cpu_select, mtrr_do_oper, oper);
290 mtrr_close(&state, true);
292 return log_msg_ret("run", ret);
297 int mtrr_set_valid(int cpu_select, int reg, bool valid)
299 struct mtrr_oper oper;
301 oper.opcode = MTRR_OP_SET_VALID;
305 return mtrr_start_op(cpu_select, &oper);
308 int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
310 struct mtrr_oper oper;
312 oper.opcode = MTRR_OP_SET;
317 return mtrr_start_op(cpu_select, &oper);