1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Prepare to adjust MTRRs */
27 void mtrr_open(struct mtrr_state *state, bool do_caches)
29 if (!gd->arch.has_mtrr)
33 state->enable_cache = dcache_status();
35 if (state->enable_cache)
38 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
39 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
42 /* Clean up after adjusting MTRRs, and enable them */
43 void mtrr_close(struct mtrr_state *state, bool do_caches)
45 if (!gd->arch.has_mtrr)
48 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
49 if (do_caches && state->enable_cache)
53 int mtrr_commit(bool do_caches)
55 struct mtrr_request *req = gd->arch.mtrr_req;
56 struct mtrr_state state;
60 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
61 gd->arch.mtrr_req_count);
62 if (!gd->arch.has_mtrr)
66 mtrr_open(&state, do_caches);
68 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
69 mask = ~(req->size - 1);
70 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
71 wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type);
72 wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID);
75 /* Clear the ones that are unused */
77 for (; i < MTRR_COUNT; i++)
78 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
80 mtrr_close(&state, do_caches);
86 int mtrr_add_request(int type, uint64_t start, uint64_t size)
88 struct mtrr_request *req;
91 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
92 if (!gd->arch.has_mtrr)
95 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
97 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
101 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
102 req->type, req->start, req->size);
103 mask = ~(req->size - 1);
104 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
105 mask |= MTRR_PHYS_MASK_VALID;
106 debug(" %016llx %016llx\n", req->start | req->type, mask);