2 * (C) Copyright 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Memory Type Range Regsters - these are used to tell the CPU whether
7 * memory is cacheable and if so the cache write mode to use.
9 * These can speed up booting. See the mtrr command.
11 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
20 DECLARE_GLOBAL_DATA_PTR;
22 /* Prepare to adjust MTRRs */
23 void mtrr_open(struct mtrr_state *state)
25 state->enable_cache = dcache_status();
27 if (state->enable_cache)
29 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
30 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
33 /* Clean up after adjusting MTRRs, and enable them */
34 void mtrr_close(struct mtrr_state *state)
36 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
37 if (state->enable_cache)
41 int mtrr_commit(bool do_caches)
43 struct mtrr_request *req = gd->arch.mtrr_req;
44 struct mtrr_state state;
49 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
50 mask = ~(req->size - 1);
51 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
52 wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type);
53 wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID);
56 /* Clear the ones that are unused */
57 for (; i < MTRR_COUNT; i++)
58 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
64 int mtrr_add_request(int type, uint64_t start, uint64_t size)
66 struct mtrr_request *req;
69 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
71 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
75 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
76 req->type, req->start, req->size);
77 mask = ~(req->size - 1);
78 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
79 mask |= MTRR_PHYS_MASK_VALID;
80 debug(" %016llx %016llx\n", req->start | req->type, mask);