1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
22 #include <asm/cache.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 /* Prepare to adjust MTRRs */
30 void mtrr_open(struct mtrr_state *state, bool do_caches)
32 if (!gd->arch.has_mtrr)
36 state->enable_cache = dcache_status();
38 if (state->enable_cache)
41 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
42 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
45 /* Clean up after adjusting MTRRs, and enable them */
46 void mtrr_close(struct mtrr_state *state, bool do_caches)
48 if (!gd->arch.has_mtrr)
51 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
52 if (do_caches && state->enable_cache)
56 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
60 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
62 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
63 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
66 int mtrr_commit(bool do_caches)
68 struct mtrr_request *req = gd->arch.mtrr_req;
69 struct mtrr_state state;
72 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
73 gd->arch.mtrr_req_count);
74 if (!gd->arch.has_mtrr)
78 mtrr_open(&state, do_caches);
80 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
81 set_var_mtrr(i, req->type, req->start, req->size);
83 /* Clear the ones that are unused */
85 for (; i < MTRR_COUNT; i++)
86 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
88 mtrr_close(&state, do_caches);
94 int mtrr_add_request(int type, uint64_t start, uint64_t size)
96 struct mtrr_request *req;
99 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
100 if (!gd->arch.has_mtrr)
103 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
105 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
109 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
110 req->type, req->start, req->size);
111 mask = ~(req->size - 1);
112 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
113 mask |= MTRR_PHYS_MASK_VALID;
114 debug(" %016llx %016llx\n", req->start | req->type, mask);
119 static int get_var_mtrr_count(void)
121 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
124 static int get_free_var_mtrr(void)
130 vcnt = get_var_mtrr_count();
132 /* Identify the first var mtrr which is not valid */
133 for (i = 0; i < vcnt; i++) {
134 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
135 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
139 /* No free var mtrr */
143 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
147 mtrr = get_free_var_mtrr();
151 set_var_mtrr(mtrr, type, start, size);
152 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);