1 // SPDX-License-Identifier: GPL-2.0
3 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
5 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
13 #include <asm/processor.h>
14 #include <asm/arch/me.h>
15 #include <asm/arch/pch.h>
18 static const char *const me_ack_values[] = {
19 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
20 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
21 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
22 [ME_HFS_ACK_S3] = "Go to S3",
23 [ME_HFS_ACK_S4] = "Go to S4",
24 [ME_HFS_ACK_S5] = "Go to S5",
25 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
26 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
29 int intel_early_me_init(struct udevice *me_dev)
35 debug("Intel ME early init\n");
37 /* Wait for ME UMA SIZE VALID bit to be set */
38 for (count = ME_RETRY; count > 0; --count) {
39 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
45 printf("ERROR: ME is not ready!\n");
49 /* Check for valid firmware */
50 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
52 printf("WARNING: ME has bad firmware\n");
56 debug("Intel ME firmware is ready\n");
61 int intel_early_me_uma_size(struct udevice *me_dev)
65 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
67 debug("ME: Requested %uMB UMA\n", uma.size);
71 debug("ME: Invalid UMA size\n");
75 static inline void set_global_reset(struct udevice *dev, int enable)
79 dm_pci_read_config32(dev, ETR3, &etr3);
81 /* Clear CF9 Without Resume Well Reset Enable */
82 etr3 &= ~ETR3_CWORWRE;
84 /* CF9GR indicates a Global Reset */
90 dm_pci_write_config32(dev, ETR3, etr3);
93 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
97 u32 mebase_l, mebase_h;
100 .init_done = ME_INIT_DONE,
104 /* MEBASE from MESEG_BASE[35:20] */
105 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
106 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
108 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
110 /* Send message to ME */
111 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
112 status, did.uma_base);
114 pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
116 /* Must wait for ME acknowledgement */
117 for (count = ME_RETRY; count > 0; --count) {
118 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
119 if (hfs.bios_msg_ack)
124 printf("ERROR: ME failed to respond\n");
128 /* Return the requested BIOS action */
129 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
131 /* Check status after acknowledgement */
132 intel_me_status(me_dev);
134 switch (hfs.ack_data) {
135 case ME_HFS_ACK_CONTINUE:
136 /* Continue to boot */
138 case ME_HFS_ACK_RESET:
139 /* Non-power cycle reset */
140 set_global_reset(dev, 0);
143 case ME_HFS_ACK_PWR_CYCLE:
144 /* Power cycle reset */
145 set_global_reset(dev, 0);
148 case ME_HFS_ACK_GBL_RESET:
150 set_global_reset(dev, 1);
162 static const struct udevice_id ivybridge_syscon_ids[] = {
163 { .compatible = "intel,me", .data = X86_SYSCON_ME },
167 U_BOOT_DRIVER(syscon_intel_me) = {
168 .name = "intel_me_syscon",
170 .of_match = ivybridge_syscon_ids,