2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/lapic.h>
17 #include <asm/arch/bd82x6x.h>
18 #include <asm/arch/model_206ax.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/sandybridge.h>
22 #define BIOS_CTRL 0xdc
24 static int pch_revision_id = -1;
25 static int pch_type = -1;
28 * pch_silicon_revision() - Read silicon revision ID from the PCH
31 * @return silicon revision ID
33 static int pch_silicon_revision(struct udevice *dev)
37 if (pch_revision_id < 0) {
38 dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
39 pch_revision_id = val;
42 return pch_revision_id;
45 int pch_silicon_type(struct udevice *dev)
50 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
58 * pch_silicon_supported() - Check if a certain revision is supported
62 * @rev: Minimum required resion
63 * @return 0 if not supported, 1 if supported
65 static int pch_silicon_supported(struct udevice *dev, int type, int rev)
67 int cur_type = pch_silicon_type(dev);
68 int cur_rev = pch_silicon_revision(dev);
72 /* CougarPoint minimum revision */
73 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
75 /* PantherPoint any revision */
76 if (cur_type == PCH_TYPE_PPT)
81 /* PantherPoint minimum revision */
82 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
90 #define IOBP_RETRY 1000
91 static inline int iobp_poll(void)
93 unsigned try = IOBP_RETRY;
97 data = readl(RCB_REG(IOBPS));
103 printf("IOBP timeout\n");
107 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
112 /* Set the address */
113 writel(address, RCB_REG(IOBPIRI));
116 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
117 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
119 writel(IOBPS_READ_AX, RCB_REG(IOBPS));
124 data = readl(RCB_REG(IOBPD));
128 /* Check for successful transaction */
129 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
130 printf("IOBP read 0x%08x failed\n", address);
134 /* Update the data */
139 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
140 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
142 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
146 /* Write IOBP data */
147 writel(data, RCB_REG(IOBPD));
152 static int bd82x6x_probe(struct udevice *dev)
154 struct udevice *gma_dev;
157 if (!(gd->flags & GD_FLG_RELOC))
160 /* Cause the SATA device to do its init */
161 uclass_first_device(UCLASS_DISK, &dev);
163 ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
166 ret = gma_func0_init(gma_dev);
173 static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
177 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
178 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
179 rcba = rcba & 0xffffc000;
180 *sbasep = rcba + 0x3800;
185 static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
190 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
194 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
195 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
197 bios_cntl &= ~BIOS_CTRL_BIOSWE;
200 bios_cntl |= BIOS_CTRL_BIOSWE;
201 bios_cntl &= ~BIT(5);
203 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
208 static const struct pch_ops bd82x6x_pch_ops = {
209 .get_sbase = bd82x6x_pch_get_sbase,
210 .get_version = bd82x6x_pch_get_version,
211 .set_spi_protect = bd82x6x_set_spi_protect,
214 static const struct udevice_id bd82x6x_ids[] = {
215 { .compatible = "intel,bd82x6x" },
219 U_BOOT_DRIVER(bd82x6x_drv) = {
222 .of_match = bd82x6x_ids,
223 .probe = bd82x6x_probe,
224 .ops = &bd82x6x_pch_ops,