1 // SPDX-License-Identifier: GPL-2.0
3 * Primary-to-Sideband Bridge
5 * Copyright 2019 Google LLC
8 #define LOG_CATEGORY UCLASS_P2SB
12 #include <dt-structs.h>
17 struct p2sb_platdata {
18 #if CONFIG_IS_ENABLED(OF_PLATDATA)
19 struct dtd_intel_apl_p2sb dtplat;
25 /* PCI config space registers */
26 #define HPTC_OFFSET 0x60
27 #define HPTC_ADDR_ENABLE_BIT BIT(7)
29 /* High Performance Event Timer Configuration */
30 #define P2SB_HPTC 0x60
31 #define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
34 * ADDRESS_SELECT ENCODING_RANGE
35 * 0 0xfed0 0000 - 0xfed0 03ff
36 * 1 0xfed0 1000 - 0xfed0 13ff
37 * 2 0xfed0 2000 - 0xfed0 23ff
38 * 3 0xfed0 3000 - 0xfed0 33ff
40 #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
41 #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
42 #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
43 #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
46 * apl_p2sb_early_init() - Enable decoding for HPET range
48 * This is needed by FSP-M which uses the High Precision Event Timer.
51 * @return 0 if OK, -ve on error
53 static int apl_p2sb_early_init(struct udevice *dev)
55 struct p2sb_platdata *plat = dev_get_platdata(dev);
56 pci_dev_t pdev = plat->bdf;
59 * Enable decoding for HPET memory address range.
60 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
61 * the High Performance Timer memory address range
62 * selected by bits 1:0
64 pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
67 /* Enable PCR Base address in PCH */
68 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
70 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
73 pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
74 PCI_COMMAND_MEMORY, PCI_SIZE_8);
79 static int apl_p2sb_spl_init(struct udevice *dev)
81 /* Enable decoding for HPET. Needed for FSP global pointer storage */
82 dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
83 P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
88 int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
90 struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
91 struct p2sb_platdata *plat = dev_get_platdata(dev);
93 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
96 if (spl_phase() == PHASE_TPL) {
99 /* TPL sets up the initial BAR */
100 ret = dev_read_u32_array(dev, "early-regs", base,
103 return log_msg_ret("Missing/short early-regs", ret);
104 plat->mmio_base = base[0];
105 plat->bdf = pci_get_devfn(dev);
107 return log_msg_ret("Cannot get p2sb PCI address",
111 plat->mmio_base = plat->dtplat.early_regs[0];
112 plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
114 upriv->mmio_base = plat->mmio_base;
115 debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base);
120 static int apl_p2sb_probe(struct udevice *dev)
122 if (spl_phase() == PHASE_TPL) {
123 return apl_p2sb_early_init(dev);
125 struct p2sb_platdata *plat = dev_get_platdata(dev);
127 plat->mmio_base = dev_read_addr_pci(dev);
128 /* Don't set BDF since it should not be used */
129 if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
132 if (spl_phase() == PHASE_SPL)
133 return apl_p2sb_spl_init(dev);
139 static int p2sb_child_post_bind(struct udevice *dev)
141 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
142 struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
146 ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
155 static const struct udevice_id apl_p2sb_ids[] = {
156 { .compatible = "intel,apl-p2sb" },
160 U_BOOT_DRIVER(apl_p2sb_drv) = {
161 .name = "intel_apl_p2sb",
163 .of_match = apl_p2sb_ids,
164 .probe = apl_p2sb_probe,
165 .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata,
166 .platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
167 .per_child_platdata_auto_alloc_size =
168 sizeof(struct p2sb_child_platdata),
169 .child_post_bind = p2sb_child_post_bind,