arch/x86/cpu/intel_common/p2sb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Primary-to-Sideband Bridge
   4  *
   5  * Copyright 2019 Google LLC
   6  */
   7
   8 #define LOG_CATEGORY UCLASS_P2SB
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dt-structs.h>
  13 #include <log.h>
  14 #include <p2sb.h>
  15 #include <spl.h>
  16 #include <asm/p2sb.h>
  17 #include <asm/pci.h>
  18 #include <linux/bitops.h>
  19
  20 #define PCH_P2SB_E0             0xe0
  21 #define HIDE_BIT                BIT(0)
  22
  23 /* PCI config space registers */
  24 #define HPTC_OFFSET             0x60
  25 #define HPTC_ADDR_ENABLE_BIT    BIT(7)
  26
  27 /* High Performance Event Timer Configuration */
  28 #define P2SB_HPTC                               0x60
  29 #define P2SB_HPTC_ADDRESS_ENABLE                BIT(7)
  30
  31 /*
  32  * ADDRESS_SELECT            ENCODING_RANGE
  33  *      0                 0xfed0 0000 - 0xfed0 03ff
  34  *      1                 0xfed0 1000 - 0xfed0 13ff
  35  *      2                 0xfed0 2000 - 0xfed0 23ff
  36  *      3                 0xfed0 3000 - 0xfed0 33ff
  37  */
  38 #define P2SB_HPTC_ADDRESS_SELECT_0              (0 << 0)
  39 #define P2SB_HPTC_ADDRESS_SELECT_1              (1 << 0)
  40 #define P2SB_HPTC_ADDRESS_SELECT_2              (2 << 0)
  41 #define P2SB_HPTC_ADDRESS_SELECT_3              (3 << 0)
  42
  43 /*
  44  * p2sb_early_init() - Enable decoding for HPET range
  45  *
  46  * This is needed by FSP-M which uses the High Precision Event Timer.
  47  *
  48  * @dev: P2SB device
  49  * @return 0 if OK, -ve on error
  50  */
  51 static int p2sb_early_init(struct udevice *dev)
  52 {
  53         struct p2sb_plat *plat = dev_get_plat(dev);
  54         pci_dev_t pdev = plat->bdf;
  55
  56         /*
  57          * Enable decoding for HPET memory address range.
  58          * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
  59          * the High Performance Timer memory address range
  60          * selected by bits 1:0
  61          */
  62         pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
  63                              PCI_SIZE_8);
  64
  65         /* Enable PCR Base address in PCH */
  66         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
  67                              PCI_SIZE_32);
  68         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  69
  70         /* Enable P2SB MSE */
  71         pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
  72                              PCI_COMMAND_MEMORY, PCI_SIZE_8);
  73
  74         return 0;
  75 }
  76
  77 static int p2sb_spl_init(struct udevice *dev)
  78 {
  79         /* Enable decoding for HPET. Needed for FSP global pointer storage */
  80         dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
  81                             P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
  82
  83         return 0;
  84 }
  85
  86 int p2sb_of_to_plat(struct udevice *dev)
  87 {
  88         struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
  89         struct p2sb_plat *plat = dev_get_plat(dev);
  90
  91 #if CONFIG_IS_ENABLED(OF_REAL)
  92         int ret;
  93         u32 base[2];
  94
  95         ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
  96         if (ret)
  97                 return log_msg_ret("Missing/short early-regs", ret);
  98         plat->mmio_base = base[0];
  99         /* TPL sets up the initial BAR */
 100         if (spl_phase() == PHASE_TPL) {
 101                 plat->bdf = pci_get_devfn(dev);
 102                 if (plat->bdf < 0)
 103                         return log_msg_ret("Cannot get p2sb PCI address",
 104                                            plat->bdf);
 105         }
 106         upriv->mmio_base = plat->mmio_base;
 107 #else
 108         plat->mmio_base = plat->dtplat.early_regs[0];
 109         plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
 110         upriv->mmio_base = plat->mmio_base;
 111 #endif
 112
 113         return 0;
 114 }
 115
 116 static int p2sb_probe(struct udevice *dev)
 117 {
 118         if (spl_phase() == PHASE_TPL)
 119                 return p2sb_early_init(dev);
 120         else if (spl_phase() == PHASE_SPL)
 121                 return p2sb_spl_init(dev);
 122
 123         return 0;
 124 }
 125
 126 static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
 127 {
 128         dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
 129                               hide ? HIDE_BIT : 0);
 130 }
 131
 132 static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
 133 {
 134         u16 vendor;
 135
 136         if (!CONFIG_IS_ENABLED(PCI))
 137                 return -EPERM;
 138         p2sb_set_hide_bit(dev, hide);
 139
 140         dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
 141         if (hide && vendor != 0xffff)
 142                 return log_msg_ret("hide", -EEXIST);
 143         else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
 144                 return log_msg_ret("unhide", -ENOMEDIUM);
 145
 146         return 0;
 147 }
 148
 149 static int p2sb_remove(struct udevice *dev)
 150 {
 151         int ret;
 152
 153         ret = intel_p2sb_set_hide(dev, true);
 154         if (ret)
 155                 return log_msg_ret("hide", ret);
 156
 157         return 0;
 158 }
 159
 160 static int p2sb_child_post_bind(struct udevice *dev)
 161 {
 162         if (CONFIG_IS_ENABLED(OF_REAL)) {
 163                 struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
 164                 int ret;
 165                 u32 pid;
 166
 167                 ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
 168                 if (ret)
 169                         return ret;
 170                 pplat->pid = pid;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static const struct p2sb_ops p2sb_ops = {
 177         .set_hide       = intel_p2sb_set_hide,
 178 };
 179
 180 #if CONFIG_IS_ENABLED(OF_REAL)
 181 static const struct udevice_id p2sb_ids[] = {
 182         { .compatible = "intel,p2sb" },
 183         { }
 184 };
 185 #endif
 186
 187 U_BOOT_DRIVER(intel_p2sb) = {
 188         .name           = "intel_p2sb",
 189         .id             = UCLASS_P2SB,
 190         .of_match       = of_match_ptr(p2sb_ids),
 191         .probe          = p2sb_probe,
 192         .remove         = p2sb_remove,
 193         .ops            = &p2sb_ops,
 194         .of_to_plat = p2sb_of_to_plat,
 195         .plat_auto      = sizeof(struct p2sb_plat),
 196         .per_child_plat_auto    = sizeof(struct p2sb_child_plat),
 197         .child_post_bind = p2sb_child_post_bind,
 198         .flags          = DM_FLAG_OS_PREPARE,
 199 };