1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
27 #include <asm/control_regs.h>
28 #include <asm/coreboot_tables.h>
33 #include <asm/processor-flags.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 * Constructor for a conventional segment GDT (or LDT) entry
39 * This is a macro so it can be used in initialisers
41 #define GDT_ENTRY(flags, base, limit) \
42 ((((base) & 0xff000000ULL) << (56-24)) | \
43 (((flags) & 0x0000f0ffULL) << 40) | \
44 (((limit) & 0x000f0000ULL) << (48-16)) | \
45 (((base) & 0x00ffffffULL) << 16) | \
46 (((limit) & 0x0000ffffULL)))
53 struct cpu_device_id {
59 uint8_t x86; /* CPU family */
60 uint8_t x86_vendor; /* CPU vendor */
65 /* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
66 #ifndef CONFIG_TPL_BUILD
68 * List of cpu vendor strings along with their normalized
75 { X86_VENDOR_INTEL, "GenuineIntel", },
76 { X86_VENDOR_CYRIX, "CyrixInstead", },
77 { X86_VENDOR_AMD, "AuthenticAMD", },
78 { X86_VENDOR_UMC, "UMC UMC UMC ", },
79 { X86_VENDOR_NEXGEN, "NexGenDriven", },
80 { X86_VENDOR_CENTAUR, "CentaurHauls", },
81 { X86_VENDOR_RISE, "RiseRiseRise", },
82 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
83 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
84 { X86_VENDOR_NSC, "Geode by NSC", },
85 { X86_VENDOR_SIS, "SiS SiS SiS ", },
89 static void load_ds(u32 segment)
91 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
94 static void load_es(u32 segment)
96 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
99 static void load_fs(u32 segment)
101 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
104 static void load_gs(u32 segment)
106 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
109 static void load_ss(u32 segment)
111 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
114 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
118 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
119 gdt.ptr = (ulong)boot_gdt;
121 asm volatile("lgdtl %0\n" : : "m" (gdt));
124 void arch_setup_gd(gd_t *new_gd)
128 gdt_addr = new_gd->arch.gdt;
131 * CS: code, read/execute, 4 GB, base 0
133 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
135 gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
136 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
138 /* DS: data, read/write, 4 GB, base 0 */
139 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
142 * FS: data, read/write, sizeof (Global Data Pointer),
143 * base (Global Data Pointer)
145 new_gd->arch.gd_addr = new_gd;
146 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
147 (ulong)&new_gd->arch.gd_addr,
148 sizeof(new_gd->arch.gd_addr) - 1);
150 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
151 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
153 /* 16-bit DS: data, read/write, 64 kB, base 0 */
154 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
156 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
157 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
159 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
160 load_ds(X86_GDT_ENTRY_32BIT_DS);
161 load_es(X86_GDT_ENTRY_32BIT_DS);
162 load_gs(X86_GDT_ENTRY_32BIT_DS);
163 load_ss(X86_GDT_ENTRY_32BIT_DS);
164 load_fs(X86_GDT_ENTRY_32BIT_FS);
167 #ifdef CONFIG_HAVE_FSP
169 * Setup FSP execution environment GDT
171 * Per Intel FSP external architecture specification, before calling any FSP
172 * APIs, we need make sure the system is in flat 32-bit mode and both the code
173 * and data selectors should have full 4GB access range. Here we reuse the one
174 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
176 void setup_fsp_gdt(void)
178 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
179 load_ds(X86_GDT_ENTRY_32BIT_DS);
180 load_ss(X86_GDT_ENTRY_32BIT_DS);
181 load_es(X86_GDT_ENTRY_32BIT_DS);
182 load_fs(X86_GDT_ENTRY_32BIT_DS);
183 load_gs(X86_GDT_ENTRY_32BIT_DS);
188 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
189 * by the fact that they preserve the flags across the division of 5/2.
190 * PII and PPro exhibit this behavior too, but they have cpuid available.
194 * Perform the Cyrix 5/2 test. A Cyrix won't change
195 * the flags, while other 486 chips will.
197 static inline int test_cyrix_52div(void)
201 __asm__ __volatile__(
202 "sahf\n\t" /* clear flags (%eax = 0x0005) */
203 "div %b2\n\t" /* divide 5 by 2 */
204 "lahf" /* store flags into %ah */
209 /* AH is 0x02 on Cyrix after the divide.. */
210 return (unsigned char) (test >> 8) == 0x02;
213 #ifndef CONFIG_TPL_BUILD
215 * Detect a NexGen CPU running without BIOS hypercode new enough
216 * to have CPUID. (Thanks to Herbert Oppmann)
218 static int deep_magic_nexgen_probe(void)
222 __asm__ __volatile__ (
223 " movw $0x5555, %%ax\n"
231 : "=a" (ret) : : "cx", "dx");
236 static bool has_cpuid(void)
238 return flag_is_changeable_p(X86_EFLAGS_ID);
241 static bool has_mtrr(void)
243 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
246 #ifndef CONFIG_TPL_BUILD
247 static int build_vendor_name(char *vendor_name)
249 struct cpuid_result result;
250 result = cpuid(0x00000000);
251 unsigned int *name_as_ints = (unsigned int *)vendor_name;
253 name_as_ints[0] = result.ebx;
254 name_as_ints[1] = result.edx;
255 name_as_ints[2] = result.ecx;
261 static void identify_cpu(struct cpu_device_id *cpu)
263 cpu->device = 0; /* fix gcc 4.4.4 warning */
266 * Do a quick and dirty check to save space - Intel and AMD only and
267 * just the vendor. This is enough for most TPL code.
269 if (spl_phase() == PHASE_TPL) {
270 struct cpuid_result result;
272 result = cpuid(0x00000000);
273 switch (result.ecx >> 24) {
274 case 'l': /* GenuineIntel */
275 cpu->vendor = X86_VENDOR_INTEL;
277 case 'D': /* AuthenticAMD */
278 cpu->vendor = X86_VENDOR_AMD;
281 cpu->vendor = X86_VENDOR_ANY;
287 /* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
288 #ifndef CONFIG_TPL_BUILD
289 char vendor_name[16];
292 vendor_name[0] = '\0'; /* Unset */
294 /* Find the id and vendor_name */
296 /* Its a 486 if we can modify the AC flag */
297 if (flag_is_changeable_p(X86_EFLAGS_AC))
298 cpu->device = 0x00000400; /* 486 */
300 cpu->device = 0x00000300; /* 386 */
301 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
302 memcpy(vendor_name, "CyrixInstead", 13);
303 /* If we ever care we can enable cpuid here */
305 /* Detect NexGen with old hypercode */
306 else if (deep_magic_nexgen_probe())
307 memcpy(vendor_name, "NexGenDriven", 13);
311 cpuid_level = build_vendor_name(vendor_name);
312 vendor_name[12] = '\0';
314 /* Intel-defined flags: level 0x00000001 */
315 if (cpuid_level >= 0x00000001) {
316 cpu->device = cpuid_eax(0x00000001);
318 /* Have CPUID level 0 only unheard of */
319 cpu->device = 0x00000400;
322 cpu->vendor = X86_VENDOR_UNKNOWN;
323 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
324 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
325 cpu->vendor = x86_vendors[i].vendor;
332 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
334 c->x86 = (tfms >> 8) & 0xf;
335 c->x86_model = (tfms >> 4) & 0xf;
336 c->x86_mask = tfms & 0xf;
338 c->x86 += (tfms >> 20) & 0xff;
340 c->x86_model += ((tfms >> 16) & 0xF) << 4;
343 u32 cpu_get_family_model(void)
345 return gd->arch.x86_device & 0x0fff0ff0;
348 u32 cpu_get_stepping(void)
350 return gd->arch.x86_mask;
353 /* initialise FPU, reset EM, set MP and NE */
354 static void setup_cpu_features(void)
356 const u32 em_rst = ~X86_CR0_EM;
357 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
360 "movl %%cr0, %%eax\n" \
363 "movl %%eax, %%cr0\n" \
364 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
367 void cpu_reinit_fpu(void)
372 static void setup_identity(void)
374 /* identify CPU via cpuid and store the decoded info into gd->arch */
376 struct cpu_device_id cpu;
377 struct cpuinfo_x86 c;
380 get_fms(&c, cpu.device);
381 gd->arch.x86 = c.x86;
382 gd->arch.x86_vendor = cpu.vendor;
383 gd->arch.x86_model = c.x86_model;
384 gd->arch.x86_mask = c.x86_mask;
385 gd->arch.x86_device = cpu.device;
387 gd->arch.has_mtrr = has_mtrr();
391 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
392 static void setup_pci_ram_top(void)
394 gd->pci_ram_top = 0x80000000U;
397 static void setup_mtrr(void)
401 /* Configure fixed range MTRRs for some legacy regions */
402 if (!gd->arch.has_mtrr)
405 mtrr_cap = native_read_msr(MTRR_CAP_MSR);
406 if (mtrr_cap & MTRR_CAP_FIX) {
407 /* Mark the VGA RAM area as uncacheable */
408 native_write_msr(MTRR_FIX_16K_A0000_MSR,
409 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
410 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
413 * Mark the PCI ROM area as cacheable to improve ROM
414 * execution performance.
416 native_write_msr(MTRR_FIX_4K_C0000_MSR,
417 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
418 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
419 native_write_msr(MTRR_FIX_4K_C8000_MSR,
420 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
421 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
422 native_write_msr(MTRR_FIX_4K_D0000_MSR,
423 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
424 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
425 native_write_msr(MTRR_FIX_4K_D8000_MSR,
426 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
427 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
429 /* Enable the fixed range MTRRs */
430 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
434 int x86_cpu_init_tpl(void)
436 setup_cpu_features();
442 int x86_cpu_init_f(void)
445 setup_cpu_features();
450 /* Set up the i8254 timer if required */
451 if (IS_ENABLED(CONFIG_I8254_TIMER))
457 int x86_cpu_reinit_f(void)
463 addr = locate_coreboot_table();
465 gd->arch.coreboot_table = addr;
466 gd->flags |= GD_FLG_SKIP_LL_INIT;
472 void x86_enable_caches(void)
477 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
481 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
483 void x86_disable_caches(void)
488 cr0 |= X86_CR0_NW | X86_CR0_CD;
493 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
495 int dcache_status(void)
497 return !(read_cr0() & X86_CR0_CD);
500 void cpu_enable_paging_pae(ulong cr3)
502 __asm__ __volatile__(
503 /* Load the page table address */
506 "movl %%cr4, %%eax\n"
507 "orl $0x00000020, %%eax\n"
508 "movl %%eax, %%cr4\n"
510 "movl %%cr0, %%eax\n"
511 "orl $0x80000000, %%eax\n"
512 "movl %%eax, %%cr0\n"
518 void cpu_disable_paging_pae(void)
520 /* Turn off paging */
521 __asm__ __volatile__ (
523 "movl %%cr0, %%eax\n"
524 "andl $0x7fffffff, %%eax\n"
525 "movl %%eax, %%cr0\n"
527 "movl %%cr4, %%eax\n"
528 "andl $0xffffffdf, %%eax\n"
529 "movl %%eax, %%cr4\n"
535 static bool can_detect_long_mode(void)
537 return cpuid_eax(0x80000000) > 0x80000000UL;
540 static bool has_long_mode(void)
542 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
545 int cpu_has_64bit(void)
547 return has_cpuid() && can_detect_long_mode() &&
551 #define PAGETABLE_BASE 0x80000
552 #define PAGETABLE_SIZE (6 * 4096)
555 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
557 * @pgtable: Pointer to a 24iKB block of memory
559 static void build_pagetable(uint32_t *pgtable)
563 memset(pgtable, '\0', PAGETABLE_SIZE);
565 /* Level 4 needs a single entry */
566 pgtable[0] = (ulong)&pgtable[1024] + 7;
568 /* Level 3 has one 64-bit entry for each GiB of memory */
569 for (i = 0; i < 4; i++)
570 pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
572 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
573 for (i = 0; i < 2048; i++)
574 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
577 int cpu_jump_to_64bit(ulong setup_base, ulong target)
581 pgtable = memalign(4096, PAGETABLE_SIZE);
585 build_pagetable(pgtable);
586 cpu_call64((ulong)pgtable, setup_base, target);
593 * Jump from SPL to U-Boot
595 * This function is work-in-progress with many issues to resolve.
597 * It works by setting up several regions:
598 * ptr - a place to put the code that jumps into 64-bit mode
599 * gdt - a place to put the global descriptor table
600 * pgtable - a place to put the page tables
602 * The cpu_call64() code is copied from ROM and then manually patched so that
603 * it has the correct GDT address in RAM. U-Boot is copied from ROM into
604 * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
605 * which changes to 64-bit mode and starts U-Boot.
607 int cpu_jump_to_64bit_uboot(ulong target)
609 typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
614 pgtable = (uint32_t *)PAGETABLE_BASE;
616 build_pagetable(pgtable);
618 extern long call64_stub_size;
619 ptr = malloc(call64_stub_size);
621 printf("Failed to allocate the cpu_call64 stub\n");
624 memcpy(ptr, cpu_call64, call64_stub_size);
629 func((ulong)pgtable, 0, (ulong)target);
634 int x86_mp_init(void)
640 printf("Warning: MP init failure\n");