1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
27 #include <asm/acpi_s3.h>
28 #include <asm/acpi_table.h>
29 #include <asm/control_regs.h>
30 #include <asm/coreboot_tables.h>
32 #include <asm/lapic.h>
33 #include <asm/microcode.h>
35 #include <asm/mrccache.h>
39 #include <asm/processor.h>
40 #include <asm/processor-flags.h>
41 #include <asm/interrupt.h>
42 #include <asm/tables.h>
43 #include <linux/compiler.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 static const char *const x86_vendor_name[] = {
48 [X86_VENDOR_INTEL] = "Intel",
49 [X86_VENDOR_CYRIX] = "Cyrix",
50 [X86_VENDOR_AMD] = "AMD",
51 [X86_VENDOR_UMC] = "UMC",
52 [X86_VENDOR_NEXGEN] = "NexGen",
53 [X86_VENDOR_CENTAUR] = "Centaur",
54 [X86_VENDOR_RISE] = "Rise",
55 [X86_VENDOR_TRANSMETA] = "Transmeta",
56 [X86_VENDOR_NSC] = "NSC",
57 [X86_VENDOR_SIS] = "SiS",
60 int __weak x86_cleanup_before_linux(void)
62 #ifdef CONFIG_BOOTSTAGE_STASH
63 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
64 CONFIG_BOOTSTAGE_STASH_SIZE);
70 int x86_init_cache(void)
76 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
78 void flush_cache(unsigned long dummy1, unsigned long dummy2)
83 /* Define these functions to allow ehch-hcd to function */
84 void flush_dcache_range(unsigned long start, unsigned long stop)
88 void invalidate_dcache_range(unsigned long start, unsigned long stop)
92 void dcache_enable(void)
97 void dcache_disable(void)
102 void icache_enable(void)
106 void icache_disable(void)
110 int icache_status(void)
115 const char *cpu_vendor_name(int vendor)
118 name = "<invalid cpu vendor>";
119 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
120 x86_vendor_name[vendor])
121 name = x86_vendor_name[vendor];
126 char *cpu_get_name(char *name)
128 unsigned int *name_as_ints = (unsigned int *)name;
129 struct cpuid_result regs;
133 /* This bit adds up to 48 bytes */
134 for (i = 0; i < 3; i++) {
135 regs = cpuid(0x80000002 + i);
136 name_as_ints[i * 4 + 0] = regs.eax;
137 name_as_ints[i * 4 + 1] = regs.ebx;
138 name_as_ints[i * 4 + 2] = regs.ecx;
139 name_as_ints[i * 4 + 3] = regs.edx;
141 name[CPU_MAX_NAME_LEN - 1] = '\0';
143 /* Skip leading spaces. */
151 int default_print_cpuinfo(void)
153 printf("CPU: %s, vendor %s, device %xh\n",
154 cpu_has_64bit() ? "x86_64" : "x86",
155 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
157 #ifdef CONFIG_HAVE_ACPI_RESUME
158 debug("ACPI previous sleep state: %s\n",
159 acpi_ss_string(gd->arch.prev_sleep_state));
165 void show_boot_progress(int val)
167 outb(val, POST_PORT);
170 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
172 * Implement a weak default function for boards that optionally
173 * need to clean up the system before jumping to the kernel.
175 __weak void board_final_cleanup(void)
179 int last_stage_init(void)
181 board_final_cleanup();
183 #if CONFIG_HAVE_ACPI_RESUME
184 struct acpi_fadt *fadt = acpi_find_fadt();
186 if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3)
196 static int x86_init_cpus(void)
199 debug("Init additional CPUs\n");
205 * This causes the cpu-x86 driver to be probed.
206 * We don't check return value here as we want to allow boards
207 * which have not been converted to use cpu uclass driver to boot.
209 uclass_first_device(UCLASS_CPU, &dev);
223 ret = x86_init_cpus();
228 * Set up the northbridge, PCH and LPC if available. Note that these
229 * may have had some limited pre-relocation init if they were probed
230 * before relocation, but this is post relocation.
232 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
233 uclass_first_device(UCLASS_PCH, &dev);
234 uclass_first_device(UCLASS_LPC, &dev);
236 /* Set up pin control if available */
237 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
238 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
243 #ifndef CONFIG_EFI_STUB
244 int reserve_arch(void)
246 #ifdef CONFIG_ENABLE_MRC_CACHE
250 #ifdef CONFIG_SEABIOS
251 high_table_reserve();
254 #ifdef CONFIG_HAVE_ACPI_RESUME
257 #ifdef CONFIG_HAVE_FSP
259 * Save stack address to CMOS so that at next S3 boot,
260 * we can use it as the stack address for fsp_contiue()
263 #endif /* CONFIG_HAVE_FSP */
264 #endif /* CONFIG_HAVE_ACPI_RESUME */