1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
22 #include <bootstage.h>
30 #include <acpi/acpi_s3.h>
31 #include <acpi/acpi_table.h>
33 #include <asm/control_regs.h>
34 #include <asm/coreboot_tables.h>
36 #include <asm/lapic.h>
37 #include <asm/microcode.h>
39 #include <asm/mrccache.h>
43 #include <asm/processor.h>
44 #include <asm/processor-flags.h>
45 #include <asm/interrupt.h>
46 #include <asm/tables.h>
47 #include <linux/compiler.h>
49 DECLARE_GLOBAL_DATA_PTR;
51 #ifndef CONFIG_TPL_BUILD
52 static const char *const x86_vendor_name[] = {
53 [X86_VENDOR_INTEL] = "Intel",
54 [X86_VENDOR_CYRIX] = "Cyrix",
55 [X86_VENDOR_AMD] = "AMD",
56 [X86_VENDOR_UMC] = "UMC",
57 [X86_VENDOR_NEXGEN] = "NexGen",
58 [X86_VENDOR_CENTAUR] = "Centaur",
59 [X86_VENDOR_RISE] = "Rise",
60 [X86_VENDOR_TRANSMETA] = "Transmeta",
61 [X86_VENDOR_NSC] = "NSC",
62 [X86_VENDOR_SIS] = "SiS",
66 int __weak x86_cleanup_before_linux(void)
68 #ifdef CONFIG_BOOTSTAGE_STASH
69 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
70 CONFIG_BOOTSTAGE_STASH_SIZE);
76 int x86_init_cache(void)
82 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
84 void flush_cache(unsigned long dummy1, unsigned long dummy2)
89 /* Define these functions to allow ehch-hcd to function */
90 void flush_dcache_range(unsigned long start, unsigned long stop)
94 void invalidate_dcache_range(unsigned long start, unsigned long stop)
98 void dcache_enable(void)
103 void dcache_disable(void)
108 void icache_enable(void)
112 void icache_disable(void)
116 int icache_status(void)
121 #ifndef CONFIG_TPL_BUILD
122 const char *cpu_vendor_name(int vendor)
125 name = "<invalid cpu vendor>";
126 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
127 x86_vendor_name[vendor])
128 name = x86_vendor_name[vendor];
134 char *cpu_get_name(char *name)
136 unsigned int *name_as_ints = (unsigned int *)name;
137 struct cpuid_result regs;
141 /* This bit adds up to 48 bytes */
142 for (i = 0; i < 3; i++) {
143 regs = cpuid(0x80000002 + i);
144 name_as_ints[i * 4 + 0] = regs.eax;
145 name_as_ints[i * 4 + 1] = regs.ebx;
146 name_as_ints[i * 4 + 2] = regs.ecx;
147 name_as_ints[i * 4 + 3] = regs.edx;
149 name[CPU_MAX_NAME_LEN - 1] = '\0';
151 /* Skip leading spaces. */
159 int default_print_cpuinfo(void)
161 printf("CPU: %s, vendor %s, device %xh\n",
162 cpu_has_64bit() ? "x86_64" : "x86",
163 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
165 #ifdef CONFIG_HAVE_ACPI_RESUME
166 debug("ACPI previous sleep state: %s\n",
167 acpi_ss_string(gd->arch.prev_sleep_state));
173 void show_boot_progress(int val)
175 outb(val, POST_PORT);
178 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
180 * Implement a weak default function for boards that optionally
181 * need to clean up the system before jumping to the kernel.
183 __weak void board_final_cleanup(void)
187 int last_stage_init(void)
189 struct acpi_fadt __maybe_unused *fadt;
191 board_final_cleanup();
193 #ifdef CONFIG_HAVE_ACPI_RESUME
194 fadt = acpi_find_fadt();
196 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
202 #ifdef CONFIG_GENERATE_ACPI_TABLE
203 fadt = acpi_find_fadt();
205 /* Don't touch ACPI hardware on HW reduced platforms */
206 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
208 * Other than waiting for OSPM to request us to switch to ACPI
209 * mode, do it by ourselves, since SMI will not be triggered.
211 enter_acpi_mode(fadt->pm1a_cnt_blk);
219 static int x86_init_cpus(void)
222 debug("Init additional CPUs\n");
228 * This causes the cpu-x86 driver to be probed.
229 * We don't check return value here as we want to allow boards
230 * which have not been converted to use cpu uclass driver to boot.
232 uclass_first_device(UCLASS_CPU, &dev);
243 if (!ll_boot_init()) {
244 uclass_first_device(UCLASS_PCI, &dev);
248 ret = x86_init_cpus();
253 * Set up the northbridge, PCH and LPC if available. Note that these
254 * may have had some limited pre-relocation init if they were probed
255 * before relocation, but this is post relocation.
257 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
258 uclass_first_device(UCLASS_PCH, &dev);
259 uclass_first_device(UCLASS_LPC, &dev);
261 /* Set up pin control if available */
262 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
263 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
268 #ifndef CONFIG_EFI_STUB
269 int reserve_arch(void)
271 #ifdef CONFIG_ENABLE_MRC_CACHE
275 #ifdef CONFIG_SEABIOS
276 high_table_reserve();
279 #ifdef CONFIG_HAVE_ACPI_RESUME
282 #ifdef CONFIG_HAVE_FSP
284 * Save stack address to CMOS so that at next S3 boot,
285 * we can use it as the stack address for fsp_contiue()
288 #endif /* CONFIG_HAVE_FSP */
289 #endif /* CONFIG_HAVE_ACPI_RESUME */
295 long detect_coreboot_table_at(ulong start, ulong size)
300 for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
301 if (*ptr == 0x4f49424c) /* "LBIO" */
308 long locate_coreboot_table(void)
312 /* We look for LBIO in the first 4K of RAM and again at 960KB */
313 addr = detect_coreboot_table_at(0x0, 0x1000);
315 addr = detect_coreboot_table_at(0xf0000, 0x1000);