2 * Copyright (c) 2011 The Chromium OS Authors.
4 * Graeme Russ, graeme.russ@gmail.com.
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/sysinfo.h>
15 #include <asm/arch/timestamp.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int arch_cpu_init(void)
21 int ret = get_coreboot_info(&lib_sysinfo);
23 printf("Failed to parse coreboot tables.\n");
29 return x86_cpu_init_f();
32 int board_early_init_f(void)
37 int print_cpuinfo(void)
39 return default_print_cpuinfo();
42 int last_stage_init(void)
44 if (gd->flags & GD_FLG_COLD_BOOT)
45 timestamp_add_to_bootstage();
50 int board_eth_init(bd_t *bis)
52 return pci_eth_init(bis);
55 void board_final_cleanup(void)
58 * Un-cache the ROM so the kernel has one
59 * more MTRR available.
61 * Coreboot should have assigned this to the
62 * top available variable MTRR.
64 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
65 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
67 /* Make sure this MTRR is the correct Write-Protected type */
68 if (top_type == MTRR_TYPE_WRPROT) {
69 struct mtrr_state state;
72 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
73 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
77 /* Issue SMI to Coreboot to lock down ME and registers */
78 printf("Finalizing Coreboot\n");