1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * Graeme Russ, graeme.russ@gmail.com.
13 #include <asm/global_data.h>
17 #include <asm/cb_sysinfo.h>
18 #include <asm/arch/timestamp.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 int arch_cpu_init(void)
24 int ret = get_coreboot_info(&lib_sysinfo);
26 printf("Failed to parse coreboot tables.\n");
32 return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
41 int print_cpuinfo(void)
43 return default_print_cpuinfo();
46 static void board_final_init(void)
49 * Un-cache the ROM so the kernel has one
50 * more MTRR available.
52 * Coreboot should have assigned this to the
53 * top available variable MTRR.
55 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
56 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
58 /* Make sure this MTRR is the correct Write-Protected type */
59 if (top_type == MTRR_TYPE_WRPROT) {
60 struct mtrr_state state;
62 mtrr_open(&state, true);
63 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
64 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
65 mtrr_close(&state, true);
68 if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
70 * Issue SMI to coreboot to lock down ME and registers
71 * when allowed via device tree
73 printf("Finalizing coreboot\n");
78 int last_stage_init(void)
80 /* start usb so that usb keyboard can be used as input device */
81 if (CONFIG_IS_ENABLED(USB_KEYBOARD))