1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
5 * From coreboot src/soc/intel/broadwell/sata.c
13 #include <asm/intel_regs.h>
14 #include <asm/lpc_common.h>
15 #include <asm/pch_common.h>
16 #include <asm/pch_common.h>
17 #include <asm/arch/pch.h>
18 #include <linux/delay.h>
20 struct sata_platdata {
29 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
30 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
36 * 0: DEVSLP is enabled
37 * 1: DEVSLP is disabled
42 static void broadwell_sata_init(struct udevice *dev)
44 struct sata_platdata *plat = dev_get_platdata(dev);
50 debug("SATA: Initializing controller in AHCI mode.\n");
53 dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
54 dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
56 /* for AHCI, Port Enable is managed in memory mapped space */
57 dm_pci_read_config16(dev, 0x92, ®16);
59 reg16 |= 0x8000 | plat->port_map;
60 dm_pci_write_config16(dev, 0x92, reg16);
63 /* Setup register 98h */
64 dm_pci_read_config32(dev, 0x98, ®32);
65 reg32 &= ~((1 << 31) | (1 << 30));
67 reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
68 dm_pci_write_config32(dev, 0x98, reg32);
70 /* Setup register 9Ch */
71 reg16 = 0; /* Disable alternate ID */
72 reg16 = 1 << 5; /* BWG step 12 */
73 dm_pci_write_config16(dev, 0x9c, reg16);
75 /* SATA Initialization register */
77 reg32 |= (plat->port_map ^ 0xf) << 24;
78 reg32 |= (plat->devslp_mux & 1) << 15;
79 dm_pci_write_config32(dev, 0x94, reg32);
81 /* Initialize AHCI memory-mapped space */
82 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, ®32);
84 debug("ABAR: %p\n", abar);
86 /* CAP (HBA Capabilities) : enable power management */
87 clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
88 0x0c006000 /* PSC+SSC+SALP+SSS */ |
89 1 << 18); /* SAM: SATA AHCI MODE ONLY */
91 /* PI (Ports implemented) */
92 writel(plat->port_map, abar + 0x0c);
93 (void) readl(abar + 0x0c); /* Read back 1 */
94 (void) readl(abar + 0x0c); /* Read back 2 */
96 /* CAP2 (HBA Capabilities Extended)*/
97 if (plat->devslp_disable) {
98 clrbits_le32(abar + 0x24, 1 << 3);
101 setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
103 for (port = 0; port < 4; port++) {
104 if (!(plat->port_map & (1 << port)))
107 setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
111 /* Static Power Gating for unused ports */
112 reg32 = readl(RCB_REG(0x3a84));
113 /* Port 3 and 2 disabled */
114 if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
115 reg32 |= (1 << 24) | (1 << 26);
116 /* Port 1 and 0 disabled */
117 if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
118 reg32 |= (1 << 20) | (1 << 18);
119 writel(reg32, RCB_REG(0x3a84));
121 /* Set Gen3 Transmitter settings if needed */
122 if (plat->port0_gen3_tx)
123 pch_iobp_update(SATA_IOBP_SP0_SECRT88,
124 ~(SATA_SECRT88_VADJ_MASK <<
125 SATA_SECRT88_VADJ_SHIFT),
126 (plat->port0_gen3_tx &
127 SATA_SECRT88_VADJ_MASK)
128 << SATA_SECRT88_VADJ_SHIFT);
130 if (plat->port1_gen3_tx)
131 pch_iobp_update(SATA_IOBP_SP1_SECRT88,
132 ~(SATA_SECRT88_VADJ_MASK <<
133 SATA_SECRT88_VADJ_SHIFT),
134 (plat->port1_gen3_tx &
135 SATA_SECRT88_VADJ_MASK)
136 << SATA_SECRT88_VADJ_SHIFT);
138 /* Set Gen3 DTLE DATA / EDGE registers if needed */
139 if (plat->port0_gen3_dtle) {
140 pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
141 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
142 (plat->port0_gen3_dtle & SATA_DTLE_MASK)
143 << SATA_DTLE_DATA_SHIFT);
145 pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
146 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
147 (plat->port0_gen3_dtle & SATA_DTLE_MASK)
148 << SATA_DTLE_EDGE_SHIFT);
151 if (plat->port1_gen3_dtle) {
152 pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
153 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
154 (plat->port1_gen3_dtle & SATA_DTLE_MASK)
155 << SATA_DTLE_DATA_SHIFT);
157 pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
158 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
159 (plat->port1_gen3_dtle & SATA_DTLE_MASK)
160 << SATA_DTLE_EDGE_SHIFT);
164 * Additional Programming Requirements for Power Optimizer
168 pch_common_sir_write(dev, 0x64, 0x883c9003);
170 /* Step 2: SIR 68h[15:0] = 880Ah */
171 reg32 = pch_common_sir_read(dev, 0x68);
174 pch_common_sir_write(dev, 0x68, reg32);
176 /* Step 3: SIR 60h[3] = 1 */
177 reg32 = pch_common_sir_read(dev, 0x60);
179 pch_common_sir_write(dev, 0x60, reg32);
181 /* Step 4: SIR 60h[0] = 1 */
182 reg32 = pch_common_sir_read(dev, 0x60);
184 pch_common_sir_write(dev, 0x60, reg32);
186 /* Step 5: SIR 60h[1] = 1 */
187 reg32 = pch_common_sir_read(dev, 0x60);
189 pch_common_sir_write(dev, 0x60, reg32);
192 pch_common_sir_write(dev, 0x70, 0x3f00bf1f);
193 pch_common_sir_write(dev, 0x54, 0xcf000f0f);
194 pch_common_sir_write(dev, 0x58, 0x00190000);
195 clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
197 dm_pci_read_config32(dev, 0x300, ®32);
198 reg32 |= 1 << 17 | 1 << 16 | 1 << 19;
199 reg32 |= 1 << 31 | 1 << 30 | 1 << 29;
200 dm_pci_write_config32(dev, 0x300, reg32);
202 dm_pci_read_config32(dev, 0x98, ®32);
204 dm_pci_write_config32(dev, 0x98, reg32);
207 dm_pci_read_config32(dev, 0x9c, ®32);
209 dm_pci_write_config32(dev, 0x9c, reg32);
212 static int broadwell_sata_enable(struct udevice *dev)
214 struct sata_platdata *plat = dev_get_platdata(dev);
215 struct gpio_desc desc;
220 * Set SATA controller mode early so the resource allocator can
221 * properly assign IO/Memory resources for the controller.
225 map |= (plat->port_map ^ 0x3f) << 8;
226 dm_pci_write_config16(dev, 0x90, map);
228 ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT);
235 static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
237 struct sata_platdata *plat = dev_get_platdata(dev);
238 const void *blob = gd->fdt_blob;
239 int node = dev_of_offset(dev);
241 plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
242 plat->port0_gen3_tx = fdtdec_get_int(blob, node,
243 "intel,sata-port0-gen3-tx", 0);
248 static int broadwell_sata_probe(struct udevice *dev)
250 if (!(gd->flags & GD_FLG_RELOC))
251 return broadwell_sata_enable(dev);
253 broadwell_sata_init(dev);
258 static const struct udevice_id broadwell_ahci_ids[] = {
259 { .compatible = "intel,wildcatpoint-ahci" },
263 U_BOOT_DRIVER(ahci_broadwell_drv) = {
264 .name = "ahci_broadwell",
266 .of_match = broadwell_ahci_ids,
267 .ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
268 .probe = broadwell_sata_probe,
269 .platdata_auto = sizeof(struct sata_platdata),