1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
5 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
14 #include <asm/cpu_x86.h>
15 #include <asm/cpu_common.h>
16 #include <asm/intel_regs.h>
19 #include <asm/turbo.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/pch.h>
22 #include <asm/arch/rcb.h>
24 struct cpu_broadwell_priv {
28 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
29 static const u8 power_limit_time_sec_to_msr[] = {
57 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
58 static const u8 power_limit_time_msr_to_sec[] = {
86 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
87 int arch_cpu_init(void)
94 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
95 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
96 * when a core is woken up
98 static int pcode_ready(void)
101 const int delay_step = 10;
105 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
108 wait_count += delay_step;
110 } while (wait_count < 1000);
115 static u32 pcode_mailbox_read(u32 command)
121 debug("PCODE: mailbox timeout on wait ready\n");
125 /* Send command and start transaction */
126 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
130 debug("PCODE: mailbox timeout on completion\n");
135 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
138 static int pcode_mailbox_write(u32 command, u32 data)
144 debug("PCODE: mailbox timeout on wait ready\n");
148 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
150 /* Send command and start transaction */
151 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
155 debug("PCODE: mailbox timeout on completion\n");
162 /* @dev is the CPU device */
163 static void initialize_vr_config(struct udevice *dev)
168 debug("Initializing VR config\n");
170 /* Configure VR_CURRENT_CONFIG */
171 msr = msr_read(MSR_VR_CURRENT_CONFIG);
173 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
176 msr.hi &= 0xc0000000;
177 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
178 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
179 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
180 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
181 /* Leave the max instantaneous current limit (12:0) to default */
182 msr_write(MSR_VR_CURRENT_CONFIG, msr);
184 /* Configure VR_MISC_CONFIG MSR */
185 msr = msr_read(MSR_VR_MISC_CONFIG);
186 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
187 msr.hi &= ~(0x3ff << (40 - 32));
188 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
189 /* Set IOUT_OFFSET to 0 */
191 /* Set entry ramp rate to slow */
192 msr.hi &= ~(1 << (51 - 32));
193 /* Enable decay mode on C-state entry */
194 msr.hi |= (1 << (52 - 32));
195 /* Set the slow ramp rate */
196 msr.hi &= ~(0x3 << (53 - 32));
197 /* Configure the C-state exit ramp rate */
198 ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
199 "intel,slow-ramp", -1);
201 /* Configured slow ramp rate */
202 msr.hi |= ((ramp & 0x3) << (53 - 32));
203 /* Set exit ramp rate to slow */
204 msr.hi &= ~(1 << (50 - 32));
206 /* Fast ramp rate / 4 */
207 msr.hi |= (0x01 << (53 - 32));
208 /* Set exit ramp rate to fast */
209 msr.hi |= (1 << (50 - 32));
211 /* Set MIN_VID (31:24) to allow CPU to have full control */
212 msr.lo &= ~0xff000000;
213 min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
215 msr.lo |= (min_vid & 0xff) << 24;
216 msr_write(MSR_VR_MISC_CONFIG, msr);
218 /* Configure VR_MISC_CONFIG2 MSR */
219 msr = msr_read(MSR_VR_MISC_CONFIG2);
222 * Allow CPU to control minimum voltage completely (15:8) and
223 * set the fast ramp voltage in 10mV steps
225 if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
226 msr.lo |= 0x006a; /* 1.56V */
228 msr.lo |= 0x006f; /* 1.60V */
229 msr_write(MSR_VR_MISC_CONFIG2, msr);
231 /* Set C9/C10 VCC Min */
232 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
235 static int calibrate_24mhz_bclk(void)
244 /* A non-zero value initiates the PCODE calibration */
245 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
246 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
247 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
253 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
255 debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
257 /* Read the calibrated value */
258 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
259 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
265 debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
266 readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
271 static void configure_pch_power_sharing(void)
273 u32 pch_power, pch_power_ext, pmsync, pmsync2;
276 /* Read PCH Power levels from PCODE */
277 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
278 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
280 debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
283 pmsync = readl(RCB_REG(PMSYNC_CONFIG));
284 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
287 * Program PMSYNC_TPR_CONFIG PCH power limit values
288 * pmsync[0:4] = mailbox[0:5]
289 * pmsync[8:12] = mailbox[6:11]
290 * pmsync[16:20] = mailbox[12:17]
292 for (i = 0; i < 3; i++) {
293 u32 level = pch_power & 0x3f;
296 pmsync &= ~(0x1f << (i * 8));
297 pmsync |= (level & 0x1f) << (i * 8);
299 writel(pmsync, RCB_REG(PMSYNC_CONFIG));
302 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
303 * pmsync2[0:4] = mailbox[23:18]
304 * pmsync2[8:12] = mailbox_ext[6:11]
305 * pmsync2[16:20] = mailbox_ext[12:17]
306 * pmsync2[24:28] = mailbox_ext[18:22]
309 pmsync2 |= pch_power & 0x1f;
311 for (i = 1; i < 4; i++) {
312 u32 level = pch_power_ext & 0x3f;
315 pmsync2 &= ~(0x1f << (i * 8));
316 pmsync2 |= (level & 0x1f) << (i * 8);
318 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
321 static int bsp_init_before_ap_bringup(struct udevice *dev)
325 initialize_vr_config(dev);
326 ret = calibrate_24mhz_bclk();
329 configure_pch_power_sharing();
334 static void set_max_ratio(void)
340 /* Check for configurable TDP option */
341 if (turbo_get_state() == TURBO_ENABLED) {
342 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
343 perf_ctl.lo = (msr.lo & 0xff) << 8;
344 } else if (cpu_config_tdp_levels()) {
345 /* Set to nominal TDP ratio */
346 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
347 perf_ctl.lo = (msr.lo & 0xff) << 8;
349 /* Platform Info bits 15:8 give max ratio */
350 msr = msr_read(MSR_PLATFORM_INFO);
351 perf_ctl.lo = msr.lo & 0xff00;
353 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
355 debug("cpu: frequency set to %d\n",
356 ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
359 int broadwell_init(struct udevice *dev)
361 struct cpu_broadwell_priv *priv = dev_get_priv(dev);
367 msr = msr_read(CORE_THREAD_COUNT_MSR);
368 num_threads = (msr.lo >> 0) & 0xffff;
369 num_cores = (msr.lo >> 16) & 0xffff;
370 debug("CPU has %u cores, %u threads enabled\n", num_cores,
373 priv->ht_disabled = num_threads == num_cores;
375 ret = bsp_init_before_ap_bringup(dev);
384 static void configure_mca(void)
387 const unsigned int mcg_cap_msr = 0x179;
391 msr = msr_read(mcg_cap_msr);
392 num_banks = msr.lo & 0xff;
396 * TODO(adurbin): This should only be done on a cold boot. Also, some
397 * of these banks are core vs package scope. For now every CPU clears
400 for (i = 0; i < num_banks; i++)
401 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
404 static void enable_lapic_tpr(void)
408 msr = msr_read(MSR_PIC_MSG_CONTROL);
409 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
410 msr_write(MSR_PIC_MSG_CONTROL, msr);
413 static void configure_c_states(void)
417 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
418 msr.lo |= (1 << 31); /* Timed MWAIT Enable */
419 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
420 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
421 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
422 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
423 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
424 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
425 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
426 /* The deepest package c-state defaults to factory-configured value */
427 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
429 msr = msr_read(MSR_MISC_PWR_MGMT);
430 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
431 msr_write(MSR_MISC_PWR_MGMT, msr);
433 msr = msr_read(MSR_POWER_CTL);
434 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
435 msr.lo |= (1 << 1); /* C1E Enable */
436 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
437 msr_write(MSR_POWER_CTL, msr);
439 /* C-state Interrupt Response Latency Control 0 - package C3 latency */
441 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
442 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
444 /* C-state Interrupt Response Latency Control 1 */
446 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
447 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
449 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
451 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
452 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
454 /* C-state Interrupt Response Latency Control 3 - package C8 */
456 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
457 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
459 /* C-state Interrupt Response Latency Control 4 - package C9 */
461 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
462 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
464 /* C-state Interrupt Response Latency Control 5 - package C10 */
466 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
467 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
470 static void configure_misc(void)
474 msr = msr_read(MSR_IA32_MISC_ENABLE);
475 msr.lo |= MISC_ENABLE_FAST_STRING;
476 msr.lo |= MISC_ENABLE_TM1;
477 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
478 msr_write(MSR_IA32_MISC_ENABLE, msr);
480 /* Disable thermal interrupts */
483 msr_write(MSR_IA32_THERM_INTERRUPT, msr);
485 /* Enable package critical interrupt only */
488 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
491 static void configure_dca_cap(void)
493 struct cpuid_result cpuid_regs;
496 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
497 cpuid_regs = cpuid(1);
498 if (cpuid_regs.ecx & (1 << 18)) {
499 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
501 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
505 static void set_energy_perf_bias(u8 policy)
510 /* Determine if energy efficient policy is supported */
511 ecx = cpuid_ecx(0x6);
512 if (!(ecx & (1 << 3)))
515 /* Energy Policy is bits 3:0 */
516 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
518 msr.lo |= policy & 0xf;
519 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
521 debug("cpu: energy policy set to %u\n", policy);
524 /* All CPUs including BSP will run the following function */
525 static void cpu_core_init(struct udevice *dev)
527 /* Clear out pending MCEs */
530 /* Enable the local cpu apics */
533 /* Configure C States */
534 configure_c_states();
536 /* Configure Enhanced SpeedStep and Thermal Sensors */
539 /* Thermal throttle activation offset */
540 cpu_configure_thermal_target(dev);
542 /* Enable Direct Cache Access */
545 /* Set energy policy */
546 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
553 * Configure processor power limits if possible
554 * This must be done AFTER set of BIOS_RESET_CPL
556 void cpu_set_power_limits(int power_limit_1_time)
561 uint tdp, min_power, max_power, max_time;
562 u8 power_limit_1_val;
564 msr = msr_read(MSR_PLATFORM_INFO);
565 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
566 power_limit_1_time = 28;
568 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
572 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
573 power_unit = 2 << ((msr.lo & 0xf) - 1);
575 /* Get power defaults for this SKU */
576 msr = msr_read(MSR_PKG_POWER_SKU);
577 tdp = msr.lo & 0x7fff;
578 min_power = (msr.lo >> 16) & 0x7fff;
579 max_power = msr.hi & 0x7fff;
580 max_time = (msr.hi >> 16) & 0x7f;
582 debug("CPU TDP: %u Watts\n", tdp / power_unit);
584 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
585 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
587 if (min_power > 0 && tdp < min_power)
590 if (max_power > 0 && tdp > max_power)
593 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
595 /* Set long term power limit to TDP */
597 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
598 limit.lo |= PKG_POWER_LIMIT_EN;
599 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
600 PKG_POWER_LIMIT_TIME_SHIFT;
602 /* Set short term power limit to 1.25 * TDP */
604 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
605 limit.hi |= PKG_POWER_LIMIT_EN;
606 /* Power limit 2 time is only programmable on server SKU */
608 msr_write(MSR_PKG_POWER_LIMIT, limit);
610 /* Set power limit values in MCHBAR as well */
611 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
612 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
614 /* Set DDR RAPL power limit by copying from MMIO to MSR */
615 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
616 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
617 msr_write(MSR_DDR_RAPL_LIMIT, msr);
619 /* Use nominal TDP values for CPUs with configurable TDP */
620 if (cpu_config_tdp_levels()) {
621 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
623 limit.lo = msr.lo & 0xff;
624 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
628 static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
630 return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
633 static int broadwell_get_count(struct udevice *dev)
638 static int cpu_x86_broadwell_probe(struct udevice *dev)
642 return broadwell_init(dev);
648 static const struct cpu_ops cpu_x86_broadwell_ops = {
649 .get_desc = cpu_x86_get_desc,
650 .get_info = broadwell_get_info,
651 .get_count = broadwell_get_count,
652 .get_vendor = cpu_x86_get_vendor,
655 static const struct udevice_id cpu_x86_broadwell_ids[] = {
656 { .compatible = "intel,core-i3-gen5" },
660 U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
661 .name = "cpu_x86_broadwell",
663 .of_match = cpu_x86_broadwell_ids,
664 .bind = cpu_x86_bind,
665 .probe = cpu_x86_broadwell_probe,
666 .ops = &cpu_x86_broadwell_ops,
667 .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
668 .flags = DM_FLAG_PRE_RELOC,