1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
5 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
12 #include <asm/cpu_x86.h>
13 #include <asm/cpu_common.h>
14 #include <asm/intel_regs.h>
17 #include <asm/turbo.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/rcb.h>
22 struct cpu_broadwell_priv {
26 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
27 static const u8 power_limit_time_sec_to_msr[] = {
55 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
56 static const u8 power_limit_time_msr_to_sec[] = {
84 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
85 int arch_cpu_init(void)
92 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
93 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
94 * when a core is woken up
96 static int pcode_ready(void)
99 const int delay_step = 10;
103 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
106 wait_count += delay_step;
108 } while (wait_count < 1000);
113 static u32 pcode_mailbox_read(u32 command)
119 debug("PCODE: mailbox timeout on wait ready\n");
123 /* Send command and start transaction */
124 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
128 debug("PCODE: mailbox timeout on completion\n");
133 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
136 static int pcode_mailbox_write(u32 command, u32 data)
142 debug("PCODE: mailbox timeout on wait ready\n");
146 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
148 /* Send command and start transaction */
149 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
153 debug("PCODE: mailbox timeout on completion\n");
160 /* @dev is the CPU device */
161 static void initialize_vr_config(struct udevice *dev)
166 debug("Initializing VR config\n");
168 /* Configure VR_CURRENT_CONFIG */
169 msr = msr_read(MSR_VR_CURRENT_CONFIG);
171 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
174 msr.hi &= 0xc0000000;
175 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
176 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
177 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
178 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
179 /* Leave the max instantaneous current limit (12:0) to default */
180 msr_write(MSR_VR_CURRENT_CONFIG, msr);
182 /* Configure VR_MISC_CONFIG MSR */
183 msr = msr_read(MSR_VR_MISC_CONFIG);
184 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
185 msr.hi &= ~(0x3ff << (40 - 32));
186 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
187 /* Set IOUT_OFFSET to 0 */
189 /* Set entry ramp rate to slow */
190 msr.hi &= ~(1 << (51 - 32));
191 /* Enable decay mode on C-state entry */
192 msr.hi |= (1 << (52 - 32));
193 /* Set the slow ramp rate */
194 msr.hi &= ~(0x3 << (53 - 32));
195 /* Configure the C-state exit ramp rate */
196 ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
197 "intel,slow-ramp", -1);
199 /* Configured slow ramp rate */
200 msr.hi |= ((ramp & 0x3) << (53 - 32));
201 /* Set exit ramp rate to slow */
202 msr.hi &= ~(1 << (50 - 32));
204 /* Fast ramp rate / 4 */
205 msr.hi |= (0x01 << (53 - 32));
206 /* Set exit ramp rate to fast */
207 msr.hi |= (1 << (50 - 32));
209 /* Set MIN_VID (31:24) to allow CPU to have full control */
210 msr.lo &= ~0xff000000;
211 min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
213 msr.lo |= (min_vid & 0xff) << 24;
214 msr_write(MSR_VR_MISC_CONFIG, msr);
216 /* Configure VR_MISC_CONFIG2 MSR */
217 msr = msr_read(MSR_VR_MISC_CONFIG2);
220 * Allow CPU to control minimum voltage completely (15:8) and
221 * set the fast ramp voltage in 10mV steps
223 if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
224 msr.lo |= 0x006a; /* 1.56V */
226 msr.lo |= 0x006f; /* 1.60V */
227 msr_write(MSR_VR_MISC_CONFIG2, msr);
229 /* Set C9/C10 VCC Min */
230 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
233 static int calibrate_24mhz_bclk(void)
242 /* A non-zero value initiates the PCODE calibration */
243 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
244 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
245 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
251 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
253 debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
255 /* Read the calibrated value */
256 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
257 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
263 debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
264 readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
269 static void configure_pch_power_sharing(void)
271 u32 pch_power, pch_power_ext, pmsync, pmsync2;
274 /* Read PCH Power levels from PCODE */
275 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
276 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
278 debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
281 pmsync = readl(RCB_REG(PMSYNC_CONFIG));
282 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
285 * Program PMSYNC_TPR_CONFIG PCH power limit values
286 * pmsync[0:4] = mailbox[0:5]
287 * pmsync[8:12] = mailbox[6:11]
288 * pmsync[16:20] = mailbox[12:17]
290 for (i = 0; i < 3; i++) {
291 u32 level = pch_power & 0x3f;
294 pmsync &= ~(0x1f << (i * 8));
295 pmsync |= (level & 0x1f) << (i * 8);
297 writel(pmsync, RCB_REG(PMSYNC_CONFIG));
300 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
301 * pmsync2[0:4] = mailbox[23:18]
302 * pmsync2[8:12] = mailbox_ext[6:11]
303 * pmsync2[16:20] = mailbox_ext[12:17]
304 * pmsync2[24:28] = mailbox_ext[18:22]
307 pmsync2 |= pch_power & 0x1f;
309 for (i = 1; i < 4; i++) {
310 u32 level = pch_power_ext & 0x3f;
313 pmsync2 &= ~(0x1f << (i * 8));
314 pmsync2 |= (level & 0x1f) << (i * 8);
316 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
319 static int bsp_init_before_ap_bringup(struct udevice *dev)
323 initialize_vr_config(dev);
324 ret = calibrate_24mhz_bclk();
327 configure_pch_power_sharing();
332 static int cpu_config_tdp_levels(void)
336 /* Bits 34:33 indicate how many levels supported */
337 platform_info = msr_read(MSR_PLATFORM_INFO);
338 return (platform_info.hi >> 1) & 3;
341 static void set_max_ratio(void)
347 /* Check for configurable TDP option */
348 if (turbo_get_state() == TURBO_ENABLED) {
349 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
350 perf_ctl.lo = (msr.lo & 0xff) << 8;
351 } else if (cpu_config_tdp_levels()) {
352 /* Set to nominal TDP ratio */
353 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
354 perf_ctl.lo = (msr.lo & 0xff) << 8;
356 /* Platform Info bits 15:8 give max ratio */
357 msr = msr_read(MSR_PLATFORM_INFO);
358 perf_ctl.lo = msr.lo & 0xff00;
360 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
362 debug("cpu: frequency set to %d\n",
363 ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
366 int broadwell_init(struct udevice *dev)
368 struct cpu_broadwell_priv *priv = dev_get_priv(dev);
374 msr = msr_read(CORE_THREAD_COUNT_MSR);
375 num_threads = (msr.lo >> 0) & 0xffff;
376 num_cores = (msr.lo >> 16) & 0xffff;
377 debug("CPU has %u cores, %u threads enabled\n", num_cores,
380 priv->ht_disabled = num_threads == num_cores;
382 ret = bsp_init_before_ap_bringup(dev);
391 static void configure_mca(void)
394 const unsigned int mcg_cap_msr = 0x179;
398 msr = msr_read(mcg_cap_msr);
399 num_banks = msr.lo & 0xff;
403 * TODO(adurbin): This should only be done on a cold boot. Also, some
404 * of these banks are core vs package scope. For now every CPU clears
407 for (i = 0; i < num_banks; i++)
408 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
411 static void enable_lapic_tpr(void)
415 msr = msr_read(MSR_PIC_MSG_CONTROL);
416 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
417 msr_write(MSR_PIC_MSG_CONTROL, msr);
420 static void configure_c_states(void)
424 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
425 msr.lo |= (1 << 31); /* Timed MWAIT Enable */
426 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
427 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
428 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
429 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
430 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
431 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
432 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
433 /* The deepest package c-state defaults to factory-configured value */
434 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
436 msr = msr_read(MSR_MISC_PWR_MGMT);
437 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
438 msr_write(MSR_MISC_PWR_MGMT, msr);
440 msr = msr_read(MSR_POWER_CTL);
441 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
442 msr.lo |= (1 << 1); /* C1E Enable */
443 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
444 msr_write(MSR_POWER_CTL, msr);
446 /* C-state Interrupt Response Latency Control 0 - package C3 latency */
448 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
449 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
451 /* C-state Interrupt Response Latency Control 1 */
453 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
454 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
456 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
458 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
459 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
461 /* C-state Interrupt Response Latency Control 3 - package C8 */
463 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
464 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
466 /* C-state Interrupt Response Latency Control 4 - package C9 */
468 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
469 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
471 /* C-state Interrupt Response Latency Control 5 - package C10 */
473 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
474 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
477 static void configure_misc(void)
481 msr = msr_read(MSR_IA32_MISC_ENABLE);
482 msr.lo |= (1 << 0); /* Fast String enable */
483 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
484 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
485 msr_write(MSR_IA32_MISC_ENABLE, msr);
487 /* Disable thermal interrupts */
490 msr_write(MSR_IA32_THERM_INTERRUPT, msr);
492 /* Enable package critical interrupt only */
495 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
498 static void configure_dca_cap(void)
500 struct cpuid_result cpuid_regs;
503 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
504 cpuid_regs = cpuid(1);
505 if (cpuid_regs.ecx & (1 << 18)) {
506 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
508 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
512 static void set_energy_perf_bias(u8 policy)
517 /* Determine if energy efficient policy is supported */
518 ecx = cpuid_ecx(0x6);
519 if (!(ecx & (1 << 3)))
522 /* Energy Policy is bits 3:0 */
523 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
525 msr.lo |= policy & 0xf;
526 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
528 debug("cpu: energy policy set to %u\n", policy);
531 /* All CPUs including BSP will run the following function */
532 static void cpu_core_init(struct udevice *dev)
534 /* Clear out pending MCEs */
537 /* Enable the local cpu apics */
540 /* Configure C States */
541 configure_c_states();
543 /* Configure Enhanced SpeedStep and Thermal Sensors */
546 /* Thermal throttle activation offset */
547 cpu_configure_thermal_target(dev);
549 /* Enable Direct Cache Access */
552 /* Set energy policy */
553 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
560 * Configure processor power limits if possible
561 * This must be done AFTER set of BIOS_RESET_CPL
563 void cpu_set_power_limits(int power_limit_1_time)
568 uint tdp, min_power, max_power, max_time;
569 u8 power_limit_1_val;
571 msr = msr_read(MSR_PLATFORM_INFO);
572 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
573 power_limit_1_time = 28;
575 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
579 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
580 power_unit = 2 << ((msr.lo & 0xf) - 1);
582 /* Get power defaults for this SKU */
583 msr = msr_read(MSR_PKG_POWER_SKU);
584 tdp = msr.lo & 0x7fff;
585 min_power = (msr.lo >> 16) & 0x7fff;
586 max_power = msr.hi & 0x7fff;
587 max_time = (msr.hi >> 16) & 0x7f;
589 debug("CPU TDP: %u Watts\n", tdp / power_unit);
591 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
592 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
594 if (min_power > 0 && tdp < min_power)
597 if (max_power > 0 && tdp > max_power)
600 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
602 /* Set long term power limit to TDP */
604 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
605 limit.lo |= PKG_POWER_LIMIT_EN;
606 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
607 PKG_POWER_LIMIT_TIME_SHIFT;
609 /* Set short term power limit to 1.25 * TDP */
611 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
612 limit.hi |= PKG_POWER_LIMIT_EN;
613 /* Power limit 2 time is only programmable on server SKU */
615 msr_write(MSR_PKG_POWER_LIMIT, limit);
617 /* Set power limit values in MCHBAR as well */
618 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
619 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
621 /* Set DDR RAPL power limit by copying from MMIO to MSR */
622 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
623 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
624 msr_write(MSR_DDR_RAPL_LIMIT, msr);
626 /* Use nominal TDP values for CPUs with configurable TDP */
627 if (cpu_config_tdp_levels()) {
628 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
630 limit.lo = msr.lo & 0xff;
631 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
635 static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
637 return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
640 static int broadwell_get_count(struct udevice *dev)
645 static int cpu_x86_broadwell_probe(struct udevice *dev)
649 return broadwell_init(dev);
655 static const struct cpu_ops cpu_x86_broadwell_ops = {
656 .get_desc = cpu_x86_get_desc,
657 .get_info = broadwell_get_info,
658 .get_count = broadwell_get_count,
659 .get_vendor = cpu_x86_get_vendor,
662 static const struct udevice_id cpu_x86_broadwell_ids[] = {
663 { .compatible = "intel,core-i3-gen5" },
667 U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
668 .name = "cpu_x86_broadwell",
670 .of_match = cpu_x86_broadwell_ids,
671 .bind = cpu_x86_bind,
672 .probe = cpu_x86_broadwell_probe,
673 .ops = &cpu_x86_broadwell_ops,
674 .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
675 .flags = DM_FLAG_PRE_RELOC,