arch/x86/cpu/broadwell/adsp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Support for Intel Application Digital Signal Processor
   4  *
   5  * Copyright 2019 Google LLC
   6  *
   7  * Modified from coreboot file of the same name
   8  */
   9
  10 #define LOG_CATEGORY UCLASS_SYSCON
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <pci.h>
  15 #include <asm/io.h>
  16 #include <asm/cpu.h>
  17 #include <asm/intel_regs.h>
  18 #include <asm/arch/adsp.h>
  19 #include <asm/arch/pch.h>
  20 #include <asm/arch/rcb.h>
  21
  22 enum pci_type_t {
  23         LYNX_POINT,
  24         WILDCAT_POINT,
  25 };
  26
  27 struct broadwell_adsp_priv {
  28         bool adsp_d3_pg_enable;
  29         bool adsp_sram_pg_enable;
  30         bool sio_acpi_mode;
  31 };
  32
  33 static int broadwell_adsp_probe(struct udevice *dev)
  34 {
  35         struct broadwell_adsp_priv *priv = dev_get_priv(dev);
  36         enum pci_type_t type;
  37         u32 bar0, bar1;
  38         u32 tmp32;
  39
  40         /* Find BAR0 and BAR1 */
  41         bar0 = dm_pci_read_bar32(dev, 0);
  42         if (!bar0)
  43                 return -EINVAL;
  44         bar1 = dm_pci_read_bar32(dev, 1);
  45         if (!bar1)
  46                 return -EINVAL;
  47
  48         /*
  49          * Set LTR value in DSP shim LTR control register to 3ms
  50          * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
  51          */
  52         type = dev_get_driver_data(dev);
  53         tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
  54         writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
  55
  56         /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
  57         dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
  58
  59         /* Program ADSP IOBP VDLDAT1 to 0x040100 */
  60         pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
  61
  62         /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
  63         dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
  64         if (type == WILDCAT_POINT) {
  65                 if (priv->adsp_d3_pg_enable) {
  66                         tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
  67                         if (priv->adsp_sram_pg_enable)
  68                                 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
  69                         else
  70                                 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
  71                 } else {
  72                         tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
  73                 }
  74         } else {
  75                 if (priv->adsp_d3_pg_enable) {
  76                         tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
  77                         if (priv->adsp_sram_pg_enable)
  78                                 tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
  79                         else
  80                                 tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
  81                 } else {
  82                         tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
  83                 }
  84         }
  85         dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
  86
  87         /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
  88         setbits_le32(RCB_REG(0x3350), 1 << 10);
  89
  90         /* Set DSP IOBP PMCTL 0x1e0=0x3f */
  91         pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
  92
  93         if (priv->sio_acpi_mode) {
  94                 /* Configure for ACPI mode */
  95                 log_info("ADSP: Enable ACPI Mode IRQ3\n");
  96
  97                 /* Set interrupt de-assert/assert opcode override to IRQ3 */
  98                 pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
  99
 100                 /* Enable IRQ3 in RCBA */
 101                 setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
 102
 103                 /* Set ACPI Interrupt Enable Bit */
 104                 pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
 105                                 ADSP_PCICFGCTL_ACPIIE);
 106
 107                 /* Put ADSP in D3hot */
 108                 clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
 109         } else {
 110                 log_info("ADSP: Enable PCI Mode IRQ23\n");
 111
 112                 /* Configure for PCI mode */
 113                 dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
 114
 115                 /* Clear ACPI Interrupt Enable Bit */
 116                 pch_iobp_update(ADSP_IOBP_PCICFGCTL,
 117                                 ~(ADSP_PCICFGCTL_SPCBAD |
 118                                  ADSP_PCICFGCTL_ACPIIE), 0);
 119         }
 120
 121         return 0;
 122 }
 123
 124 static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
 125 {
 126         struct broadwell_adsp_priv *priv = dev_get_priv(dev);
 127
 128         priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
 129         priv->adsp_sram_pg_enable = dev_read_bool(dev,
 130                                                   "intel,adsp-sram-pg-enable");
 131         priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
 132
 133         return 0;
 134 }
 135
 136 static const struct udevice_id broadwell_adsp_ids[] = {
 137         { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
 138         { }
 139 };
 140
 141 U_BOOT_DRIVER(broadwell_adsp_drv) = {
 142         .name           = "adsp",
 143         .id             = UCLASS_SYSCON,
 144         .ofdata_to_platdata     = broadwell_adsp_ofdata_to_platdata,
 145         .of_match       = broadwell_adsp_ids,
 146         .bind           = dm_scan_fdt_dev,
 147         .probe          = broadwell_adsp_probe,
 148 };
 149
 150 static struct pci_device_id broadwell_adsp_supported[] = {
 151         { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
 152                 PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
 153         { },
 154 };
 155
 156 U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);