dm: core: Create a new header file for 'compat' features
[platform/kernel/u-boot.git] / arch / x86 / cpu / apollolake / spl.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2019 Google LLC
4  */
5
6 #include <common.h>
7 #include <binman_sym.h>
8 #include <dm.h>
9 #include <malloc.h>
10 #include <spi.h>
11 #include <spl.h>
12 #include <spi_flash.h>
13 #include <asm/fast_spi.h>
14 #include <asm/spl.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/iomap.h>
17 #include <dm/device-internal.h>
18 #include <dm/uclass-internal.h>
19
20 /* This reads the next phase from mapped SPI flash */
21 static int rom_load_image(struct spl_image_info *spl_image,
22                           struct spl_boot_device *bootdev)
23 {
24         ulong spl_pos = spl_get_image_pos();
25         ulong spl_size = spl_get_image_size();
26         struct udevice *dev;
27         ulong map_base;
28         size_t map_size;
29         uint offset;
30         int ret;
31
32         spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
33         spl_image->entry_point = spl_phase() == PHASE_TPL ?
34                 CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
35         spl_image->load_addr = spl_image->entry_point;
36         spl_image->os = IH_OS_U_BOOT;
37         spl_image->name = "U-Boot";
38         debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
39
40         if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
41                 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
42                 if (ret)
43                         return log_msg_ret("spi_flash", ret);
44                 if (!dev)
45                         return log_msg_ret("spi_flash dev", -ENODEV);
46                 ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
47                 if (ret)
48                         return log_msg_ret("mmap", ret);
49         } else {
50                 ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
51                                              &offset);
52                 if (ret)
53                         return ret;
54         }
55         spl_pos += map_base & ~0xff000000;
56         debug(", base %lx, pos %lx\n", map_base, spl_pos);
57         bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
58         memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
59         cpu_flush_l1d_to_l2();
60         bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
61
62         return 0;
63 }
64 SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
65
66 #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
67
68 static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
69                               void *buf)
70 {
71         struct spi_flash *flash = dev_get_uclass_priv(dev);
72         struct mtd_info *mtd = &flash->mtd;
73         size_t retlen;
74
75         return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
76 }
77
78 static int apl_flash_probe(struct udevice *dev)
79 {
80         return spi_flash_std_probe(dev);
81 }
82
83 /*
84  * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
85  * need to allocate the parent_platdata since by the time this function is
86  * called device_bind() has already gone past that step.
87  */
88 static int apl_flash_bind(struct udevice *dev)
89 {
90         if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
91                 struct dm_spi_slave_platdata *plat;
92                 struct udevice *spi;
93                 int ret;
94
95                 ret = uclass_first_device_err(UCLASS_SPI, &spi);
96                 if (ret)
97                         return ret;
98                 dev->parent = spi;
99
100                 plat = calloc(sizeof(*plat), 1);
101                 if (!plat)
102                         return -ENOMEM;
103                 dev->parent_platdata = plat;
104         }
105
106         return 0;
107 }
108
109 static const struct dm_spi_flash_ops apl_flash_ops = {
110         .read           = apl_flash_std_read,
111 };
112
113 static const struct udevice_id apl_flash_ids[] = {
114         { .compatible = "jedec,spi-nor" },
115         { }
116 };
117
118 U_BOOT_DRIVER(winbond_w25q128fw) = {
119         .name           = "winbond_w25q128fw",
120         .id             = UCLASS_SPI_FLASH,
121         .of_match       = apl_flash_ids,
122         .bind           = apl_flash_bind,
123         .probe          = apl_flash_probe,
124         .priv_auto_alloc_size = sizeof(struct spi_flash),
125         .ops            = &apl_flash_ops,
126 };
127
128 /* This uses a SPI flash device to read the next phase */
129 static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
130                                    struct spl_boot_device *bootdev)
131 {
132         ulong spl_pos = spl_get_image_pos();
133         ulong spl_size = spl_get_image_size();
134         struct udevice *dev;
135         int ret;
136
137         ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
138         if (ret)
139                 return ret;
140
141         spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
142         spl_image->entry_point = spl_phase() == PHASE_TPL ?
143                 CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
144         spl_image->load_addr = spl_image->entry_point;
145         spl_image->os = IH_OS_U_BOOT;
146         spl_image->name = "U-Boot";
147         spl_pos &= ~0xff000000;
148         debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
149         ret = spi_flash_read_dm(dev, spl_pos, spl_size,
150                                 (void *)spl_image->load_addr);
151         cpu_flush_l1d_to_l2();
152         if (ret)
153                 return ret;
154
155         return 0;
156 }
157 SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
158                       spl_fast_spi_load_image);
159
160 void board_boot_order(u32 *spl_boot_list)
161 {
162         bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
163
164         if (use_spi_flash) {
165                 spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
166                 spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
167         } else {
168                 spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
169                 spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
170         }
171 }
172
173 #else
174
175 void board_boot_order(u32 *spl_boot_list)
176 {
177         spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
178 }
179 #endif