1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
16 #include <acpi/acpi_s3.h>
17 #include <asm/intel_pinctrl.h>
19 #include <asm/intel_regs.h>
21 #include <asm/msr-index.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/systemagent.h>
25 #include <asm/arch/fsp_bindings.h>
26 #include <asm/arch/fsp/fsp_configs.h>
27 #include <asm/arch/fsp/fsp_s_upd.h>
28 #include <dm/uclass-internal.h>
29 #include <linux/bitops.h>
31 #define PCH_P2SB_E0 0xe0
32 #define HIDE_BIT BIT(0)
34 int fsps_update_config(struct udevice *dev, ulong rom_offset,
37 struct fsp_s_config *cfg = &upd->config;
40 if (IS_ENABLED(CONFIG_HAVE_VBT)) {
44 ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL);
46 return log_msg_ret("Cannot find VBT", ret);
47 if (*(u32 *)buf != VBT_SIGNATURE)
48 return log_msg_ret("VBT signature", -EINVAL);
51 * Load VBT before devicetree-specific config. This only
52 * supports memory-mapped SPI at present.
54 cfg->graphics_config_ptr = (ulong)buf;
57 node = dev_read_subnode(dev, "fsp-s");
58 if (!ofnode_valid(node))
59 return log_msg_ret("fsp-s settings", -ENOENT);
61 return fsp_s_update_config_from_dtb(node, cfg);
64 /* Configure package power limits */
65 static int set_power_limits(struct udevice *dev)
67 msr_t rapl_msr_reg, limit;
69 u32 tdp, min_power, max_power;
75 rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
76 power_unit = 1 << (rapl_msr_reg.lo & 0xf);
78 /* Get power defaults for this SKU */
79 rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
80 tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
81 pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
82 min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
83 max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
85 if (min_power > 0 && tdp < min_power)
88 if (max_power > 0 && tdp > max_power)
91 ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
92 ARRAY_SIZE(override_tdp));
94 return log_msg_ret("tdp-pl-override-mw", ret);
96 /* Set PL1 override value */
98 tdp = override_tdp[0] * power_unit / 1000;
100 /* Set PL2 override value */
102 pl2_val = override_tdp[1] * power_unit / 1000;
104 /* Set long term power limit to TDP */
105 limit.lo = tdp & PKG_POWER_LIMIT_MASK;
106 /* Set PL1 Pkg Power clamp bit */
107 limit.lo |= PKG_POWER_LIMIT_CLAMP;
109 limit.lo |= PKG_POWER_LIMIT_EN;
110 limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
111 PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
113 /* Set short term power limit PL2 */
114 limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
115 limit.hi |= PKG_POWER_LIMIT_EN;
117 /* Program package power limits in RAPL MSR */
118 msr_write(MSR_PKG_POWER_LIMIT, limit);
119 log_debug("RAPL PL1 %d.%dW\n", tdp / power_unit,
120 100 * (tdp % power_unit) / power_unit);
121 log_debug("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
122 100 * (pl2_val % power_unit) / power_unit);
125 * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
126 * instead of MMIO, so disable LIMIT_EN bit for MMIO
128 writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
129 writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
134 int p2sb_unhide(void)
139 ret = uclass_find_first_device(UCLASS_P2SB, &dev);
141 return log_msg_ret("p2sb", ret);
142 ret = p2sb_set_hide(dev, false);
144 return log_msg_ret("hide", ret);
149 /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
150 static void set_sci_irq(void)
152 /* Skip this for now */
155 int arch_fsps_preinit(void)
157 struct udevice *itss;
162 ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
164 return log_msg_ret("no itss", ret);
167 * Clear the GPI interrupt status and enable registers. These
168 * registers do not get reset to default state when booting from S5.
170 ret = pinctrl_gpi_clear_int_cfg();
172 return log_msg_ret("gpi_clear", ret);
177 int arch_fsp_init_r(void)
180 struct udevice *dev, *itss;
186 s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
187 gd->arch.prev_sleep_state == ACPI_S3;
190 * This must be called before any devices are probed. Put any probing
191 * into arch_fsps_preinit() above.
193 * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
194 * force PCI to be probed.
196 ret = fsp_silicon_init(s3wake, false);
200 ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
202 return log_msg_ret("no itss", ret);
205 * Restore GPIO IRQ polarities back to previous settings. This was
206 * stored in reserve_arch() - see X86_IRQT_ITSS
208 irq_restore_polarities(itss);
213 return log_msg_ret("unhide p2sb", ret);
215 /* Set RAPL MSR for Package power limits*/
216 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
218 return log_msg_ret("Cannot get northbridge", ret);
219 set_power_limits(dev);
222 * FSP-S routes SCI to IRQ 9. With the help of this function you can
223 * select another IRQ for SCI.