1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
10 #include <asm/arch/iomap.h>
11 #include <asm/arch/fsp_bindings.h>
12 #include <asm/fsp2/fsp_internal.h>
13 #include <dm/uclass-internal.h>
15 int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
17 struct fsp_m_config *cfg = &upd->config;
18 struct fspm_arch_upd *arch = &upd->arch;
23 arch->nvs_buffer_ptr = NULL;
24 cache_ret = prepare_mrc_cache(upd);
25 if (cache_ret && cache_ret != -ENOENT)
26 return log_msg_ret("mrc", cache_ret);
27 arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
29 arch->boot_loader_tolum_size = 0;
30 arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
31 FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
33 node = dev_ofnode(dev);
34 if (!ofnode_valid(node))
35 return log_msg_ret("fsp-m settings", -ENOENT);
37 ret = fsp_m_update_config_from_dtb(node, cfg);
39 return log_msg_ret("dtb", cache_ret);
45 * The FSP-M binary appears to break the SPI controller. It can be fixed by
46 * writing the BAR again, so do that here
48 int fspm_done(struct udevice *dev)
53 /* Don't probe the device, since that reads the BAR */
54 ret = uclass_find_first_device(UCLASS_SPI, &spi);
56 return log_msg_ret("SPI", ret);
58 return log_msg_ret("no SPI", -ENODEV);
60 dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
61 IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);