1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
5 * Portions taken from coreboot
10 #include <ec_commands.h>
13 #include <spi_flash.h>
16 #include <acpi/acpi_s3.h>
18 #include <asm/cpu_common.h>
19 #include <asm/cpu_x86.h>
20 #include <asm/fast_spi.h>
21 #include <asm/intel_pinctrl.h>
22 #include <asm/intel_regs.h>
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/iomap.h>
30 #include <asm/arch/lpc.h>
31 #include <asm/arch/pch.h>
32 #include <asm/arch/systemagent.h>
33 #include <asm/arch/uart.h>
34 #include <asm/fsp2/fsp_api.h>
35 #include <linux/sizes.h>
36 #include <power/acpi_pmc.h>
38 /* Define this here to avoid referencing any drivers for the debug UART 1 */
39 #define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
41 static void pch_uart_init(void)
44 * Set up the pinmux so that the UART rx/tx signals are connected
47 * There are about 500 lines of code required to program the GPIO
48 * configuration for the UARTs. But it boils down to four writes, and
49 * for the debug UART we want the minimum possible amount of code before
50 * the UART is running. So just add the magic writes here. See
51 * apl_hostbridge_early_init_pinctrl() for the full horror.
53 if (PCI_FUNC(PCH_DEV_UART) == 1) {
54 writel(0x40000402, 0xd0c50650);
55 writel(0x3c47, 0xd0c50654);
56 writel(0x40000400, 0xd0c50658);
57 writel(0x3c48, 0xd0c5065c);
59 writel(0x40000402, 0xd0c50670);
60 writel(0x3c4b, 0xd0c50674);
61 writel(0x40000400, 0xd0c50678);
62 writel(0x3c4c, 0xd0c5067c);
65 #ifdef CONFIG_DEBUG_UART
66 apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
70 static void p2sb_enable_bar(ulong bar)
72 /* Enable PCR Base address in PCH */
73 pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
75 pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
78 pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
79 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
84 * board_debug_uart_init() - Init the debug UART ready for use
86 * This is the minimum init needed to get the UART running. It avoids any
87 * drivers or complex code, so that the UART is running as soon as possible.
89 void board_debug_uart_init(void)
91 p2sb_enable_bar(IOMAP_P2SB_BAR);
95 static int fast_spi_cache_bios_region(void)
97 uint map_size, offset;
101 ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE);
103 return log_msg_ret("early_init", ret);
105 ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
108 return log_msg_ret("get_mmap", ret);
110 base = SZ_4G - map_size;
111 mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
112 log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
117 static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
122 if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
126 base = EC_HOST_CMD_REGION0;
127 size = 2 * EC_HOST_CMD_REGION_SIZE;
128 /* Make sure MEMMAP region follows host cmd region */
129 assert(base + size == EC_LPC_ADDR_MEMMAP);
130 size += EC_MEMMAP_SIZE;
137 static void early_ec_init(void)
142 * Set up LPC decoding for the Chrome OS EC I/O port ranges:
143 * - Ports 62/66, 60/64, and 200->208
144 * - Chrome OS EC communication I/O ports
146 lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 |
148 google_chromeec_ioport_range(&base, &size);
149 lpc_open_pmio_window(base, size);
152 static int arch_cpu_init_tpl(void)
154 struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc;
157 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
159 return log_msg_ret("PMC", ret);
161 /* Clear global reset promotion bit */
162 ret = pmc_global_reset_set_enable(pmc, false);
164 return log_msg_ret("disable global reset", ret);
166 enable_pm_timer_emulation(pmc);
168 ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
170 return log_msg_ret("p2sb", ret);
171 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa);
173 return log_msg_ret("northbridge", ret);
174 gd->baudrate = CONFIG_BAUDRATE;
175 ret = uclass_first_device_err(UCLASS_SERIAL, &serial);
177 return log_msg_ret("serial", ret);
178 if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
179 ret = uclass_first_device_err(UCLASS_SPI, &spi);
181 return log_msg_ret("SPI", ret);
183 /* Alternative code if we don't have SPI in TPL */
184 if (IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH))
185 printf("Warning: Enable APL_SPI_FLASHBOOT to use SPI-flash driver in TPL");
186 ret = fast_spi_cache_bios_region();
188 return log_msg_ret("BIOS cache", ret);
190 ret = pmc_disable_tco(pmc);
192 return log_msg_ret("disable TCO", ret);
193 ret = pmc_gpe_init(pmc);
195 return log_msg_ret("pmc_gpe", ret);
196 ret = uclass_first_device_err(UCLASS_LPC, &lpc);
198 return log_msg_ret("lpc", ret);
206 * Enables several BARs and devices which are needed for memory init
207 * - MCH_BASE_ADDR is needed in order to talk to the memory controller
208 * - HPET is enabled because FSP wants to store a pointer to global data in the
209 * HPET comparator register
211 static int arch_cpu_init_spl(void)
213 struct udevice *pmc, *p2sb;
216 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
218 return log_msg_ret("Could not probe PMC", ret);
219 ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
221 return log_msg_ret("Cannot set up p2sb", ret);
223 lpc_io_setup_comm_a_b();
225 /* TODO(sjg@chromium.org): Enable upper RTC bank here */
229 return log_msg_ret("Could not init PMC", ret);
230 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
231 ret = pmc_prev_sleep_state(pmc);
233 return log_msg_ret("Could not get PMC sleep state",
235 gd->arch.prev_sleep_state = ret;
241 int arch_cpu_init(void)
245 if (spl_phase() == PHASE_TPL)
246 ret = arch_cpu_init_tpl();
247 else if (spl_phase() == PHASE_SPL)
248 ret = arch_cpu_init_spl();
250 printf("%s: Error %d\n", __func__, ret);