arch/x86/cpu/apollolake/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Google LLC
   4  */
   5
   6 #include <common.h>
   7 #include <cpu.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <acpi/acpigen.h>
  11 #include <acpi/acpi_table.h>
  12 #include <asm/cpu_common.h>
  13 #include <asm/cpu_x86.h>
  14 #include <asm/intel_acpi.h>
  15 #include <asm/msr.h>
  16 #include <asm/mtrr.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/iomap.h>
  19 #include <dm/acpi.h>
  20
  21 #define CSTATE_RES(address_space, width, offset, address)               \
  22         {                                                               \
  23         .space_id = address_space,                                      \
  24         .bit_width = width,                                             \
  25         .bit_offset = offset,                                           \
  26         .addrl = address,                                               \
  27         }
  28
  29 static struct acpi_cstate cstate_map[] = {
  30         {
  31                 /* C1 */
  32                 .ctype = 1,             /* ACPI C1 */
  33                 .latency = 1,
  34                 .power = 1000,
  35                 .resource = {
  36                         .space_id = ACPI_ADDRESS_SPACE_FIXED,
  37                 },
  38         }, {
  39                 .ctype = 2,             /* ACPI C2 */
  40                 .latency = 50,
  41                 .power = 10,
  42                 .resource = {
  43                         .space_id = ACPI_ADDRESS_SPACE_IO,
  44                         .bit_width = 8,
  45                         .addrl = 0x415,
  46                 },
  47         }, {
  48                 .ctype = 3,             /* ACPI C3 */
  49                 .latency = 150,
  50                 .power = 10,
  51                 .resource = {
  52                         .space_id = ACPI_ADDRESS_SPACE_IO,
  53                         .bit_width = 8,
  54                         .addrl = 0x419,
  55                 },
  56         },
  57 };
  58
  59 static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
  60 {
  61         return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
  62 }
  63
  64 static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
  65 {
  66         uint core_id = dev->req_seq;
  67         int cores_per_package;
  68         int ret;
  69
  70         cores_per_package = cpu_get_cores_per_package();
  71         ret = acpi_generate_cpu_header(ctx, core_id, cstate_map,
  72                                        ARRAY_SIZE(cstate_map));
  73
  74         /* Generate P-state tables */
  75         generate_p_state_entries(ctx, core_id, cores_per_package);
  76
  77         /* Generate T-state tables */
  78         generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0);
  79
  80         acpigen_pop_len(ctx);
  81
  82         if (device_is_last_sibling(dev)) {
  83                 ret = acpi_generate_cpu_package_final(ctx, cores_per_package);
  84
  85                 if (ret)
  86                         return ret;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static void update_fixed_mtrrs(void)
  93 {
  94         native_write_msr(MTRR_FIX_64K_00000_MSR,
  95                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  96                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  97         native_write_msr(MTRR_FIX_16K_80000_MSR,
  98                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  99                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 100         native_write_msr(MTRR_FIX_4K_E0000_MSR,
 101                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
 102                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 103         native_write_msr(MTRR_FIX_4K_E8000_MSR,
 104                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
 105                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 106         native_write_msr(MTRR_FIX_4K_F0000_MSR,
 107                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
 108                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 109         native_write_msr(MTRR_FIX_4K_F8000_MSR,
 110                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
 111                          MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 112 }
 113
 114 static void setup_core_msrs(void)
 115 {
 116         wrmsrl(MSR_PMG_CST_CONFIG_CONTROL,
 117                PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK |
 118                IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK);
 119         /* Power Management I/O base address for I/O trapping to C-states */
 120         wrmsrl(MSR_PMG_IO_CAPTURE_ADR, ACPI_PMIO_CST_REG |
 121                (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16));
 122         /* Disable C1E */
 123         msr_clrsetbits_64(MSR_POWER_CTL, 0x2, 0);
 124         /* Disable support for MONITOR and MWAIT instructions */
 125         msr_clrsetbits_64(MSR_IA32_MISC_ENABLE, MISC_ENABLE_MWAIT, 0);
 126         /*
 127          * Enable and Lock the Advanced Encryption Standard (AES-NI)
 128          * feature register
 129          */
 130         msr_clrsetbits_64(MSR_FEATURE_CONFIG, FEATURE_CONFIG_RESERVED_MASK,
 131                           FEATURE_CONFIG_LOCK);
 132
 133         update_fixed_mtrrs();
 134 }
 135
 136 static int soc_core_init(void)
 137 {
 138         struct udevice *pmc;
 139         int ret;
 140
 141         /* Clear out pending MCEs */
 142         cpu_mca_configure();
 143
 144         /* Set core MSRs */
 145         setup_core_msrs();
 146         /*
 147          * Enable ACPI PM timer emulation, which also lets microcode know
 148          * location of ACPI_BASE_ADDRESS. This also enables other features
 149          * implemented in microcode.
 150          */
 151         ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
 152         if (ret)
 153                 return log_msg_ret("PMC", ret);
 154         enable_pm_timer_emulation(pmc);
 155
 156         return 0;
 157 }
 158
 159 static int cpu_apl_probe(struct udevice *dev)
 160 {
 161         if (gd->flags & GD_FLG_RELOC) {
 162                 int ret;
 163
 164                 ret = soc_core_init();
 165                 if (ret)
 166                         return log_ret(ret);
 167         }
 168
 169         return 0;
 170 }
 171
 172 struct acpi_ops apl_cpu_acpi_ops = {
 173         .fill_ssdt      = acpi_cpu_fill_ssdt,
 174 };
 175
 176 static const struct cpu_ops cpu_x86_apl_ops = {
 177         .get_desc       = cpu_x86_get_desc,
 178         .get_info       = apl_get_info,
 179         .get_count      = cpu_x86_get_count,
 180         .get_vendor     = cpu_x86_get_vendor,
 181 };
 182
 183 static const struct udevice_id cpu_x86_apl_ids[] = {
 184         { .compatible = "intel,apl-cpu" },
 185         { }
 186 };
 187
 188 U_BOOT_DRIVER(intel_apl_cpu) = {
 189         .name           = "intel_apl_cpu",
 190         .id             = UCLASS_CPU,
 191         .of_match       = cpu_x86_apl_ids,
 192         .bind           = cpu_x86_bind,
 193         .probe          = cpu_apl_probe,
 194         .ops            = &cpu_x86_apl_ops,
 195         ACPI_OPS_PTR(&apl_cpu_acpi_ops)
 196         .flags          = DM_FLAG_PRE_RELOC,
 197 };