1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 1991, 1992, 1993 Linus Torvalds
9 * head.S contains the 32-bit startup code.
11 * NOTE!!! Startup happens at absolute address 0x00001000, which is also where
12 * the page directory will exist. The startup code will be overwritten by
13 * the page directory. [According to comments etc elsewhere on a compressed
14 * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
16 * Page 0 is deliberately kept safe, since System Management Mode code in
17 * laptops may need to access the BIOS data stored there. This is also
18 * useful for future device drivers that either access the BIOS via VM86
23 * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
28 #include <linux/init.h>
29 #include <linux/linkage.h>
30 #include <asm/segment.h>
33 #include <asm/processor-flags.h>
34 #include <asm/asm-offsets.h>
35 #include <asm/bootparam.h>
36 #include <asm/desc_defs.h>
37 #include <asm/trapnr.h>
41 * Fix alignment at 16 bytes. Following CONFIG_FUNCTION_ALIGNMENT will result
42 * in assembly errors due to trying to move .org backward due to the excessive
46 #define __ALIGN .balign 16, 0x90
49 * Locally defined symbols should be marked hidden:
58 * This macro gives the relative virtual address of X, i.e. the offset of X
59 * from startup_32. This is the same as the link-time virtual address of X,
60 * since startup_32 is at 0, but defining it this way tells the
61 * assembler/linker that we do not want the actual run-time address of X. This
62 * prevents the linker from trying to create unwanted run-time relocation
63 * entries for the reference when the compressed kernel is linked as PIE.
65 * A reference X(%reg) will result in the link-time VA of X being stored with
66 * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
67 * adds the 64-bit base address where the kernel is loaded.
69 * Replacing it with (X-startup_32)(%reg) results in the offset being stored,
70 * and no run-time relocation.
72 * The macro should be used as a displacement with a base register containing
73 * the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate
76 * This macro can only be used from within the .head.text section, since the
77 * expression requires startup_32 to be in the same section as the code being
80 #define rva(X) ((X) - startup_32)
83 SYM_FUNC_START(startup_32)
85 * 32bit entry is 0 and it is ABI so immutable!
86 * If we come here directly from a bootloader,
87 * kernel(text+data+bss+brk) ramdisk, zero_page, command line
88 * all need to be under the 4G limit.
94 * Calculate the delta between where we were compiled to run
95 * at and where we were actually loaded at. This can only be done
96 * with a short local call on x86. Nothing else will tell us what
97 * address we are running at. The reserved chunk of the real-mode
98 * data at 0x1e4 (defined as a scratch field) are used as the stack
99 * for this calculation. Only 4 bytes are needed.
101 leal (BP_scratch+4)(%esi), %esp
106 /* Load new GDT with the 64bit segments using 32bit descriptor */
107 leal rva(gdt)(%ebp), %eax
111 /* Load segment registers with our descriptors */
112 movl $__BOOT_DS, %eax
119 /* Setup a stack and load CS from current GDT */
120 leal rva(boot_stack_end)(%ebp), %esp
123 leal rva(1f)(%ebp), %eax
128 /* Setup Exception handling for SEV-ES */
129 #ifdef CONFIG_AMD_MEM_ENCRYPT
130 call startup32_load_idt
133 /* Make sure cpu supports long mode. */
139 * Compute the delta between where we were compiled to run at
140 * and where the code will actually run at.
142 * %ebp contains the address we are loaded at by the boot loader and %ebx
143 * contains the address where we should move the kernel image temporarily
144 * for safe in-place decompression.
147 #ifdef CONFIG_RELOCATABLE
150 #ifdef CONFIG_EFI_STUB
152 * If we were loaded via the EFI LoadImage service, startup_32 will be at an
153 * offset to the start of the space allocated for the image. efi_pe_entry will
154 * set up image_offset to tell us where the image actually starts, so that we
155 * can use the full available buffer.
156 * image_offset = startup_32 - image_base
157 * Otherwise image_offset will be zero and has no effect on the calculations.
159 subl rva(image_offset)(%ebp), %ebx
162 movl BP_kernel_alignment(%esi), %eax
167 cmpl $LOAD_PHYSICAL_ADDR, %ebx
170 movl $LOAD_PHYSICAL_ADDR, %ebx
173 /* Target address to relocate to for decompression */
174 addl BP_init_size(%esi), %ebx
175 subl $ rva(_end), %ebx
178 * Prepare for entering 64 bit mode
181 /* Enable PAE mode */
183 orl $X86_CR4_PAE, %eax
187 * Build early 4G boot pagetable
190 * If SEV is active then set the encryption mask in the page tables.
191 * This will ensure that when the kernel is copied and decompressed
192 * it will be done so encrypted.
195 #ifdef CONFIG_AMD_MEM_ENCRYPT
196 call get_sev_encryption_bit
200 subl $32, %eax /* Encryption bit is always above bit 31 */
201 bts %eax, %edx /* Set encryption mask for page tables */
203 * Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that
204 * startup32_check_sev_cbit() will do a check. sev_enable() will
205 * initialize sev_status with all the bits reported by
206 * MSR_AMD_SEV_STATUS later, but only MSR_AMD64_SEV_ENABLED_BIT
207 * needs to be set for now.
209 movl $1, rva(sev_status)(%ebp)
213 /* Initialize Page tables to 0 */
214 leal rva(pgtable)(%ebx), %edi
216 movl $(BOOT_INIT_PGT_SIZE/4), %ecx
220 leal rva(pgtable + 0)(%ebx), %edi
221 leal 0x1007 (%edi), %eax
226 leal rva(pgtable + 0x1000)(%ebx), %edi
227 leal 0x1007(%edi), %eax
229 1: movl %eax, 0x00(%edi)
230 addl %edx, 0x04(%edi)
231 addl $0x00001000, %eax
237 leal rva(pgtable + 0x2000)(%ebx), %edi
238 movl $0x00000183, %eax
240 1: movl %eax, 0(%edi)
242 addl $0x00200000, %eax
247 /* Enable the boot page tables */
248 leal rva(pgtable)(%ebx), %eax
251 /* Enable Long mode in EFER (Extended Feature Enable Register) */
254 btsl $_EFER_LME, %eax
257 /* After gdt is loaded */
260 movl $__BOOT_TSS, %eax
263 #ifdef CONFIG_AMD_MEM_ENCRYPT
264 /* Check if the C-bit position is correct when SEV is active */
265 call startup32_check_sev_cbit
269 * Setup for the jump to 64bit mode
271 * When the jump is performed we will be in long mode but
272 * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
273 * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
274 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
275 * We place all of the values on our mini stack so lret can
276 * used to perform that far jump.
278 leal rva(startup_64)(%ebp), %eax
279 #ifdef CONFIG_EFI_MIXED
280 cmpb $1, rva(efi_is64)(%ebp)
282 leal rva(startup_64_mixed_mode)(%ebp), %eax
289 /* Enter paged protected Mode, activating Long Mode */
290 movl $CR0_STATE, %eax
293 /* Jump from 32bit compatibility mode into 64bit mode. */
295 SYM_FUNC_END(startup_32)
299 SYM_CODE_START(startup_64)
301 * 64bit entry is 0x200 and it is ABI so immutable!
302 * We come here either from startup_32 or directly from a
304 * If we come here from a bootloader, kernel(text+data+bss+brk),
305 * ramdisk, zero_page, command line could be above 4G.
306 * We depend on an identity mapped page table being provided
307 * that maps our entire kernel(text+data+bss+brk), zero page
314 /* Setup data segments. */
323 * Compute the decompressed kernel start address. It is where
324 * we were loaded at aligned to a 2M boundary. %rbp contains the
325 * decompressed kernel start address.
327 * If it is a relocatable kernel then decompress and run the kernel
328 * from load address aligned to 2MB addr, otherwise decompress and
329 * run the kernel from LOAD_PHYSICAL_ADDR
331 * We cannot rely on the calculation done in 32-bit mode, since we
332 * may have been invoked via the 64-bit entry point.
335 /* Start with the delta to where the kernel will run at. */
336 #ifdef CONFIG_RELOCATABLE
337 leaq startup_32(%rip) /* - $startup_32 */, %rbp
339 #ifdef CONFIG_EFI_STUB
341 * If we were loaded via the EFI LoadImage service, startup_32 will be at an
342 * offset to the start of the space allocated for the image. efi_pe_entry will
343 * set up image_offset to tell us where the image actually starts, so that we
344 * can use the full available buffer.
345 * image_offset = startup_32 - image_base
346 * Otherwise image_offset will be zero and has no effect on the calculations.
348 movl image_offset(%rip), %eax
352 movl BP_kernel_alignment(%rsi), %eax
357 cmpq $LOAD_PHYSICAL_ADDR, %rbp
360 movq $LOAD_PHYSICAL_ADDR, %rbp
363 /* Target address to relocate to for decompression */
364 movl BP_init_size(%rsi), %ebx
365 subl $ rva(_end), %ebx
368 /* Set up the stack */
369 leaq rva(boot_stack_end)(%rbx), %rsp
372 * At this point we are in long mode with 4-level paging enabled,
373 * but we might want to enable 5-level paging or vice versa.
375 * The problem is that we cannot do it directly. Setting or clearing
376 * CR4.LA57 in long mode would trigger #GP. So we need to switch off
377 * long mode and paging first.
379 * We also need a trampoline in lower memory to switch over from
380 * 4- to 5-level paging for cases when the bootloader puts the kernel
381 * above 4G, but didn't enable 5-level paging for us.
383 * The same trampoline can be used to switch from 5- to 4-level paging
384 * mode, like when starting 4-level paging kernel via kexec() when
385 * original kernel worked in 5-level paging mode.
387 * For the trampoline, we need the top page table to reside in lower
388 * memory as we don't have a way to load 64-bit values into CR3 in
392 /* Make sure we have GDT with 32-bit code segment */
393 leaq gdt64(%rip), %rax
397 /* Reload CS so IRET returns to a CS actually in the GDT */
399 leaq .Lon_kernel_cs(%rip), %rax
405 * RSI holds a pointer to a boot_params structure provided by the
406 * loader, and this needs to be preserved across C function calls. So
407 * move it into a callee saved register.
413 #ifdef CONFIG_AMD_MEM_ENCRYPT
415 * Now that the stage1 interrupt handlers are set up, #VC exceptions from
416 * CPUID instructions can be properly handled for SEV-ES guests.
418 * For SEV-SNP, the CPUID table also needs to be set up in advance of any
419 * CPUID instructions being issued, so go ahead and do that now via
420 * sev_enable(), which will also handle the rest of the SEV-related
421 * detection/setup to ensure that has been done in advance of any dependent
422 * code. Pass the boot_params pointer as the first argument.
429 * configure_5level_paging() updates the number of paging levels using
430 * a trampoline in 32-bit addressable memory if the current number does
431 * not match the desired number.
433 * Pass the boot_params pointer as the first argument.
436 call configure_5level_paging
439 * cleanup_trampoline() would restore trampoline memory.
441 * RDI is address of the page table to use instead of page table
442 * in trampoline memory (if required).
444 leaq rva(top_pgtable)(%rbx), %rdi
445 call cleanup_trampoline
452 * Copy the compressed kernel to the end of our buffer
453 * where decompression in place becomes safe.
455 leaq (_bss-8)(%rip), %rsi
456 leaq rva(_bss-8)(%rbx), %rdi
457 movl $(_bss - startup_32), %ecx
464 * The GDT may get overwritten either during the copy we just did or
465 * during extract_kernel below. To avoid any issues, repoint the GDTR
466 * to the new copy of the GDT.
468 leaq rva(gdt64)(%rbx), %rax
469 leaq rva(gdt)(%rbx), %rdx
474 * Jump to the relocated address.
476 leaq rva(.Lrelocated)(%rbx), %rax
478 SYM_CODE_END(startup_64)
481 SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated)
484 * Clear BSS (stack is currently empty)
487 leaq _bss(%rip), %rdi
488 leaq _ebss(%rip), %rcx
495 /* Pass boot_params to initialize_identity_maps() */
497 call initialize_identity_maps
500 * Do the extraction, and jump to the new kernel..
502 /* pass struct boot_params pointer */
504 leaq boot_heap(%rip), %rsi /* malloc area for uncompression */
505 leaq input_data(%rip), %rdx /* input_data */
506 movl input_len(%rip), %ecx /* input_len */
507 movq %rbp, %r8 /* output target address */
508 movl output_len(%rip), %r9d /* decompressed length, end of relocs */
509 call extract_kernel /* returns kernel entry point in %rax */
512 * Jump to the decompressed kernel.
516 SYM_FUNC_END(.Lrelocated)
519 * This is the 32-bit trampoline that will be copied over to low memory. It
520 * will be called using the ordinary 64-bit calling convention from code
521 * running in 64-bit mode.
523 * Return address is at the top of the stack (might be above 4G).
524 * The first argument (EDI) contains the 32-bit addressable base of the
527 .section ".rodata", "a", @progbits
528 SYM_CODE_START(trampoline_32bit_src)
530 * Preserve callee save 64-bit registers on the stack: this is
531 * necessary because the architecture does not guarantee that GPRs will
532 * retain their full 64-bit values across a 32-bit mode switch.
541 /* Preserve top half of RSP in a legacy mode GPR to avoid truncation */
545 /* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
552 * The 32-bit code below will do a far jump back to long mode and end
553 * up here after reconfiguring the number of paging levels. First, the
554 * stack pointer needs to be restored to its full 64-bit value before
555 * the callee save register contents can be popped from the stack.
561 /* Restore the preserved 64-bit registers */
574 btrl $X86_CR0_PG_BIT, %eax
577 /* Point CR3 to the trampoline's new top level page table */
578 leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%edi), %eax
581 /* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
584 btsl $_EFER_LME, %eax
585 /* Avoid writing EFER if no change was made (for TDX guest) */
589 /* Toggle CR4.LA57 */
591 btcl $X86_CR4_LA57_BIT, %eax
594 /* Enable paging again. */
596 btsl $X86_CR0_PG_BIT, %eax
600 * Return to the 64-bit calling code using LJMP rather than LRET, to
601 * avoid the need for a 32-bit addressable stack. The destination
602 * address will be adjusted after the template code is copied into a
603 * 32-bit addressable buffer.
605 .Ljmp: ljmpl $__KERNEL_CS, $(.Lret - trampoline_32bit_src)
606 SYM_CODE_END(trampoline_32bit_src)
609 * This symbol is placed right after trampoline_32bit_src() so its address can
610 * be used to infer the size of the trampoline code.
612 SYM_DATA(trampoline_ljmp_imm_offset, .word .Ljmp + 1 - trampoline_32bit_src)
615 * The trampoline code has a size limit.
616 * Make sure we fail to compile if the trampoline code grows
617 * beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
619 .org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
622 SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode)
623 /* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
627 SYM_FUNC_END(.Lno_longmode)
630 #include "../../kernel/verify_cpu.S"
633 SYM_DATA_START_LOCAL(gdt64)
634 .word gdt_end - gdt - 1
638 SYM_DATA_START_LOCAL(gdt)
639 .word gdt_end - gdt - 1
642 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */
643 .quad 0x00af9a000000ffff /* __KERNEL_CS */
644 .quad 0x00cf92000000ffff /* __KERNEL_DS */
645 .quad 0x0080890000000000 /* TS descriptor */
646 .quad 0x0000000000000000 /* TS continued */
647 SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end)
649 SYM_DATA_START(boot_idt_desc)
650 .word boot_idt_end - boot_idt - 1
652 SYM_DATA_END(boot_idt_desc)
654 SYM_DATA_START(boot_idt)
655 .rept BOOT_IDT_ENTRIES
659 SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end)
662 * Stack and heap for uncompression
666 SYM_DATA_LOCAL(boot_heap, .fill BOOT_HEAP_SIZE, 1, 0)
668 SYM_DATA_START_LOCAL(boot_stack)
669 .fill BOOT_STACK_SIZE, 1, 0
671 SYM_DATA_END_LABEL(boot_stack, SYM_L_LOCAL, boot_stack_end)
674 * Space for page tables (not in .bss so not zeroed)
676 .section ".pgtable","aw",@nobits
678 SYM_DATA_LOCAL(pgtable, .fill BOOT_PGT_SIZE, 1, 0)
681 * The page table is going to be used instead of page table in the trampoline
684 SYM_DATA_LOCAL(top_pgtable, .fill PAGE_SIZE, 1, 0)