1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
37 select SPL_SEPARATE_BSS
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
40 experimental and many features are missing. U-Boot SPL starts up,
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
42 mode and jumps to U-Boot proper.
54 prompt "Mainboard vendor"
55 default VENDOR_EMULATION
57 config VENDOR_ADVANTECH
60 config VENDOR_CONGATEC
63 config VENDOR_COREBOOT
72 config VENDOR_EMULATION
83 # subarchitectures-specific options below
85 bool "Intel MID platform support"
89 Select to build a U-Boot capable of supporting Intel MID
90 (Mobile Internet Device) platform systems which do not have
91 the PCI legacy interfaces.
93 If you are building for a PC class system say N here.
95 Intel MID platforms are based on an Intel processor and
96 chipset which consume less power than most of the x86
99 # board-specific options below
100 source "board/advantech/Kconfig"
101 source "board/congatec/Kconfig"
102 source "board/coreboot/Kconfig"
103 source "board/dfi/Kconfig"
104 source "board/efi/Kconfig"
105 source "board/emulation/Kconfig"
106 source "board/google/Kconfig"
107 source "board/intel/Kconfig"
109 # platform-specific options below
110 source "arch/x86/cpu/baytrail/Kconfig"
111 source "arch/x86/cpu/broadwell/Kconfig"
112 source "arch/x86/cpu/coreboot/Kconfig"
113 source "arch/x86/cpu/ivybridge/Kconfig"
114 source "arch/x86/cpu/qemu/Kconfig"
115 source "arch/x86/cpu/quark/Kconfig"
116 source "arch/x86/cpu/queensbay/Kconfig"
117 source "arch/x86/cpu/tangier/Kconfig"
119 # architecture-specific options below
124 config SYS_MALLOC_F_LEN
133 depends on X86_RESET_VECTOR
142 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
151 config X86_RESET_VECTOR
155 # The following options control where the 16-bit and 32-bit init lies
156 # If SPL is enabled then it normally holds this init code, and U-Boot proper
157 # is normally a 64-bit build.
159 # The 16-bit init refers to the reset vector and the small amount of code to
160 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
161 # or missing altogether if U-Boot is started from EFI or coreboot.
163 # The 32-bit init refers to processor init, running binary blobs including
164 # FSP, setting up interrupts and anything else that needs to be done in
165 # 32-bit code. It is normally in the same place as 16-bit init if that is
166 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
167 config X86_16BIT_INIT
169 depends on X86_RESET_VECTOR
170 default y if X86_RESET_VECTOR && !SPL
172 This is enabled when 16-bit init is in U-Boot proper
174 config SPL_X86_16BIT_INIT
176 depends on X86_RESET_VECTOR
177 default y if X86_RESET_VECTOR && SPL
179 This is enabled when 16-bit init is in SPL
181 config X86_32BIT_INIT
183 depends on X86_RESET_VECTOR
184 default y if X86_RESET_VECTOR && !SPL
186 This is enabled when 32-bit init is in U-Boot proper
188 config SPL_X86_32BIT_INIT
190 depends on X86_RESET_VECTOR
191 default y if X86_RESET_VECTOR && SPL
193 This is enabled when 32-bit init is in SPL
195 config RESET_SEG_START
197 depends on X86_RESET_VECTOR
200 config RESET_SEG_SIZE
202 depends on X86_RESET_VECTOR
207 depends on X86_RESET_VECTOR
210 config SYS_X86_START16
212 depends on X86_RESET_VECTOR
215 config X86_LOAD_FROM_32_BIT
216 bool "Boot from a 32-bit program"
218 Define this to boot U-Boot from a 32-bit program which sets
219 the GDT differently. This can be used to boot directly from
220 any stage of coreboot, for example, bypassing the normal
221 payload-loading feature.
223 config BOARD_ROMSIZE_KB_512
225 config BOARD_ROMSIZE_KB_1024
227 config BOARD_ROMSIZE_KB_2048
229 config BOARD_ROMSIZE_KB_4096
231 config BOARD_ROMSIZE_KB_8192
233 config BOARD_ROMSIZE_KB_16384
237 prompt "ROM chip size"
238 depends on X86_RESET_VECTOR
239 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
240 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
241 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
242 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
243 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
244 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
246 Select the size of the ROM chip you intend to flash U-Boot on.
248 The build system will take care of creating a u-boot.rom file
249 of the matching size.
251 config UBOOT_ROMSIZE_KB_512
254 Choose this option if you have a 512 KB ROM chip.
256 config UBOOT_ROMSIZE_KB_1024
257 bool "1024 KB (1 MB)"
259 Choose this option if you have a 1024 KB (1 MB) ROM chip.
261 config UBOOT_ROMSIZE_KB_2048
262 bool "2048 KB (2 MB)"
264 Choose this option if you have a 2048 KB (2 MB) ROM chip.
266 config UBOOT_ROMSIZE_KB_4096
267 bool "4096 KB (4 MB)"
269 Choose this option if you have a 4096 KB (4 MB) ROM chip.
271 config UBOOT_ROMSIZE_KB_8192
272 bool "8192 KB (8 MB)"
274 Choose this option if you have a 8192 KB (8 MB) ROM chip.
276 config UBOOT_ROMSIZE_KB_16384
277 bool "16384 KB (16 MB)"
279 Choose this option if you have a 16384 KB (16 MB) ROM chip.
283 # Map the config names to an integer (KB).
284 config UBOOT_ROMSIZE_KB
286 default 512 if UBOOT_ROMSIZE_KB_512
287 default 1024 if UBOOT_ROMSIZE_KB_1024
288 default 2048 if UBOOT_ROMSIZE_KB_2048
289 default 4096 if UBOOT_ROMSIZE_KB_4096
290 default 8192 if UBOOT_ROMSIZE_KB_8192
291 default 16384 if UBOOT_ROMSIZE_KB_16384
293 # Map the config names to a hex value (bytes).
296 default 0x80000 if UBOOT_ROMSIZE_KB_512
297 default 0x100000 if UBOOT_ROMSIZE_KB_1024
298 default 0x200000 if UBOOT_ROMSIZE_KB_2048
299 default 0x400000 if UBOOT_ROMSIZE_KB_4096
300 default 0x800000 if UBOOT_ROMSIZE_KB_8192
301 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
302 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
305 bool "Platform requires Intel Management Engine"
307 Newer higher-end devices have an Intel Management Engine (ME)
308 which is a very large binary blob (typically 1.5MB) which is
309 required for the platform to work. This enforces a particular
310 SPI flash format. You will need to supply the me.bin file in
311 your board directory.
314 bool "Perform a simple RAM test after SDRAM initialisation"
316 If there is something wrong with SDRAM then the platform will
317 often crash within U-Boot or the kernel. This option enables a
318 very simple RAM test that quickly checks whether the SDRAM seems
319 to work correctly. It is not exhaustive but can save time by
320 detecting obvious failures.
322 config FLASH_DESCRIPTOR_FILE
323 string "Flash descriptor binary filename"
324 depends on HAVE_INTEL_ME
325 default "descriptor.bin"
327 The filename of the file to use as flash descriptor in the
331 string "Intel Management Engine binary filename"
332 depends on HAVE_INTEL_ME
335 The filename of the file to use as Intel Management Engine in the
339 bool "Add an Firmware Support Package binary"
342 Select this option to add an Firmware Support Package binary to
343 the resulting U-Boot image. It is a binary blob which U-Boot uses
344 to set up SDRAM and other chipset specific initialization.
346 Note: Without this binary U-Boot will not be able to set up its
347 SDRAM so will not boot.
350 string "Firmware Support Package binary filename"
354 The filename of the file to use as Firmware Support Package binary
355 in the board directory.
358 hex "Firmware Support Package binary location"
362 FSP is not Position Independent Code (PIC) and the whole FSP has to
363 be rebased if it is placed at a location which is different from the
364 perferred base address specified during the FSP build. Use Intel's
365 Binary Configuration Tool (BCT) to do the rebase.
367 The default base address of 0xfffc0000 indicates that the binary must
368 be located at offset 0xc0000 from the beginning of a 1MB flash device.
370 config FSP_TEMP_RAM_ADDR
375 Stack top address which is used in fsp_init() after DRAM is ready and
378 config FSP_SYS_MALLOC_F_LEN
383 Additional size of malloc() pool before relocation.
390 Most FSPs use UPD data region for some FSP customization. But there
391 are still some FSPs that might not even have UPD. For such FSPs,
392 override this to n in their platform Kconfig files.
394 config FSP_BROKEN_HOB
398 Indicate some buggy FSPs that does not report memory used by FSP
399 itself as reserved in the resource descriptor HOB. Select this to
400 tell U-Boot to do some additional work to ensure U-Boot relocation
401 do not overwrite the important boot service data which is used by
402 FSP, otherwise the subsequent call to fsp_notify() will fail.
404 config ENABLE_MRC_CACHE
405 bool "Enable MRC cache"
406 depends on !EFI && !SYS_COREBOOT
408 Enable this feature to cause MRC data to be cached in NV storage
409 to be used for speeding up boot time on future reboots and/or
412 For platforms that use Intel FSP for the memory initialization,
413 please check FSP output HOB via U-Boot command 'fsp hob' to see
414 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
415 If such GUID does not exist, MRC cache is not avaiable on such
416 platform (eg: Intel Queensbay), which means selecting this option
417 here does not make any difference.
420 bool "Add a System Agent binary"
423 Select this option to add a System Agent binary to
424 the resulting U-Boot image. MRC stands for Memory Reference Code.
425 It is a binary blob which U-Boot uses to set up SDRAM.
427 Note: Without this binary U-Boot will not be able to set up its
428 SDRAM so will not boot.
435 Enable caching for the memory reference code binary. This uses an
436 MTRR (memory type range register) to turn on caching for the section
437 of SPI flash that contains the memory reference code. This makes
438 SDRAM init run faster.
440 config CACHE_MRC_SIZE_KB
445 Sets the size of the cached area for the memory reference code.
446 This ends at the end of SPI flash (address 0xffffffff) and is
447 measured in KB. Typically this is set to 512, providing for 0.5MB
450 config DCACHE_RAM_BASE
454 Sets the base of the data cache area in memory space. This is the
455 start address of the cache-as-RAM (CAR) area and the address varies
456 depending on the CPU. Once CAR is set up, read/write memory becomes
457 available at this address and can be used temporarily until SDRAM
460 config DCACHE_RAM_SIZE
465 Sets the total size of the data cache area in memory space. This
466 sets the size of the cache-as-RAM (CAR) area. Note that much of the
467 CAR space is required by the MRC. The CAR space available to U-Boot
468 is normally at the start and typically extends to 1/4 or 1/2 of the
471 config DCACHE_RAM_MRC_VAR_SIZE
475 This is the amount of CAR (Cache as RAM) reserved for use by the
476 memory reference code. This depends on the implementation of the
477 memory reference code and must be set correctly or the board will
481 bool "Add a Reference Code binary"
483 Select this option to add a Reference Code binary to the resulting
484 U-Boot image. This is an Intel binary blob that handles system
485 initialisation, in this case the PCH and System Agent.
487 Note: Without this binary (on platforms that need it such as
488 broadwell) U-Boot will be missing some critical setup steps.
489 Various peripherals may fail to work.
492 bool "Enable Symmetric Multiprocessing"
495 Enable use of more than one CPU in U-Boot and the Operating System
496 when loaded. Each CPU will be started up and information can be
497 obtained using the 'cpu' command. If this option is disabled, then
498 only one CPU will be enabled regardless of the number of CPUs
502 int "Maximum number of CPUs permitted"
506 When using multi-CPU chips it is possible for U-Boot to start up
507 more than one CPU. The stack memory used by all of these CPUs is
508 pre-allocated so at present U-Boot wants to know the maximum
509 number of CPUs that may be present. Set this to at least as high
510 as the number of CPUs in your system (it uses about 4KB of RAM for
518 Each additional CPU started by U-Boot requires its own stack. This
519 option sets the stack size used by each CPU and directly affects
520 the memory used by this initialisation process. Typically 4KB is
524 bool "Add a VGA BIOS image"
526 Select this option if you have a VGA BIOS image that you would
527 like to add to your ROM.
530 string "VGA BIOS image filename"
531 depends on HAVE_VGA_BIOS
534 The filename of the VGA BIOS image in the board directory.
537 hex "VGA BIOS image location"
538 depends on HAVE_VGA_BIOS
541 The location of VGA BIOS image in the SPI flash. For example, base
542 address of 0xfff90000 indicates that the image will be put at offset
543 0x90000 from the beginning of a 1MB flash device.
545 config ROM_TABLE_ADDR
549 All x86 tables happen to like the address range from 0x0f0000
550 to 0x100000. We use 0xf0000 as the starting address to store
551 those tables, including PIRQ routing table, Multi-Processor
552 table and ACPI table.
554 config ROM_TABLE_SIZE
559 depends on !EFI && !SYS_COREBOOT
561 config GENERATE_PIRQ_TABLE
562 bool "Generate a PIRQ table"
565 Generate a PIRQ routing table for this board. The PIRQ routing table
566 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
567 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
568 It specifies the interrupt router information as well how all the PCI
569 devices' interrupt pins are wired to PIRQs.
571 config GENERATE_SFI_TABLE
572 bool "Generate a SFI (Simple Firmware Interface) table"
574 The Simple Firmware Interface (SFI) provides a lightweight method
575 for platform firmware to pass information to the operating system
576 via static tables in memory. Kernel SFI support is required to
577 boot on SFI-only platforms. If you have ACPI tables then these are
580 U-Boot writes this table in write_sfi_table() just before booting
583 For more information, see http://simplefirmware.org
585 config GENERATE_MP_TABLE
586 bool "Generate an MP (Multi-Processor) table"
589 Generate an MP (Multi-Processor) table for this board. The MP table
590 provides a way for the operating system to support for symmetric
591 multiprocessing as well as symmetric I/O interrupt handling with
592 the local APIC and I/O APIC.
594 config GENERATE_ACPI_TABLE
595 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
599 The Advanced Configuration and Power Interface (ACPI) specification
600 provides an open standard for device configuration and management
601 by the operating system. It defines platform-independent interfaces
602 for configuration and power management monitoring.
606 config HAVE_ACPI_RESUME
607 bool "Enable ACPI S3 resume"
609 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
610 state where all system context is lost except system memory. U-Boot
611 is responsible for restoring the machine state as it was before sleep.
612 It needs restore the memory controller, without overwriting memory
613 which is not marked as reserved. For the peripherals which lose their
614 registers, U-Boot needs to write the original value. When everything
615 is done, U-Boot needs to find out the wakeup vector provided by OSes
618 config S3_VGA_ROM_RUN
619 bool "Re-run VGA option ROMs on S3 resume"
620 depends on HAVE_ACPI_RESUME
621 default y if HAVE_ACPI_RESUME
623 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
624 this is needed when graphics console is being used in the kernel.
626 Turning it off can reduce some resume time, but be aware that your
627 graphics console won't work without VGA options ROMs. Set it to N
628 if your kernel is only on a serial console.
632 depends on HAVE_ACPI_RESUME
635 Estimated U-Boot's runtime stack size that needs to be reserved
636 during an ACPI S3 resume.
638 config MAX_PIRQ_LINKS
642 This variable specifies the number of PIRQ interrupt links which are
643 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
644 Some newer chipsets offer more than four links, commonly up to PIRQH.
646 config IRQ_SLOT_COUNT
650 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
651 which in turns forms a table of exact 4KiB. The default value 128
652 should be enough for most boards. If this does not fit your board,
653 change it according to your needs.
655 config PCIE_ECAM_BASE
659 This is the memory-mapped address of PCI configuration space, which
660 is only available through the Enhanced Configuration Access
661 Mechanism (ECAM) with PCI Express. It can be set up almost
662 anywhere. Before it is set up, it is possible to access PCI
663 configuration space through I/O access, but memory access is more
664 convenient. Using this, PCI can be scanned and configured. This
665 should be set to a region that does not conflict with memory
666 assigned to PCI devices - i.e. the memory and prefetch regions, as
667 passed to pci_set_region().
669 config PCIE_ECAM_SIZE
673 This is the size of memory-mapped address of PCI configuration space,
674 which is only available through the Enhanced Configuration Access
675 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
676 so a default 0x10000000 size covers all of the 256 buses which is the
677 maximum number of PCI buses as defined by the PCI specification.
683 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
684 slave) interrupt controllers. Include this to have U-Boot set up
685 the interrupt correctly.
691 Intel 8254 timer contains three counters which have fixed uses.
692 Include this to have U-Boot set up the timer correctly.
695 bool "Support booting SeaBIOS"
697 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
698 It can run in an emulator or natively on X86 hardware with the use
699 of coreboot/U-Boot. By turning on this option, U-Boot prepares
700 all the configuration tables that are necessary to boot SeaBIOS.
702 Check http://www.seabios.org/SeaBIOS for details.
704 config HIGH_TABLE_SIZE
705 hex "Size of configuration tables which reside in high memory"
709 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
710 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
711 puts a copy of configuration tables in high memory region which
712 is reserved on the stack before relocation. The region size is
713 determined by this option.
715 Increse it if the default size does not fit the board's needs.
716 This is most likely due to a large ACPI DSDT table is used.
718 source "arch/x86/lib/efi/Kconfig"