1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
17 config VENDOR_EMULATION
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/efi/Kconfig"
31 source "board/emulation/Kconfig"
32 source "board/google/Kconfig"
33 source "board/intel/Kconfig"
35 # platform-specific options below
36 source "arch/x86/cpu/baytrail/Kconfig"
37 source "arch/x86/cpu/coreboot/Kconfig"
38 source "arch/x86/cpu/ivybridge/Kconfig"
39 source "arch/x86/cpu/qemu/Kconfig"
40 source "arch/x86/cpu/quark/Kconfig"
41 source "arch/x86/cpu/queensbay/Kconfig"
43 # architecture-specific options below
45 config SYS_MALLOC_F_LEN
54 depends on X86_RESET_VECTOR
63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
72 config X86_RESET_VECTOR
76 config RESET_SEG_START
78 depends on X86_RESET_VECTOR
83 depends on X86_RESET_VECTOR
88 depends on X86_RESET_VECTOR
91 config SYS_X86_START16
93 depends on X86_RESET_VECTOR
97 default y # Until we finish moving over to the new API
99 config BOARD_ROMSIZE_KB_512
101 config BOARD_ROMSIZE_KB_1024
103 config BOARD_ROMSIZE_KB_2048
105 config BOARD_ROMSIZE_KB_4096
107 config BOARD_ROMSIZE_KB_8192
109 config BOARD_ROMSIZE_KB_16384
113 prompt "ROM chip size"
114 depends on X86_RESET_VECTOR
115 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
116 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
117 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
118 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
119 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
120 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
122 Select the size of the ROM chip you intend to flash U-Boot on.
124 The build system will take care of creating a u-boot.rom file
125 of the matching size.
127 config UBOOT_ROMSIZE_KB_512
130 Choose this option if you have a 512 KB ROM chip.
132 config UBOOT_ROMSIZE_KB_1024
133 bool "1024 KB (1 MB)"
135 Choose this option if you have a 1024 KB (1 MB) ROM chip.
137 config UBOOT_ROMSIZE_KB_2048
138 bool "2048 KB (2 MB)"
140 Choose this option if you have a 2048 KB (2 MB) ROM chip.
142 config UBOOT_ROMSIZE_KB_4096
143 bool "4096 KB (4 MB)"
145 Choose this option if you have a 4096 KB (4 MB) ROM chip.
147 config UBOOT_ROMSIZE_KB_8192
148 bool "8192 KB (8 MB)"
150 Choose this option if you have a 8192 KB (8 MB) ROM chip.
152 config UBOOT_ROMSIZE_KB_16384
153 bool "16384 KB (16 MB)"
155 Choose this option if you have a 16384 KB (16 MB) ROM chip.
159 # Map the config names to an integer (KB).
160 config UBOOT_ROMSIZE_KB
162 default 512 if UBOOT_ROMSIZE_KB_512
163 default 1024 if UBOOT_ROMSIZE_KB_1024
164 default 2048 if UBOOT_ROMSIZE_KB_2048
165 default 4096 if UBOOT_ROMSIZE_KB_4096
166 default 8192 if UBOOT_ROMSIZE_KB_8192
167 default 16384 if UBOOT_ROMSIZE_KB_16384
169 # Map the config names to a hex value (bytes).
172 default 0x80000 if UBOOT_ROMSIZE_KB_512
173 default 0x100000 if UBOOT_ROMSIZE_KB_1024
174 default 0x200000 if UBOOT_ROMSIZE_KB_2048
175 default 0x400000 if UBOOT_ROMSIZE_KB_4096
176 default 0x800000 if UBOOT_ROMSIZE_KB_8192
177 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
178 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
181 bool "Platform requires Intel Management Engine"
183 Newer higher-end devices have an Intel Management Engine (ME)
184 which is a very large binary blob (typically 1.5MB) which is
185 required for the platform to work. This enforces a particular
186 SPI flash format. You will need to supply the me.bin file in
187 your board directory.
190 bool "Perform a simple RAM test after SDRAM initialisation"
192 If there is something wrong with SDRAM then the platform will
193 often crash within U-Boot or the kernel. This option enables a
194 very simple RAM test that quickly checks whether the SDRAM seems
195 to work correctly. It is not exhaustive but can save time by
196 detecting obvious failures.
199 bool "Add an Firmware Support Package binary"
202 Select this option to add an Firmware Support Package binary to
203 the resulting U-Boot image. It is a binary blob which U-Boot uses
204 to set up SDRAM and other chipset specific initialization.
206 Note: Without this binary U-Boot will not be able to set up its
207 SDRAM so will not boot.
210 string "Firmware Support Package binary filename"
214 The filename of the file to use as Firmware Support Package binary
215 in the board directory.
218 hex "Firmware Support Package binary location"
222 FSP is not Position Independent Code (PIC) and the whole FSP has to
223 be rebased if it is placed at a location which is different from the
224 perferred base address specified during the FSP build. Use Intel's
225 Binary Configuration Tool (BCT) to do the rebase.
227 The default base address of 0xfffc0000 indicates that the binary must
228 be located at offset 0xc0000 from the beginning of a 1MB flash device.
230 config FSP_TEMP_RAM_ADDR
235 Stack top address which is used in fsp_init() after DRAM is ready and
238 config FSP_SYS_MALLOC_F_LEN
243 Additional size of malloc() pool before relocation.
250 Most FSPs use UPD data region for some FSP customization. But there
251 are still some FSPs that might not even have UPD. For such FSPs,
252 override this to n in their platform Kconfig files.
254 config ENABLE_MRC_CACHE
255 bool "Enable MRC cache"
256 depends on !EFI && !SYS_COREBOOT
258 Enable this feature to cause MRC data to be cached in NV storage
259 to be used for speeding up boot time on future reboots and/or
263 bool "Enable Symmetric Multiprocessing"
266 Enable use of more than one CPU in U-Boot and the Operating System
267 when loaded. Each CPU will be started up and information can be
268 obtained using the 'cpu' command. If this option is disabled, then
269 only one CPU will be enabled regardless of the number of CPUs
273 int "Maximum number of CPUs permitted"
277 When using multi-CPU chips it is possible for U-Boot to start up
278 more than one CPU. The stack memory used by all of these CPUs is
279 pre-allocated so at present U-Boot wants to know the maximum
280 number of CPUs that may be present. Set this to at least as high
281 as the number of CPUs in your system (it uses about 4KB of RAM for
289 Each additional CPU started by U-Boot requires its own stack. This
290 option sets the stack size used by each CPU and directly affects
291 the memory used by this initialisation process. Typically 4KB is
295 bool "Add a VGA BIOS image"
297 Select this option if you have a VGA BIOS image that you would
298 like to add to your ROM.
301 string "VGA BIOS image filename"
302 depends on HAVE_VGA_BIOS
305 The filename of the VGA BIOS image in the board directory.
308 hex "VGA BIOS image location"
309 depends on HAVE_VGA_BIOS
312 The location of VGA BIOS image in the SPI flash. For example, base
313 address of 0xfff90000 indicates that the image will be put at offset
314 0x90000 from the beginning of a 1MB flash device.
317 depends on !EFI && !SYS_COREBOOT
319 config GENERATE_PIRQ_TABLE
320 bool "Generate a PIRQ table"
323 Generate a PIRQ routing table for this board. The PIRQ routing table
324 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
325 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
326 It specifies the interrupt router information as well how all the PCI
327 devices' interrupt pins are wired to PIRQs.
329 config GENERATE_SFI_TABLE
330 bool "Generate a SFI (Simple Firmware Interface) table"
332 The Simple Firmware Interface (SFI) provides a lightweight method
333 for platform firmware to pass information to the operating system
334 via static tables in memory. Kernel SFI support is required to
335 boot on SFI-only platforms. If you have ACPI tables then these are
338 U-Boot writes this table in write_sfi_table() just before booting
341 For more information, see http://simplefirmware.org
343 config GENERATE_MP_TABLE
344 bool "Generate an MP (Multi-Processor) table"
347 Generate an MP (Multi-Processor) table for this board. The MP table
348 provides a way for the operating system to support for symmetric
349 multiprocessing as well as symmetric I/O interrupt handling with
350 the local APIC and I/O APIC.
352 config GENERATE_ACPI_TABLE
353 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
356 The Advanced Configuration and Power Interface (ACPI) specification
357 provides an open standard for device configuration and management
358 by the operating system. It defines platform-independent interfaces
359 for configuration and power management monitoring.
361 config GENERATE_SMBIOS_TABLE
362 bool "Generate an SMBIOS (System Management BIOS) table"
365 The System Management BIOS (SMBIOS) specification addresses how
366 motherboard and system vendors present management information about
367 their products in a standard format by extending the BIOS interface
368 on Intel architecture systems.
370 Check http://www.dmtf.org/standards/smbios for details.
374 config MAX_PIRQ_LINKS
378 This variable specifies the number of PIRQ interrupt links which are
379 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
380 Some newer chipsets offer more than four links, commonly up to PIRQH.
382 config IRQ_SLOT_COUNT
386 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
387 which in turns forms a table of exact 4KiB. The default value 128
388 should be enough for most boards. If this does not fit your board,
389 change it according to your needs.
391 config PCIE_ECAM_BASE
395 This is the memory-mapped address of PCI configuration space, which
396 is only available through the Enhanced Configuration Access
397 Mechanism (ECAM) with PCI Express. It can be set up almost
398 anywhere. Before it is set up, it is possible to access PCI
399 configuration space through I/O access, but memory access is more
400 convenient. Using this, PCI can be scanned and configured. This
401 should be set to a region that does not conflict with memory
402 assigned to PCI devices - i.e. the memory and prefetch regions, as
403 passed to pci_set_region().
405 config PCIE_ECAM_SIZE
409 This is the size of memory-mapped address of PCI configuration space,
410 which is only available through the Enhanced Configuration Access
411 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
412 so a default 0x10000000 size covers all of the 256 buses which is the
413 maximum number of PCI buses as defined by the PCI specification.
419 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
420 slave) interrupt controllers. Include this to have U-Boot set up
421 the interrupt correctly.
427 Intel 8254 timer contains three counters which have fixed uses.
428 Include this to have U-Boot set up the timer correctly.
436 source "arch/x86/lib/efi/Kconfig"