1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
35 config TARGET_CROWNBAY
36 bool "Support Intel Crown Bay CRB"
38 This is the Intel Crown Bay Customer Reference Board. It contains
39 the Intel Atom Processor E6xx populated on the COM Express module
40 with 1GB DDR2 soldered down memory and a carrier board with the
41 Intel Platform Controller Hub EG20T, other system components and
42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
44 config TARGET_MINNOWMAX
45 bool "Support Intel Minnowboard MAX"
47 This is the Intel Minnowboard MAX. It contains an Atom E3800
48 processor in a small form factor with Ethernet, micro-SD, USB 2,
49 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
50 It requires some binary blobs - see README.x86 for details.
52 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
53 by U-Boot matches that value.
63 depends on X86_RESET_VECTOR
72 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
81 config X86_RESET_VECTOR
85 config SYS_X86_START16
87 depends on X86_RESET_VECTOR
90 config BOARD_ROMSIZE_KB_512
92 config BOARD_ROMSIZE_KB_1024
94 config BOARD_ROMSIZE_KB_2048
96 config BOARD_ROMSIZE_KB_4096
98 config BOARD_ROMSIZE_KB_8192
100 config BOARD_ROMSIZE_KB_16384
104 prompt "ROM chip size"
105 depends on X86_RESET_VECTOR
106 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
107 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
108 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
109 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
110 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
111 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
113 Select the size of the ROM chip you intend to flash U-Boot on.
115 The build system will take care of creating a u-boot.rom file
116 of the matching size.
118 config UBOOT_ROMSIZE_KB_512
121 Choose this option if you have a 512 KB ROM chip.
123 config UBOOT_ROMSIZE_KB_1024
124 bool "1024 KB (1 MB)"
126 Choose this option if you have a 1024 KB (1 MB) ROM chip.
128 config UBOOT_ROMSIZE_KB_2048
129 bool "2048 KB (2 MB)"
131 Choose this option if you have a 2048 KB (2 MB) ROM chip.
133 config UBOOT_ROMSIZE_KB_4096
134 bool "4096 KB (4 MB)"
136 Choose this option if you have a 4096 KB (4 MB) ROM chip.
138 config UBOOT_ROMSIZE_KB_8192
139 bool "8192 KB (8 MB)"
141 Choose this option if you have a 8192 KB (8 MB) ROM chip.
143 config UBOOT_ROMSIZE_KB_16384
144 bool "16384 KB (16 MB)"
146 Choose this option if you have a 16384 KB (16 MB) ROM chip.
150 # Map the config names to an integer (KB).
151 config UBOOT_ROMSIZE_KB
153 default 512 if UBOOT_ROMSIZE_KB_512
154 default 1024 if UBOOT_ROMSIZE_KB_1024
155 default 2048 if UBOOT_ROMSIZE_KB_2048
156 default 4096 if UBOOT_ROMSIZE_KB_4096
157 default 8192 if UBOOT_ROMSIZE_KB_8192
158 default 16384 if UBOOT_ROMSIZE_KB_16384
160 # Map the config names to a hex value (bytes).
163 default 0x80000 if UBOOT_ROMSIZE_KB_512
164 default 0x100000 if UBOOT_ROMSIZE_KB_1024
165 default 0x200000 if UBOOT_ROMSIZE_KB_2048
166 default 0x400000 if UBOOT_ROMSIZE_KB_4096
167 default 0x800000 if UBOOT_ROMSIZE_KB_8192
168 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
169 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
172 bool "Platform requires Intel Management Engine"
174 Newer higher-end devices have an Intel Management Engine (ME)
175 which is a very large binary blob (typically 1.5MB) which is
176 required for the platform to work. This enforces a particular
177 SPI flash format. You will need to supply the me.bin file in
178 your board directory.
181 bool "Perform a simple RAM test after SDRAM initialisation"
183 If there is something wrong with SDRAM then the platform will
184 often crash within U-Boot or the kernel. This option enables a
185 very simple RAM test that quickly checks whether the SDRAM seems
186 to work correctly. It is not exhaustive but can save time by
187 detecting obvious failures.
189 config MARK_GRAPHICS_MEM_WRCOMB
190 bool "Mark graphics memory as write-combining."
193 The graphics performance may increase if the graphics
194 memory is set as write-combining cache type. This option
195 enables marking the graphics memory as write-combining.
199 config FRAMEBUFFER_SET_VESA_MODE
200 prompt "Set framebuffer graphics resolution"
203 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
206 prompt "framebuffer graphics resolution"
207 default FRAMEBUFFER_VESA_MODE_117
208 depends on FRAMEBUFFER_SET_VESA_MODE
210 This option sets the resolution used for the coreboot framebuffer (and
213 config FRAMEBUFFER_VESA_MODE_100
214 bool "640x400 256-color"
216 config FRAMEBUFFER_VESA_MODE_101
217 bool "640x480 256-color"
219 config FRAMEBUFFER_VESA_MODE_102
220 bool "800x600 16-color"
222 config FRAMEBUFFER_VESA_MODE_103
223 bool "800x600 256-color"
225 config FRAMEBUFFER_VESA_MODE_104
226 bool "1024x768 16-color"
228 config FRAMEBUFFER_VESA_MODE_105
229 bool "1024x7686 256-color"
231 config FRAMEBUFFER_VESA_MODE_106
232 bool "1280x1024 16-color"
234 config FRAMEBUFFER_VESA_MODE_107
235 bool "1280x1024 256-color"
237 config FRAMEBUFFER_VESA_MODE_108
240 config FRAMEBUFFER_VESA_MODE_109
243 config FRAMEBUFFER_VESA_MODE_10A
246 config FRAMEBUFFER_VESA_MODE_10B
249 config FRAMEBUFFER_VESA_MODE_10C
252 config FRAMEBUFFER_VESA_MODE_10D
253 bool "320x200 32k-color (1:5:5:5)"
255 config FRAMEBUFFER_VESA_MODE_10E
256 bool "320x200 64k-color (5:6:5)"
258 config FRAMEBUFFER_VESA_MODE_10F
259 bool "320x200 16.8M-color (8:8:8)"
261 config FRAMEBUFFER_VESA_MODE_110
262 bool "640x480 32k-color (1:5:5:5)"
264 config FRAMEBUFFER_VESA_MODE_111
265 bool "640x480 64k-color (5:6:5)"
267 config FRAMEBUFFER_VESA_MODE_112
268 bool "640x480 16.8M-color (8:8:8)"
270 config FRAMEBUFFER_VESA_MODE_113
271 bool "800x600 32k-color (1:5:5:5)"
273 config FRAMEBUFFER_VESA_MODE_114
274 bool "800x600 64k-color (5:6:5)"
276 config FRAMEBUFFER_VESA_MODE_115
277 bool "800x600 16.8M-color (8:8:8)"
279 config FRAMEBUFFER_VESA_MODE_116
280 bool "1024x768 32k-color (1:5:5:5)"
282 config FRAMEBUFFER_VESA_MODE_117
283 bool "1024x768 64k-color (5:6:5)"
285 config FRAMEBUFFER_VESA_MODE_118
286 bool "1024x768 16.8M-color (8:8:8)"
288 config FRAMEBUFFER_VESA_MODE_119
289 bool "1280x1024 32k-color (1:5:5:5)"
291 config FRAMEBUFFER_VESA_MODE_11A
292 bool "1280x1024 64k-color (5:6:5)"
294 config FRAMEBUFFER_VESA_MODE_11B
295 bool "1280x1024 16.8M-color (8:8:8)"
297 config FRAMEBUFFER_VESA_MODE_USER
298 bool "Manually select VESA mode"
302 # Map the config names to an integer (KB).
303 config FRAMEBUFFER_VESA_MODE
304 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
306 default 0x100 if FRAMEBUFFER_VESA_MODE_100
307 default 0x101 if FRAMEBUFFER_VESA_MODE_101
308 default 0x102 if FRAMEBUFFER_VESA_MODE_102
309 default 0x103 if FRAMEBUFFER_VESA_MODE_103
310 default 0x104 if FRAMEBUFFER_VESA_MODE_104
311 default 0x105 if FRAMEBUFFER_VESA_MODE_105
312 default 0x106 if FRAMEBUFFER_VESA_MODE_106
313 default 0x107 if FRAMEBUFFER_VESA_MODE_107
314 default 0x108 if FRAMEBUFFER_VESA_MODE_108
315 default 0x109 if FRAMEBUFFER_VESA_MODE_109
316 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
317 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
318 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
319 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
320 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
321 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
322 default 0x110 if FRAMEBUFFER_VESA_MODE_110
323 default 0x111 if FRAMEBUFFER_VESA_MODE_111
324 default 0x112 if FRAMEBUFFER_VESA_MODE_112
325 default 0x113 if FRAMEBUFFER_VESA_MODE_113
326 default 0x114 if FRAMEBUFFER_VESA_MODE_114
327 default 0x115 if FRAMEBUFFER_VESA_MODE_115
328 default 0x116 if FRAMEBUFFER_VESA_MODE_116
329 default 0x117 if FRAMEBUFFER_VESA_MODE_117
330 default 0x118 if FRAMEBUFFER_VESA_MODE_118
331 default 0x119 if FRAMEBUFFER_VESA_MODE_119
332 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
333 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
334 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
338 config TSC_CALIBRATION_BYPASS
339 bool "Bypass Time-Stamp Counter (TSC) calibration"
342 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
343 running frequency via Model-Specific Register (MSR) and Programmable
344 Interval Timer (PIT). If the calibration does not work on your board,
345 select this option and provide a hardcoded TSC running frequency with
346 CONFIG_TSC_FREQ_IN_MHZ below.
348 Normally this option should be turned on in a simulation environment
351 config TSC_FREQ_IN_MHZ
352 int "Time-Stamp Counter (TSC) running frequency in MHz"
353 depends on TSC_CALIBRATION_BYPASS
356 The running frequency in MHz of Time-Stamp Counter (TSC).
359 bool "Add an Firmware Support Package binary"
361 Select this option to add an Firmware Support Package binary to
362 the resulting U-Boot image. It is a binary blob which U-Boot uses
363 to set up SDRAM and other chipset specific initialization.
365 Note: Without this binary U-Boot will not be able to set up its
366 SDRAM so will not boot.
369 string "Firmware Support Package binary filename"
373 The filename of the file to use as Firmware Support Package binary
374 in the board directory.
377 hex "Firmware Support Package binary location"
381 FSP is not Position Independent Code (PIC) and the whole FSP has to
382 be rebased if it is placed at a location which is different from the
383 perferred base address specified during the FSP build. Use Intel's
384 Binary Configuration Tool (BCT) to do the rebase.
386 The default base address of 0xfffc0000 indicates that the binary must
387 be located at offset 0xc0000 from the beginning of a 1MB flash device.
389 config FSP_TEMP_RAM_ADDR
393 Stack top address which is used in FspInit after DRAM is ready and
396 source "arch/x86/cpu/baytrail/Kconfig"
398 source "arch/x86/cpu/coreboot/Kconfig"
400 source "arch/x86/cpu/ivybridge/Kconfig"
402 source "arch/x86/cpu/queensbay/Kconfig"
404 source "board/coreboot/coreboot/Kconfig"
406 source "board/google/chromebook_link/Kconfig"
408 source "board/intel/crownbay/Kconfig"
410 source "board/intel/minnowmax/Kconfig"
412 config PCIE_ECAM_BASE
416 This is the memory-mapped address of PCI configuration space, which
417 is only available through the Enhanced Configuration Access
418 Mechanism (ECAM) with PCI Express. It can be set up almost
419 anywhere. Before it is set up, it is possible to access PCI
420 configuration space through I/O access, but memory access is more
421 convenient. Using this, PCI can be scanned and configured. This
422 should be set to a region that does not conflict with memory
423 assigned to PCI devices - i.e. the memory and prefetch regions, as
424 passed to pci_set_region().