1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/apollolake/Kconfig"
110 source "arch/x86/cpu/baytrail/Kconfig"
111 source "arch/x86/cpu/braswell/Kconfig"
112 source "arch/x86/cpu/broadwell/Kconfig"
113 source "arch/x86/cpu/coreboot/Kconfig"
114 source "arch/x86/cpu/ivybridge/Kconfig"
115 source "arch/x86/cpu/efi/Kconfig"
116 source "arch/x86/cpu/qemu/Kconfig"
117 source "arch/x86/cpu/quark/Kconfig"
118 source "arch/x86/cpu/queensbay/Kconfig"
119 source "arch/x86/cpu/slimbootloader/Kconfig"
120 source "arch/x86/cpu/tangier/Kconfig"
122 # architecture-specific options below
127 config SYS_MALLOC_F_LEN
136 depends on X86_RESET_VECTOR
145 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
154 config X86_RESET_VECTOR
159 # The following options control where the 16-bit and 32-bit init lies
160 # If SPL is enabled then it normally holds this init code, and U-Boot proper
161 # is normally a 64-bit build.
163 # The 16-bit init refers to the reset vector and the small amount of code to
164 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
165 # or missing altogether if U-Boot is started from EFI or coreboot.
167 # The 32-bit init refers to processor init, running binary blobs including
168 # FSP, setting up interrupts and anything else that needs to be done in
169 # 32-bit code. It is normally in the same place as 16-bit init if that is
170 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
171 config X86_16BIT_INIT
173 depends on X86_RESET_VECTOR
174 default y if X86_RESET_VECTOR && !SPL
176 This is enabled when 16-bit init is in U-Boot proper
178 config SPL_X86_16BIT_INIT
180 depends on X86_RESET_VECTOR
181 default y if X86_RESET_VECTOR && SPL && !TPL
183 This is enabled when 16-bit init is in SPL
185 config TPL_X86_16BIT_INIT
187 depends on X86_RESET_VECTOR
188 default y if X86_RESET_VECTOR && TPL
190 This is enabled when 16-bit init is in TPL
192 config X86_32BIT_INIT
194 depends on X86_RESET_VECTOR
195 default y if X86_RESET_VECTOR && !SPL
197 This is enabled when 32-bit init is in U-Boot proper
199 config SPL_X86_32BIT_INIT
201 depends on X86_RESET_VECTOR
202 default y if X86_RESET_VECTOR && SPL
204 This is enabled when 32-bit init is in SPL
206 config USE_EARLY_BOARD_INIT
209 config RESET_SEG_START
211 depends on X86_RESET_VECTOR
216 depends on X86_RESET_VECTOR
219 config SYS_X86_START16
221 depends on X86_RESET_VECTOR
227 Enable inclusion of an Intel Firmware Interface Table (FIT) into the
228 image. This table is supposed to point to microcode and the like. So
229 far it is just a fixed table with the minimum set of headers, so that
230 it is actually present.
232 config X86_LOAD_FROM_32_BIT
233 bool "Boot from a 32-bit program"
235 Define this to boot U-Boot from a 32-bit program which sets
236 the GDT differently. This can be used to boot directly from
237 any stage of coreboot, for example, bypassing the normal
238 payload-loading feature.
240 config BOARD_ROMSIZE_KB_512
242 config BOARD_ROMSIZE_KB_1024
244 config BOARD_ROMSIZE_KB_2048
246 config BOARD_ROMSIZE_KB_4096
248 config BOARD_ROMSIZE_KB_8192
250 config BOARD_ROMSIZE_KB_16384
254 prompt "ROM chip size"
255 depends on X86_RESET_VECTOR
256 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
257 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
258 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
259 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
260 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
261 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
263 Select the size of the ROM chip you intend to flash U-Boot on.
265 The build system will take care of creating a u-boot.rom file
266 of the matching size.
268 config UBOOT_ROMSIZE_KB_512
271 Choose this option if you have a 512 KB ROM chip.
273 config UBOOT_ROMSIZE_KB_1024
274 bool "1024 KB (1 MB)"
276 Choose this option if you have a 1024 KB (1 MB) ROM chip.
278 config UBOOT_ROMSIZE_KB_2048
279 bool "2048 KB (2 MB)"
281 Choose this option if you have a 2048 KB (2 MB) ROM chip.
283 config UBOOT_ROMSIZE_KB_4096
284 bool "4096 KB (4 MB)"
286 Choose this option if you have a 4096 KB (4 MB) ROM chip.
288 config UBOOT_ROMSIZE_KB_8192
289 bool "8192 KB (8 MB)"
291 Choose this option if you have a 8192 KB (8 MB) ROM chip.
293 config UBOOT_ROMSIZE_KB_16384
294 bool "16384 KB (16 MB)"
296 Choose this option if you have a 16384 KB (16 MB) ROM chip.
300 # Map the config names to an integer (KB).
301 config UBOOT_ROMSIZE_KB
303 default 512 if UBOOT_ROMSIZE_KB_512
304 default 1024 if UBOOT_ROMSIZE_KB_1024
305 default 2048 if UBOOT_ROMSIZE_KB_2048
306 default 4096 if UBOOT_ROMSIZE_KB_4096
307 default 8192 if UBOOT_ROMSIZE_KB_8192
308 default 16384 if UBOOT_ROMSIZE_KB_16384
310 # Map the config names to a hex value (bytes).
313 default 0x80000 if UBOOT_ROMSIZE_KB_512
314 default 0x100000 if UBOOT_ROMSIZE_KB_1024
315 default 0x200000 if UBOOT_ROMSIZE_KB_2048
316 default 0x400000 if UBOOT_ROMSIZE_KB_4096
317 default 0x800000 if UBOOT_ROMSIZE_KB_8192
318 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
319 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
322 bool "Platform requires Intel Management Engine"
324 Newer higher-end devices have an Intel Management Engine (ME)
325 which is a very large binary blob (typically 1.5MB) which is
326 required for the platform to work. This enforces a particular
327 SPI flash format. You will need to supply the me.bin file in
328 your board directory.
331 bool "Perform a simple RAM test after SDRAM initialisation"
333 If there is something wrong with SDRAM then the platform will
334 often crash within U-Boot or the kernel. This option enables a
335 very simple RAM test that quickly checks whether the SDRAM seems
336 to work correctly. It is not exhaustive but can save time by
337 detecting obvious failures.
339 config FLASH_DESCRIPTOR_FILE
340 string "Flash descriptor binary filename"
341 depends on HAVE_INTEL_ME || FSP_VERSION2
342 default "descriptor.bin"
344 The filename of the file to use as flash descriptor in the
348 string "Intel Management Engine binary filename"
349 depends on HAVE_INTEL_ME
352 The filename of the file to use as Intel Management Engine in the
356 bool "Use HOB (Hand-Off Block)"
358 Select this option to access HOB (Hand-Off Block) data structures
359 and parse HOBs. This HOB infra structure can be reused with
360 different solutions across different platforms.
363 bool "Add an Firmware Support Package binary"
367 select ROM_NEEDS_BLOBS
369 Select this option to add an Firmware Support Package binary to
370 the resulting U-Boot image. It is a binary blob which U-Boot uses
371 to set up SDRAM and other chipset specific initialization.
373 Note: Without this binary U-Boot will not be able to set up its
374 SDRAM so will not boot.
377 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
378 default y if !HAVE_FSP
380 Select this option if your board uses CAR init code, typically in a
381 car.S file, to get some initial memory for code execution. This is
382 common with Intel CPUs which don't use FSP.
389 Selects the FSP version to use. Intel has published several versions
390 of the FSP External Architecture Specification and this allows
391 selection of the version number used by a particular SoC.
394 bool "FSP version 1.x"
396 This covers versions 1.0 and 1.1a. See here for details:
397 https://github.com/IntelFsp/fsp/wiki
400 bool "FSP version 2.x"
402 This covers versions 2.0 and 2.1. See here for details:
403 https://github.com/IntelFsp/fsp/wiki
408 string "Firmware Support Package binary filename"
409 depends on FSP_VERSION1
412 The filename of the file to use as Firmware Support Package binary
413 in the board directory.
416 hex "Firmware Support Package binary location"
417 depends on FSP_VERSION1
420 FSP is not Position Independent Code (PIC) and the whole FSP has to
421 be rebased if it is placed at a location which is different from the
422 perferred base address specified during the FSP build. Use Intel's
423 Binary Configuration Tool (BCT) to do the rebase.
425 The default base address of 0xfffc0000 indicates that the binary must
426 be located at offset 0xc0000 from the beginning of a 1MB flash device.
431 string "Firmware Support Package binary filename (Temp RAM)"
434 The filename of the file to use for the temporary-RAM init phase from
435 the Firmware Support Package binary. Put this in the board directory.
436 It is used to set up an initial area of RAM which can be used for the
437 stack and other purposes, while bringing up the main system DRAM.
440 hex "Firmware Support Package binary location (Temp RAM)"
443 FSP is not Position-Independent Code (PIC) and FSP components have to
444 be rebased if placed at a location which is different from the
445 perferred base address specified during the FSP build. Use Intel's
446 Binary Configuration Tool (BCT) to do the rebase.
449 string "Firmware Support Package binary filename (Memory Init)"
452 The filename of the file to use for the RAM init phase from the
453 Firmware Support Package binary. Put this in the board directory.
454 It is used to set up the main system DRAM and runs in SPL, once
455 temporary RAM (CAR) is working.
458 string "Firmware Support Package binary filename (Silicon Init)"
461 The filename of the file to use for the Silicon init phase from the
462 Firmware Support Package binary. Put this in the board directory.
463 It is used to set up the silicon to work correctly and must be
464 executed after DRAM is running.
466 config IFWI_INPUT_FILE
467 string "Filename containing FIT (Firmware Interface Table) with IFWI"
468 default "fitimage.bin"
470 The IFWI is obtained by running a tool on this file to extract the
471 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
472 microcode and other internal items.
476 config FSP_TEMP_RAM_ADDR
478 depends on FSP_VERSION1
481 Stack top address which is used in fsp_init() after DRAM is ready and
484 config FSP_SYS_MALLOC_F_LEN
486 depends on FSP_VERSION1
489 Additional size of malloc() pool before relocation.
493 depends on FSP_VERSION1
496 Most FSPs use UPD data region for some FSP customization. But there
497 are still some FSPs that might not even have UPD. For such FSPs,
498 override this to n in their platform Kconfig files.
500 config FSP_BROKEN_HOB
502 depends on FSP_VERSION1
504 Indicate some buggy FSPs that does not report memory used by FSP
505 itself as reserved in the resource descriptor HOB. Select this to
506 tell U-Boot to do some additional work to ensure U-Boot relocation
507 do not overwrite the important boot service data which is used by
508 FSP, otherwise the subsequent call to fsp_notify() will fail.
510 config ENABLE_MRC_CACHE
511 bool "Enable MRC cache"
512 depends on !EFI && !SYS_COREBOOT
514 Enable this feature to cause MRC data to be cached in NV storage
515 to be used for speeding up boot time on future reboots and/or
518 For platforms that use Intel FSP for the memory initialization,
519 please check FSP output HOB via U-Boot command 'fsp hob' to see
520 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
521 If such GUID does not exist, MRC cache is not available on such
522 platform (eg: Intel Queensbay), which means selecting this option
523 here does not make any difference.
526 bool "Add a System Agent binary"
528 select ROM_NEEDS_BLOBS
531 Select this option to add a System Agent binary to
532 the resulting U-Boot image. MRC stands for Memory Reference Code.
533 It is a binary blob which U-Boot uses to set up SDRAM.
535 Note: Without this binary U-Boot will not be able to set up its
536 SDRAM so will not boot.
543 Enable caching for the memory reference code binary. This uses an
544 MTRR (memory type range register) to turn on caching for the section
545 of SPI flash that contains the memory reference code. This makes
546 SDRAM init run faster.
548 config CACHE_MRC_SIZE_KB
553 Sets the size of the cached area for the memory reference code.
554 This ends at the end of SPI flash (address 0xffffffff) and is
555 measured in KB. Typically this is set to 512, providing for 0.5MB
558 config DCACHE_RAM_BASE
562 Sets the base of the data cache area in memory space. This is the
563 start address of the cache-as-RAM (CAR) area and the address varies
564 depending on the CPU. Once CAR is set up, read/write memory becomes
565 available at this address and can be used temporarily until SDRAM
568 config DCACHE_RAM_SIZE
573 Sets the total size of the data cache area in memory space. This
574 sets the size of the cache-as-RAM (CAR) area. Note that much of the
575 CAR space is required by the MRC. The CAR space available to U-Boot
576 is normally at the start and typically extends to 1/4 or 1/2 of the
579 config DCACHE_RAM_MRC_VAR_SIZE
583 This is the amount of CAR (Cache as RAM) reserved for use by the
584 memory reference code. This depends on the implementation of the
585 memory reference code and must be set correctly or the board will
589 bool "Add a Reference Code binary"
591 Select this option to add a Reference Code binary to the resulting
592 U-Boot image. This is an Intel binary blob that handles system
593 initialisation, in this case the PCH and System Agent.
595 Note: Without this binary (on platforms that need it such as
596 broadwell) U-Boot will be missing some critical setup steps.
597 Various peripherals may fail to work.
599 config HAVE_MICROCODE
600 bool "Board requires a microcode binary"
601 default y if !FSP_VERSION2
603 Enable this if the board requires microcode to be loaded on boot.
604 Typically this is handed by the FSP for modern boards, but for
605 some older boards, it must be programmed by U-Boot, and that form
609 bool "Enable Symmetric Multiprocessing"
612 Enable use of more than one CPU in U-Boot and the Operating System
613 when loaded. Each CPU will be started up and information can be
614 obtained using the 'cpu' command. If this option is disabled, then
615 only one CPU will be enabled regardless of the number of CPUs
622 Allow APs to do other work after initialisation instead of going
626 int "Maximum number of CPUs permitted"
630 When using multi-CPU chips it is possible for U-Boot to start up
631 more than one CPU. The stack memory used by all of these CPUs is
632 pre-allocated so at present U-Boot wants to know the maximum
633 number of CPUs that may be present. Set this to at least as high
634 as the number of CPUs in your system (it uses about 4KB of RAM for
642 Each additional CPU started by U-Boot requires its own stack. This
643 option sets the stack size used by each CPU and directly affects
644 the memory used by this initialisation process. Typically 4KB is
647 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
650 This option indicates that the turbo mode setting is not package
651 scoped. i.e. turbo_enable() needs to be called on not just the
652 bootstrap processor (BSP).
655 bool "Add a VGA BIOS image"
657 Select this option if you have a VGA BIOS image that you would
658 like to add to your ROM.
661 string "VGA BIOS image filename"
662 depends on HAVE_VGA_BIOS
665 The filename of the VGA BIOS image in the board directory.
668 hex "VGA BIOS image location"
669 depends on HAVE_VGA_BIOS
672 The location of VGA BIOS image in the SPI flash. For example, base
673 address of 0xfff90000 indicates that the image will be put at offset
674 0x90000 from the beginning of a 1MB flash device.
677 bool "Add a Video BIOS Table (VBT) image"
680 Select this option if you have a Video BIOS Table (VBT) image that
681 you would like to add to your ROM. This is normally required if you
682 are using an Intel FSP firmware that is complaint with spec 1.1 or
683 later to initialize the integrated graphics device (IGD).
685 Video BIOS Table, or VBT, provides platform and board specific
686 configuration information to the driver that is not discoverable
687 or available through other means. By other means the most used
688 method here is to read EDID table from the attached monitor, over
689 Display Data Channel (DDC) using two pin I2C serial interface. VBT
690 configuration is related to display hardware and is available via
691 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
694 string "Video BIOS Table (VBT) image filename"
698 The filename of the file to use as Video BIOS Table (VBT) image
699 in the board directory.
702 hex "Video BIOS Table (VBT) image location"
706 The location of Video BIOS Table (VBT) image in the SPI flash. For
707 example, base address of 0xfff90000 indicates that the image will
708 be put at offset 0x90000 from the beginning of a 1MB flash device.
711 bool "Enable FSP framebuffer driver support"
712 depends on HAVE_VBT && DM_VIDEO
714 Turn on this option to enable a framebuffer driver when U-Boot is
715 using Video BIOS Table (VBT) image for FSP firmware to initialize
716 the integrated graphics device.
718 config ROM_TABLE_ADDR
722 All x86 tables happen to like the address range from 0x0f0000
723 to 0x100000. We use 0xf0000 as the starting address to store
724 those tables, including PIRQ routing table, Multi-Processor
725 table and ACPI table.
727 config ROM_TABLE_SIZE
734 Select this to include the driver for the Interrupt Timer
735 Subsystem (ITSS) which is found on several Intel devices.
741 Select this to include the driver for the Primary to
742 Sideband Bridge (P2SB) which is found on several Intel
746 depends on !EFI && !SYS_COREBOOT
748 config GENERATE_PIRQ_TABLE
749 bool "Generate a PIRQ table"
752 Generate a PIRQ routing table for this board. The PIRQ routing table
753 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
754 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
755 It specifies the interrupt router information as well how all the PCI
756 devices' interrupt pins are wired to PIRQs.
758 config GENERATE_SFI_TABLE
759 bool "Generate a SFI (Simple Firmware Interface) table"
761 The Simple Firmware Interface (SFI) provides a lightweight method
762 for platform firmware to pass information to the operating system
763 via static tables in memory. Kernel SFI support is required to
764 boot on SFI-only platforms. If you have ACPI tables then these are
767 U-Boot writes this table in write_sfi_table() just before booting
770 For more information, see http://simplefirmware.org
772 config GENERATE_MP_TABLE
773 bool "Generate an MP (Multi-Processor) table"
776 Generate an MP (Multi-Processor) table for this board. The MP table
777 provides a way for the operating system to support for symmetric
778 multiprocessing as well as symmetric I/O interrupt handling with
779 the local APIC and I/O APIC.
781 config GENERATE_ACPI_TABLE
782 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
786 The Advanced Configuration and Power Interface (ACPI) specification
787 provides an open standard for device configuration and management
788 by the operating system. It defines platform-independent interfaces
789 for configuration and power management monitoring.
793 config HAVE_ACPI_RESUME
794 bool "Enable ACPI S3 resume"
795 select ENABLE_MRC_CACHE
797 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
798 state where all system context is lost except system memory. U-Boot
799 is responsible for restoring the machine state as it was before sleep.
800 It needs restore the memory controller, without overwriting memory
801 which is not marked as reserved. For the peripherals which lose their
802 registers, U-Boot needs to write the original value. When everything
803 is done, U-Boot needs to find out the wakeup vector provided by OSes
806 config S3_VGA_ROM_RUN
807 bool "Re-run VGA option ROMs on S3 resume"
808 depends on HAVE_ACPI_RESUME
810 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
811 this is needed when graphics console is being used in the kernel.
813 Turning it off can reduce some resume time, but be aware that your
814 graphics console won't work without VGA options ROMs. Set it to N
815 if your kernel is only on a serial console.
817 config STACK_SIZE_RESUME
819 depends on HAVE_ACPI_RESUME
822 Estimated U-Boot's runtime stack size that needs to be reserved
823 during an ACPI S3 resume.
825 config MAX_PIRQ_LINKS
829 This variable specifies the number of PIRQ interrupt links which are
830 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
831 Some newer chipsets offer more than four links, commonly up to PIRQH.
833 config IRQ_SLOT_COUNT
837 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
838 which in turns forms a table of exact 4KiB. The default value 128
839 should be enough for most boards. If this does not fit your board,
840 change it according to your needs.
842 config PCIE_ECAM_BASE
846 This is the memory-mapped address of PCI configuration space, which
847 is only available through the Enhanced Configuration Access
848 Mechanism (ECAM) with PCI Express. It can be set up almost
849 anywhere. Before it is set up, it is possible to access PCI
850 configuration space through I/O access, but memory access is more
851 convenient. Using this, PCI can be scanned and configured. This
852 should be set to a region that does not conflict with memory
853 assigned to PCI devices - i.e. the memory and prefetch regions, as
854 passed to pci_set_region().
856 config PCIE_ECAM_SIZE
860 This is the size of memory-mapped address of PCI configuration space,
861 which is only available through the Enhanced Configuration Access
862 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
863 so a default 0x10000000 size covers all of the 256 buses which is the
864 maximum number of PCI buses as defined by the PCI specification.
867 bool "Enable Intel 8259 compatible interrupt controller"
870 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
871 slave) interrupt controllers. Include this to have U-Boot set up
872 the interrupt correctly.
875 bool "Enable Intel Advanced Programmable Interrupt Controller"
878 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
879 for catching interrupts and distributing them to one or more CPU
880 cores. In most cases there are some LAPICs (local) for each core and
881 one I/O APIC. This conjunction is found on most modern x86 systems.
886 Intel ICH6 compatible chipset pinctrl driver. It needs to work
887 together with the ICH6 compatible gpio driver.
893 Intel 8254 timer contains three counters which have fixed uses.
894 Include this to have U-Boot set up the timer correctly.
897 bool "Support booting SeaBIOS"
899 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
900 It can run in an emulator or natively on X86 hardware with the use
901 of coreboot/U-Boot. By turning on this option, U-Boot prepares
902 all the configuration tables that are necessary to boot SeaBIOS.
904 Check http://www.seabios.org/SeaBIOS for details.
906 config HIGH_TABLE_SIZE
907 hex "Size of configuration tables which reside in high memory"
911 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
912 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
913 puts a copy of configuration tables in high memory region which
914 is reserved on the stack before relocation. The region size is
915 determined by this option.
917 Increse it if the default size does not fit the board's needs.
918 This is most likely due to a large ACPI DSDT table is used.
920 config INTEL_CAR_CQOS
921 bool "Support Intel Cache Quality of Service"
923 Cache Quality of Service allows more fine-grained control of cache
924 usage. As result, it is possible to set up a portion of L2 cache for
925 CAR and use the remainder for actual caching.
928 # Each bit in QOS mask controls this many bytes. This is calculated as:
929 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
931 config CACHE_QOS_SIZE_PER_BIT
933 depends on INTEL_CAR_CQOS
934 default 0x20000 # 128 KB
936 config X86_OFFSET_U_BOOT
937 hex "Offset of U-Boot in ROM image"
938 depends on HAVE_SYS_TEXT_BASE
939 default SYS_TEXT_BASE
941 config X86_OFFSET_SPL
942 hex "Offset of SPL in ROM image"
943 depends on SPL && X86
944 default SPL_TEXT_BASE
947 bool "Support ACPI general-purpose events"
949 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
950 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
951 needs access to these interrupts. This can happen when it uses a
952 peripheral that is set up to use GPEs and so cannot use the normal
953 GPIO mechanism for polling an input.
955 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
958 bool "Support ACPI general-purpose events in SPL"
960 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
961 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
962 needs access to these interrupts. This can happen when it uses a
963 peripheral that is set up to use GPEs and so cannot use the normal
964 GPIO mechanism for polling an input.
966 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
969 bool "Support ACPI general-purpose events in TPL"
971 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
972 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
973 needs access to these interrupts. This can happen when it uses a
974 peripheral that is set up to use GPEs and so cannot use the normal
975 GPIO mechanism for polling an input.
977 See https://queue.acm.org/blogposting.cfm?id=18977 for more info