2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
17 * The hypervisor's public API.
23 #include <arch/chip.h>
25 /* Linux builds want unsigned long constants, but assembler wants numbers */
27 /** One, for assembler */
28 #define __HV_SIZE_ONE 1
29 #elif !defined(__tile__) && CHIP_VA_WIDTH() > 32
30 /** One, for 64-bit on host */
31 #define __HV_SIZE_ONE 1ULL
34 #define __HV_SIZE_ONE 1UL
37 /** The log2 of the span of a level-1 page table, in bytes.
39 #define HV_LOG2_L1_SPAN 32
41 /** The span of a level-1 page table, in bytes.
43 #define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
45 /** The log2 of the initial size of small pages, in bytes.
46 * See HV_DEFAULT_PAGE_SIZE_SMALL.
48 #define HV_LOG2_DEFAULT_PAGE_SIZE_SMALL 16
50 /** The initial size of small pages, in bytes. This value should be verified
51 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
52 * It may also be modified when installing a new context.
54 #define HV_DEFAULT_PAGE_SIZE_SMALL \
55 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_SMALL)
57 /** The log2 of the initial size of large pages, in bytes.
58 * See HV_DEFAULT_PAGE_SIZE_LARGE.
60 #define HV_LOG2_DEFAULT_PAGE_SIZE_LARGE 24
62 /** The initial size of large pages, in bytes. This value should be verified
63 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
64 * It may also be modified when installing a new context.
66 #define HV_DEFAULT_PAGE_SIZE_LARGE \
67 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_LARGE)
69 /** The log2 of the granularity at which page tables must be aligned;
70 * in other words, the CPA for a page table must have this many zero
71 * bits at the bottom of the address.
73 #define HV_LOG2_PAGE_TABLE_ALIGN 11
75 /** The granularity at which page tables must be aligned.
77 #define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN)
79 /** Normal start of hypervisor glue in client physical memory. */
80 #define HV_GLUE_START_CPA 0x10000
82 /** This much space is reserved at HV_GLUE_START_CPA
83 * for the hypervisor glue. The client program must start at
84 * some address higher than this, and in particular the address of
85 * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE
86 * so that relative offsets to the HV glue are correct.
88 #define HV_GLUE_RESERVED_SIZE 0x10000
90 /** Each entry in the hv dispatch array takes this many bytes. */
91 #define HV_DISPATCH_ENTRY_SIZE 32
93 /** Version of the hypervisor interface defined by this file */
94 #define _HV_VERSION 11
96 /* Index into hypervisor interface dispatch code blocks.
98 * Hypervisor calls are invoked from user space by calling code
99 * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE,
100 * where index is one of these enum values.
102 * Normally a supervisor is expected to produce a set of symbols
103 * starting at HV_BASE_ADDRESS that obey this convention, but a user
104 * program could call directly through function pointers if desired.
106 * These numbers are part of the binary API and will not be changed
107 * without updating HV_VERSION, which should be a rare event.
111 #define _HV_DISPATCH_RESERVED 0
114 #define HV_DISPATCH_INIT 1
116 /** hv_install_context */
117 #define HV_DISPATCH_INSTALL_CONTEXT 2
120 #define HV_DISPATCH_SYSCONF 3
123 #define HV_DISPATCH_GET_RTC 4
126 #define HV_DISPATCH_SET_RTC 5
129 #define HV_DISPATCH_FLUSH_ASID 6
132 #define HV_DISPATCH_FLUSH_PAGE 7
134 /** hv_flush_pages */
135 #define HV_DISPATCH_FLUSH_PAGES 8
138 #define HV_DISPATCH_RESTART 9
141 #define HV_DISPATCH_HALT 10
144 #define HV_DISPATCH_POWER_OFF 11
146 /** hv_inquire_physical */
147 #define HV_DISPATCH_INQUIRE_PHYSICAL 12
149 /** hv_inquire_memory_controller */
150 #define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER 13
152 /** hv_inquire_virtual */
153 #define HV_DISPATCH_INQUIRE_VIRTUAL 14
155 /** hv_inquire_asid */
156 #define HV_DISPATCH_INQUIRE_ASID 15
159 #define HV_DISPATCH_NANOSLEEP 16
161 /** hv_console_read_if_ready */
162 #define HV_DISPATCH_CONSOLE_READ_IF_READY 17
164 /** hv_console_write */
165 #define HV_DISPATCH_CONSOLE_WRITE 18
167 /** hv_downcall_dispatch */
168 #define HV_DISPATCH_DOWNCALL_DISPATCH 19
170 /** hv_inquire_topology */
171 #define HV_DISPATCH_INQUIRE_TOPOLOGY 20
173 /** hv_fs_findfile */
174 #define HV_DISPATCH_FS_FINDFILE 21
177 #define HV_DISPATCH_FS_FSTAT 22
180 #define HV_DISPATCH_FS_PREAD 23
182 /** hv_physaddr_read64 */
183 #define HV_DISPATCH_PHYSADDR_READ64 24
185 /** hv_physaddr_write64 */
186 #define HV_DISPATCH_PHYSADDR_WRITE64 25
188 /** hv_get_command_line */
189 #define HV_DISPATCH_GET_COMMAND_LINE 26
191 /** hv_set_caching */
192 #define HV_DISPATCH_SET_CACHING 27
195 #define HV_DISPATCH_BZERO_PAGE 28
197 /** hv_register_message_state */
198 #define HV_DISPATCH_REGISTER_MESSAGE_STATE 29
200 /** hv_send_message */
201 #define HV_DISPATCH_SEND_MESSAGE 30
203 /** hv_receive_message */
204 #define HV_DISPATCH_RECEIVE_MESSAGE 31
206 /** hv_inquire_context */
207 #define HV_DISPATCH_INQUIRE_CONTEXT 32
209 /** hv_start_all_tiles */
210 #define HV_DISPATCH_START_ALL_TILES 33
213 #define HV_DISPATCH_DEV_OPEN 34
216 #define HV_DISPATCH_DEV_CLOSE 35
219 #define HV_DISPATCH_DEV_PREAD 36
222 #define HV_DISPATCH_DEV_PWRITE 37
225 #define HV_DISPATCH_DEV_POLL 38
227 /** hv_dev_poll_cancel */
228 #define HV_DISPATCH_DEV_POLL_CANCEL 39
231 #define HV_DISPATCH_DEV_PREADA 40
233 /** hv_dev_pwritea */
234 #define HV_DISPATCH_DEV_PWRITEA 41
236 /** hv_flush_remote */
237 #define HV_DISPATCH_FLUSH_REMOTE 42
239 /** hv_console_putc */
240 #define HV_DISPATCH_CONSOLE_PUTC 43
242 /** hv_inquire_tiles */
243 #define HV_DISPATCH_INQUIRE_TILES 44
246 #define HV_DISPATCH_CONFSTR 45
249 #define HV_DISPATCH_REEXEC 46
251 /** hv_set_command_line */
252 #define HV_DISPATCH_SET_COMMAND_LINE 47
257 #define HV_DISPATCH_CLEAR_INTR 48
259 /** hv_enable_intr */
260 #define HV_DISPATCH_ENABLE_INTR 49
262 /** hv_disable_intr */
263 #define HV_DISPATCH_DISABLE_INTR 50
266 #define HV_DISPATCH_RAISE_INTR 51
268 /** hv_trigger_ipi */
269 #define HV_DISPATCH_TRIGGER_IPI 52
271 #endif /* !CHIP_HAS_IPI() */
273 /** hv_store_mapping */
274 #define HV_DISPATCH_STORE_MAPPING 53
276 /** hv_inquire_realpa */
277 #define HV_DISPATCH_INQUIRE_REALPA 54
280 #define HV_DISPATCH_FLUSH_ALL 55
283 /** hv_get_ipi_pte */
284 #define HV_DISPATCH_GET_IPI_PTE 56
287 /** One more than the largest dispatch value */
288 #define _HV_DISPATCH_END 57
291 #ifndef __ASSEMBLER__
294 #include <asm/types.h>
295 typedef u32 __hv32; /**< 32-bit value */
296 typedef u64 __hv64; /**< 64-bit value */
299 typedef uint32_t __hv32; /**< 32-bit value */
300 typedef uint64_t __hv64; /**< 64-bit value */
304 /** Hypervisor physical address. */
305 typedef __hv64 HV_PhysAddr;
307 #if CHIP_VA_WIDTH() > 32
308 /** Hypervisor virtual address. */
309 typedef __hv64 HV_VirtAddr;
311 /** Hypervisor virtual address. */
312 typedef __hv32 HV_VirtAddr;
313 #endif /* CHIP_VA_WIDTH() > 32 */
315 /** Hypervisor ASID. */
316 typedef unsigned int HV_ASID;
318 /** Hypervisor tile location for a memory access
319 * ("location overridden target").
321 typedef unsigned int HV_LOTAR;
323 /** Hypervisor size of a page. */
324 typedef unsigned long HV_PageSize;
326 /** A page table entry.
330 __hv64 val; /**< Value of PTE */
333 /** Hypervisor error code. */
334 typedef int HV_Errno;
336 #endif /* !__ASSEMBLER__ */
338 #define HV_OK 0 /**< No error */
339 #define HV_EINVAL -801 /**< Invalid argument */
340 #define HV_ENODEV -802 /**< No such device */
341 #define HV_ENOENT -803 /**< No such file or directory */
342 #define HV_EBADF -804 /**< Bad file number */
343 #define HV_EFAULT -805 /**< Bad address */
344 #define HV_ERECIP -806 /**< Bad recipients */
345 #define HV_E2BIG -807 /**< Message too big */
346 #define HV_ENOTSUP -808 /**< Service not supported */
347 #define HV_EBUSY -809 /**< Device busy */
348 #define HV_ENOSYS -810 /**< Invalid syscall */
349 #define HV_EPERM -811 /**< No permission */
350 #define HV_ENOTREADY -812 /**< Device not ready */
351 #define HV_EIO -813 /**< I/O error */
352 #define HV_ENOMEM -814 /**< Out of memory */
353 #define HV_EAGAIN -815 /**< Try again */
355 #define HV_ERR_MAX -801 /**< Largest HV error code */
356 #define HV_ERR_MIN -815 /**< Smallest HV error code */
358 #ifndef __ASSEMBLER__
360 /** Pass HV_VERSION to hv_init to request this version of the interface. */
361 typedef enum { HV_VERSION = _HV_VERSION } HV_VersionNumber;
363 /** Initializes the hypervisor.
365 * @param interface_version_number The version of the hypervisor interface
366 * that this program expects, typically HV_VERSION.
367 * @param chip_num Architecture number of the chip the client was built for.
368 * @param chip_rev_num Revision number of the chip the client was built for.
370 void hv_init(HV_VersionNumber interface_version_number,
371 int chip_num, int chip_rev_num);
374 /** Queries we can make for hv_sysconf().
376 * These numbers are part of the binary API and guaranteed not to change.
379 /** An invalid value; do not use. */
380 _HV_SYSCONF_RESERVED = 0,
382 /** The length of the glue section containing the hv_ procs, in bytes. */
383 HV_SYSCONF_GLUE_SIZE = 1,
385 /** The size of small pages, in bytes. */
386 HV_SYSCONF_PAGE_SIZE_SMALL = 2,
388 /** The size of large pages, in bytes. */
389 HV_SYSCONF_PAGE_SIZE_LARGE = 3,
391 /** Processor clock speed, in hertz. */
392 HV_SYSCONF_CPU_SPEED = 4,
394 /** Processor temperature, in degrees Kelvin. The value
395 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
396 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
397 * that the temperature has hit an upper limit and is no longer being
398 * accurately tracked.
400 HV_SYSCONF_CPU_TEMP = 5,
402 /** Board temperature, in degrees Kelvin. The value
403 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
404 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
405 * that the temperature has hit an upper limit and is no longer being
406 * accurately tracked.
408 HV_SYSCONF_BOARD_TEMP = 6,
410 /** Legal page size bitmask for hv_install_context().
411 * For example, if 16KB and 64KB small pages are supported,
412 * it would return "HV_CTX_PG_SM_16K | HV_CTX_PG_SM_64K".
414 HV_SYSCONF_VALID_PAGE_SIZES = 7,
418 /** Offset to subtract from returned Kelvin temperature to get degrees
420 #define HV_SYSCONF_TEMP_KTOC 273
422 /** Pseudo-temperature value indicating that the temperature has
423 * pegged at its upper limit and is no longer accurate; note that this is
424 * the value after subtracting HV_SYSCONF_TEMP_KTOC. */
425 #define HV_SYSCONF_OVERTEMP 999
427 /** Query a configuration value from the hypervisor.
428 * @param query Which value is requested (HV_SYSCONF_xxx).
429 * @return The requested value, or -1 the requested value is illegal or
432 long hv_sysconf(HV_SysconfQuery query);
435 /** Queries we can make for hv_confstr().
437 * These numbers are part of the binary API and guaranteed not to change.
440 /** An invalid value; do not use. */
441 _HV_CONFSTR_RESERVED = 0,
443 /** Board part number. */
444 HV_CONFSTR_BOARD_PART_NUM = 1,
446 /** Board serial number. */
447 HV_CONFSTR_BOARD_SERIAL_NUM = 2,
449 /** Chip serial number. */
450 HV_CONFSTR_CHIP_SERIAL_NUM = 3,
452 /** Board revision level. */
453 HV_CONFSTR_BOARD_REV = 4,
455 /** Hypervisor software version. */
456 HV_CONFSTR_HV_SW_VER = 5,
458 /** The name for this chip model. */
459 HV_CONFSTR_CHIP_MODEL = 6,
461 /** Human-readable board description. */
462 HV_CONFSTR_BOARD_DESC = 7,
464 /** Human-readable description of the hypervisor configuration. */
465 HV_CONFSTR_HV_CONFIG = 8,
467 /** Human-readable version string for the boot image (for instance,
468 * who built it and when, what configuration file was used). */
469 HV_CONFSTR_HV_CONFIG_VER = 9,
471 /** Mezzanine part number. */
472 HV_CONFSTR_MEZZ_PART_NUM = 10,
474 /** Mezzanine serial number. */
475 HV_CONFSTR_MEZZ_SERIAL_NUM = 11,
477 /** Mezzanine revision level. */
478 HV_CONFSTR_MEZZ_REV = 12,
480 /** Human-readable mezzanine description. */
481 HV_CONFSTR_MEZZ_DESC = 13,
483 /** Control path for the onboard network switch. */
484 HV_CONFSTR_SWITCH_CONTROL = 14,
486 /** Chip revision level. */
487 HV_CONFSTR_CHIP_REV = 15
491 /** Query a configuration string from the hypervisor.
493 * @param query Identifier for the specific string to be retrieved
495 * @param buf Buffer in which to place the string.
496 * @param len Length of the buffer.
497 * @return If query is valid, then the length of the corresponding string,
498 * including the trailing null; if this is greater than len, the string
499 * was truncated. If query is invalid, HV_EINVAL. If the specified
500 * buffer is not writable by the client, HV_EFAULT.
502 int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len);
504 /** Tile coordinate */
507 #ifndef __BIG_ENDIAN__
508 /** X coordinate, relative to supervisor's top-left coordinate */
511 /** Y coordinate, relative to supervisor's top-left coordinate */
522 /** Get the PTE for sending an IPI to a particular tile.
524 * @param tile Tile which will receive the IPI.
525 * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1.
526 * @param pte Filled with resulting PTE.
527 * @result Zero if no error, non-zero for invalid parameters.
529 int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
531 #else /* !CHIP_HAS_IPI() */
533 /** A set of interrupts. */
534 typedef __hv32 HV_IntrMask;
536 /** The low interrupt numbers are reserved for use by the client in
537 * delivering IPIs. Any interrupt numbers higher than this value are
538 * reserved for use by HV device drivers. */
539 #define HV_MAX_IPI_INTERRUPT 7
541 /** Enable a set of device interrupts.
543 * @param enab_mask Bitmap of interrupts to enable.
545 void hv_enable_intr(HV_IntrMask enab_mask);
547 /** Disable a set of device interrupts.
549 * @param disab_mask Bitmap of interrupts to disable.
551 void hv_disable_intr(HV_IntrMask disab_mask);
553 /** Clear a set of device interrupts.
555 * @param clear_mask Bitmap of interrupts to clear.
557 void hv_clear_intr(HV_IntrMask clear_mask);
559 /** Raise a set of device interrupts.
561 * @param raise_mask Bitmap of interrupts to raise.
563 void hv_raise_intr(HV_IntrMask raise_mask);
565 /** Trigger a one-shot interrupt on some tile
567 * @param tile Which tile to interrupt.
568 * @param interrupt Interrupt number to trigger; must be between 0 and
569 * HV_MAX_IPI_INTERRUPT.
570 * @return HV_OK on success, or a hypervisor error code.
572 HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
574 #endif /* !CHIP_HAS_IPI() */
576 /** Store memory mapping in debug memory so that external debugger can read it.
577 * A maximum of 16 entries can be stored.
579 * @param va VA of memory that is mapped.
580 * @param len Length of mapped memory.
581 * @param pa PA of memory that is mapped.
582 * @return 0 on success, -1 if the maximum number of mappings is exceeded.
584 int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa);
586 /** Given a client PA and a length, return its real (HV) PA.
588 * @param cpa Client physical address.
589 * @param len Length of mapped memory.
590 * @return physical address, or -1 if cpa or len is not valid.
592 HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len);
594 /** RTC return flag for no RTC chip present.
596 #define HV_RTC_NO_CHIP 0x1
598 /** RTC return flag for low-voltage condition, indicating that battery had
599 * died and time read is unreliable.
601 #define HV_RTC_LOW_VOLTAGE 0x2
603 /** Date/Time of day */
605 #if CHIP_WORD_SIZE() > 32
606 __hv64 tm_sec; /**< Seconds, 0-59 */
607 __hv64 tm_min; /**< Minutes, 0-59 */
608 __hv64 tm_hour; /**< Hours, 0-23 */
609 __hv64 tm_mday; /**< Day of month, 0-30 */
610 __hv64 tm_mon; /**< Month, 0-11 */
611 __hv64 tm_year; /**< Years since 1900, 0-199 */
612 __hv64 flags; /**< Return flags, 0 if no error */
614 __hv32 tm_sec; /**< Seconds, 0-59 */
615 __hv32 tm_min; /**< Minutes, 0-59 */
616 __hv32 tm_hour; /**< Hours, 0-23 */
617 __hv32 tm_mday; /**< Day of month, 0-30 */
618 __hv32 tm_mon; /**< Month, 0-11 */
619 __hv32 tm_year; /**< Years since 1900, 0-199 */
620 __hv32 flags; /**< Return flags, 0 if no error */
624 /** Read the current time-of-day clock.
625 * @return HV_RTCTime of current time (GMT).
627 HV_RTCTime hv_get_rtc(void);
630 /** Set the current time-of-day clock.
631 * @param time time to reset time-of-day to (GMT).
633 void hv_set_rtc(HV_RTCTime time);
635 /** Installs a context, comprising a page table and other attributes.
637 * Once this service completes, page_table will be used to translate
638 * subsequent virtual address references to physical memory.
640 * Installing a context does not cause an implicit TLB flush. Before
641 * reusing an ASID value for a different address space, the client is
642 * expected to flush old references from the TLB with hv_flush_asid().
643 * (Alternately, hv_flush_all() may be used to flush many ASIDs at once.)
644 * After invalidating a page table entry, changing its attributes, or
645 * changing its target CPA, the client is expected to flush old references
646 * from the TLB with hv_flush_page() or hv_flush_pages(). Making a
647 * previously invalid page valid does not require a flush.
649 * Specifying an invalid ASID, or an invalid CPA (client physical address)
650 * (either as page_table_pointer, or within the referenced table),
651 * or another page table data item documented as above as illegal may
652 * lead to client termination; since the validation of the table is
653 * done as needed, this may happen before the service returns, or at
654 * some later time, or never, depending upon the client's pattern of
655 * memory references. Page table entries which supply translations for
656 * invalid virtual addresses may result in client termination, or may
657 * be silently ignored. "Invalid" in this context means a value which
658 * was not provided to the client via the appropriate hv_inquire_* routine.
660 * To support changing the instruction VAs at the same time as
661 * installing the new page table, this call explicitly supports
662 * setting the "lr" register to a different address and then jumping
663 * directly to the hv_install_context() routine. In this case, the
664 * new page table does not need to contain any mapping for the
665 * hv_install_context address itself.
667 * At most one HV_CTX_PG_SM_* flag may be specified in "flags";
668 * if multiple flags are specified, HV_EINVAL is returned.
669 * Specifying none of the flags results in using the default page size.
670 * All cores participating in a given client must request the same
671 * page size, or the results are undefined.
673 * @param page_table Root of the page table.
674 * @param access PTE providing info on how to read the page table. This
675 * value must be consistent between multiple tiles sharing a page table,
676 * and must also be consistent with any virtual mappings the client
677 * may be using to access the page table.
678 * @param asid HV_ASID the page table is to be used for.
679 * @param flags Context flags, denoting attributes or privileges of the
680 * current context (HV_CTX_xxx).
681 * @return Zero on success, or a hypervisor error code on failure.
683 int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid,
686 #endif /* !__ASSEMBLER__ */
688 #define HV_CTX_DIRECTIO 0x1 /**< Direct I/O requests are accepted from
691 #define HV_CTX_PG_SM_4K 0x10 /**< Use 4K small pages, if available. */
692 #define HV_CTX_PG_SM_16K 0x20 /**< Use 16K small pages, if available. */
693 #define HV_CTX_PG_SM_64K 0x40 /**< Use 64K small pages, if available. */
694 #define HV_CTX_PG_SM_MASK 0xf0 /**< Mask of all possible small pages. */
696 #ifndef __ASSEMBLER__
698 /** Value returned from hv_inquire_context(). */
701 /** Physical address of page table */
702 HV_PhysAddr page_table;
704 /** PTE which defines access method for top of page table */
707 /** ASID associated with this page table */
714 /** Retrieve information about the currently installed context.
715 * @return The data passed to the last successful hv_install_context call.
717 HV_Context hv_inquire_context(void);
720 /** Flushes all translations associated with the named address space
721 * identifier from the TLB and any other hypervisor data structures.
722 * Translations installed with the "global" bit are not flushed.
724 * Specifying an invalid ASID may lead to client termination. "Invalid"
725 * in this context means a value which was not provided to the client
726 * via <tt>hv_inquire_asid()</tt>.
728 * @param asid HV_ASID whose entries are to be flushed.
729 * @return Zero on success, or a hypervisor error code on failure.
731 int hv_flush_asid(HV_ASID asid);
734 /** Flushes all translations associated with the named virtual address
735 * and page size from the TLB and other hypervisor data structures. Only
736 * pages visible to the current ASID are affected; note that this includes
737 * global pages in addition to pages specific to the current ASID.
739 * The supplied VA need not be aligned; it may be anywhere in the
742 * Specifying an invalid virtual address may lead to client termination,
743 * or may silently succeed. "Invalid" in this context means a value
744 * which was not provided to the client via hv_inquire_virtual.
746 * @param address Address of the page to flush.
747 * @param page_size Size of pages to assume.
748 * @return Zero on success, or a hypervisor error code on failure.
750 int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size);
753 /** Flushes all translations associated with the named virtual address range
754 * and page size from the TLB and other hypervisor data structures. Only
755 * pages visible to the current ASID are affected; note that this includes
756 * global pages in addition to pages specific to the current ASID.
758 * The supplied VA need not be aligned; it may be anywhere in the
761 * Specifying an invalid virtual address may lead to client termination,
762 * or may silently succeed. "Invalid" in this context means a value
763 * which was not provided to the client via hv_inquire_virtual.
765 * @param start Address to flush.
766 * @param page_size Size of pages to assume.
767 * @param size The number of bytes to flush. Any page in the range
768 * [start, start + size) will be flushed from the TLB.
769 * @return Zero on success, or a hypervisor error code on failure.
771 int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size,
775 /** Flushes all non-global translations (if preserve_global is true),
776 * or absolutely all translations (if preserve_global is false).
778 * @param preserve_global Non-zero if we want to preserve "global" mappings.
779 * @return Zero on success, or a hypervisor error code on failure.
781 int hv_flush_all(int preserve_global);
784 /** Restart machine with optional restart command and optional args.
785 * @param cmd Const pointer to command to restart with, or NULL
786 * @param args Const pointer to argument string to restart with, or NULL
788 void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args);
795 /** Power off machine. */
796 void hv_power_off(void);
799 /** Re-enter virtual-is-physical memory translation mode and restart
800 * execution at a given address.
801 * @param entry Client physical address at which to begin execution.
802 * @return A hypervisor error code on failure; if the operation is
803 * successful the call does not return.
805 int hv_reexec(HV_PhysAddr entry);
811 /** Relative coordinates of the querying tile */
814 /** Width of the querying supervisor's tile rectangle. */
817 /** Height of the querying supervisor's tile rectangle. */
822 /** Returns information about the tile coordinate system.
824 * Each supervisor is given a rectangle of tiles it potentially controls.
825 * These tiles are labeled using a relative coordinate system with (0,0) as
826 * the upper left tile regardless of their physical location on the chip.
828 * This call returns both the size of that rectangle and the position
829 * within that rectangle of the querying tile.
831 * Not all tiles within that rectangle may be available to the supervisor;
832 * to get the precise set of available tiles, you must also call
833 * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...).
835 HV_Topology hv_inquire_topology(void);
837 /** Sets of tiles we can retrieve with hv_inquire_tiles().
839 * These numbers are part of the binary API and guaranteed not to change.
842 /** An invalid value; do not use. */
843 _HV_INQ_TILES_RESERVED = 0,
845 /** All available tiles within the supervisor's tile rectangle. */
846 HV_INQ_TILES_AVAIL = 1,
848 /** The set of tiles used for hash-for-home caching. */
849 HV_INQ_TILES_HFH_CACHE = 2,
851 /** The set of tiles that can be legally used as a LOTAR for a PTE. */
852 HV_INQ_TILES_LOTAR = 3
855 /** Returns specific information about various sets of tiles within the
856 * supervisor's tile rectangle.
858 * @param set Which set of tiles to retrieve.
859 * @param cpumask Pointer to a returned bitmask (in row-major order,
860 * supervisor-relative) of tiles. The low bit of the first word
861 * corresponds to the tile at the upper left-hand corner of the
862 * supervisor's rectangle. In order for the supervisor to know the
863 * buffer length to supply, it should first call hv_inquire_topology.
864 * @param length Number of bytes available for the returned bitmask.
866 HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length);
869 /** An identifier for a memory controller. Multiple memory controllers
870 * may be connected to one chip, and this uniquely identifies each one.
872 typedef int HV_MemoryController;
874 /** A range of physical memory. */
877 HV_PhysAddr start; /**< Starting address. */
878 __hv64 size; /**< Size in bytes. */
879 HV_MemoryController controller; /**< Which memory controller owns this. */
882 /** Returns information about a range of physical memory.
884 * hv_inquire_physical() returns one of the ranges of client
885 * physical addresses which are available to this client.
887 * The first range is retrieved by specifying an idx of 0, and
888 * successive ranges are returned with subsequent idx values. Ranges
889 * are ordered by increasing start address (i.e., as idx increases,
890 * so does start), do not overlap, and do not touch (i.e., the
891 * available memory is described with the fewest possible ranges).
893 * If an out-of-range idx value is specified, the returned size will be zero.
894 * A client can count the number of ranges by increasing idx until the
895 * returned size is zero. There will always be at least one valid range.
897 * Some clients might not be prepared to deal with more than one
898 * physical address range; they still ought to call this routine and
899 * issue a warning message if they're given more than one range, on the
900 * theory that whoever configured the hypervisor to provide that memory
901 * should know that it's being wasted.
903 HV_PhysAddrRange hv_inquire_physical(int idx);
905 /** Possible DIMM types. */
908 NO_DIMM = 0, /**< No DIMM */
909 DDR2 = 1, /**< DDR2 */
910 DDR3 = 2 /**< DDR3 */
915 /** Log2 of minimum DIMM bytes supported by the memory controller. */
916 #define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
918 /** Max number of DIMMs contained by one memory controller. */
919 #define HV_MSH_MAX_DIMMS 8
923 /** Log2 of minimum DIMM bytes supported by the memory controller. */
924 #define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
926 /** Max number of DIMMs contained by one memory controller. */
927 #define HV_MSH_MAX_DIMMS 2
931 /** Number of bits to right-shift to get the DIMM type. */
932 #define HV_DIMM_TYPE_SHIFT 0
934 /** Bits to mask to get the DIMM type. */
935 #define HV_DIMM_TYPE_MASK 0xf
937 /** Number of bits to right-shift to get the DIMM size. */
938 #define HV_DIMM_SIZE_SHIFT 4
940 /** Bits to mask to get the DIMM size. */
941 #define HV_DIMM_SIZE_MASK 0xf
943 /** Memory controller information. */
946 HV_Coord coord; /**< Relative tile coordinates of the port used by a
947 specified tile to communicate with this controller. */
948 __hv64 speed; /**< Speed of this controller in bytes per second. */
949 } HV_MemoryControllerInfo;
951 /** Returns information about a particular memory controller.
953 * hv_inquire_memory_controller(coord,idx) returns information about a
954 * particular controller. Two pieces of information are returned:
955 * - The relative coordinates of the port on the controller that the specified
956 * tile would use to contact it. The relative coordinates may lie
957 * outside the supervisor's rectangle, i.e. the controller may not
958 * be attached to a node managed by the querying node's supervisor.
959 * In particular note that x or y may be negative.
960 * - The speed of the memory controller. (This is a not-to-exceed value
961 * based on the raw hardware data rate, and may not be achievable in
962 * practice; it is provided to give clients information on the relative
963 * performance of the available controllers.)
965 * Clients should avoid calling this interface with invalid values.
966 * A client who does may be terminated.
967 * @param coord Tile for which to calculate the relative port position.
968 * @param controller Index of the controller; identical to value returned
969 * from other routines like hv_inquire_physical.
970 * @return Information about the controller.
972 HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord,
976 /** A range of virtual memory. */
979 HV_VirtAddr start; /**< Starting address. */
980 __hv64 size; /**< Size in bytes. */
983 /** Returns information about a range of virtual memory.
985 * hv_inquire_virtual() returns one of the ranges of client
986 * virtual addresses which are available to this client.
988 * The first range is retrieved by specifying an idx of 0, and
989 * successive ranges are returned with subsequent idx values. Ranges
990 * are ordered by increasing start address (i.e., as idx increases,
991 * so does start), do not overlap, and do not touch (i.e., the
992 * available memory is described with the fewest possible ranges).
994 * If an out-of-range idx value is specified, the returned size will be zero.
995 * A client can count the number of ranges by increasing idx until the
996 * returned size is zero. There will always be at least one valid range.
998 * Some clients may well have various virtual addresses hardwired
999 * into themselves; for instance, their instruction stream may
1000 * have been compiled expecting to live at a particular address.
1001 * Such clients should use this interface to verify they've been
1002 * given the virtual address space they expect, and issue a (potentially
1003 * fatal) warning message otherwise.
1005 * Note that the returned size is a __hv64, not a __hv32, so it is
1006 * possible to express a single range spanning the entire 32-bit
1009 HV_VirtAddrRange hv_inquire_virtual(int idx);
1012 /** A range of ASID values. */
1015 #ifndef __BIG_ENDIAN__
1016 HV_ASID start; /**< First ASID in the range. */
1017 unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */
1019 unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */
1020 HV_ASID start; /**< First ASID in the range. */
1024 /** Returns information about a range of ASIDs.
1026 * hv_inquire_asid() returns one of the ranges of address
1027 * space identifiers which are available to this client.
1029 * The first range is retrieved by specifying an idx of 0, and
1030 * successive ranges are returned with subsequent idx values. Ranges
1031 * are ordered by increasing start value (i.e., as idx increases,
1032 * so does start), do not overlap, and do not touch (i.e., the
1033 * available ASIDs are described with the fewest possible ranges).
1035 * If an out-of-range idx value is specified, the returned size will be zero.
1036 * A client can count the number of ranges by increasing idx until the
1037 * returned size is zero. There will always be at least one valid range.
1039 HV_ASIDRange hv_inquire_asid(int idx);
1042 /** Waits for at least the specified number of nanoseconds then returns.
1044 * NOTE: this deprecated function currently assumes a 750 MHz clock,
1045 * and is thus not generally suitable for use. New code should call
1046 * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for,
1047 * and delay by looping while checking the cycle counter SPR.
1049 * @param nanosecs The number of nanoseconds to sleep.
1051 void hv_nanosleep(int nanosecs);
1054 /** Reads a character from the console without blocking.
1056 * @return A value from 0-255 indicates the value successfully read.
1057 * A negative value means no value was ready.
1059 int hv_console_read_if_ready(void);
1062 /** Writes a character to the console, blocking if the console is busy.
1064 * This call cannot fail. If the console is broken for some reason,
1065 * output will simply vanish.
1066 * @param byte Character to write.
1068 void hv_console_putc(int byte);
1071 /** Writes a string to the console, blocking if the console is busy.
1072 * @param bytes Pointer to characters to write.
1073 * @param len Number of characters to write.
1074 * @return Number of characters written, or HV_EFAULT if the buffer is invalid.
1076 int hv_console_write(HV_VirtAddr bytes, int len);
1079 /** Dispatch the next interrupt from the client downcall mechanism.
1081 * The hypervisor uses downcalls to notify the client of asynchronous
1082 * events. Some of these events are hypervisor-created (like incoming
1083 * messages). Some are regular interrupts which initially occur in
1084 * the hypervisor, and are normally handled directly by the client;
1085 * when these occur in a client's interrupt critical section, they must
1086 * be delivered through the downcall mechanism.
1088 * A downcall is initially delivered to the client as an INTCTRL_CL
1089 * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL
1090 * vector, the client must immediately invoke the hv_downcall_dispatch
1091 * service. This service will not return; instead it will cause one of
1092 * the client's actual downcall-handling interrupt vectors to be entered.
1093 * The EX_CONTEXT registers in the client will be set so that when the
1094 * client irets, it will return to the code which was interrupted by the
1095 * INTCTRL_CL interrupt.
1097 * Under some circumstances, the firing of INTCTRL_CL can race with
1098 * the lowering of a device interrupt. In such a case, the
1099 * hv_downcall_dispatch service may issue an iret instruction instead
1100 * of entering one of the client's actual downcall-handling interrupt
1101 * vectors. This will return execution to the location that was
1102 * interrupted by INTCTRL_CL.
1104 * Any saving of registers should be done by the actual handling
1105 * vectors; no registers should be changed by the INTCTRL_CL handler.
1106 * In particular, the client should not use a jal instruction to invoke
1107 * the hv_downcall_dispatch service, as that would overwrite the client's
1108 * lr register. Note that the hv_downcall_dispatch service may overwrite
1109 * one or more of the client's system save registers.
1111 * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor
1112 * will set this register to cause a downcall to happen, and will clear
1113 * it when no further downcalls are pending.
1115 * When a downcall vector is entered, the INTCTRL_CL interrupt will be
1116 * masked. When the client is done processing a downcall, and is ready
1117 * to accept another, it must unmask this interrupt; if more downcalls
1118 * are pending, this will cause the INTCTRL_CL vector to be reentered.
1119 * Currently the following interrupt vectors can be entered through a
1122 * INT_MESSAGE_RCV_DWNCL (hypervisor message available)
1123 * INT_DEV_INTR_DWNCL (device interrupt)
1124 * INT_DMATLB_MISS_DWNCL (DMA TLB miss)
1125 * INT_SNITLB_MISS_DWNCL (SNI TLB miss)
1126 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
1128 void hv_downcall_dispatch(void);
1130 #endif /* !__ASSEMBLER__ */
1132 /** We use actual interrupt vectors which never occur (they're only there
1133 * to allow setting MPLs for related SPRs) for our downcall vectors.
1135 /** Message receive downcall interrupt vector */
1136 #define INT_MESSAGE_RCV_DWNCL INT_BOOT_ACCESS
1137 /** DMA TLB miss downcall interrupt vector */
1138 #define INT_DMATLB_MISS_DWNCL INT_DMA_ASID
1139 /** Static nework processor instruction TLB miss interrupt vector */
1140 #define INT_SNITLB_MISS_DWNCL INT_SNI_ASID
1141 /** DMA TLB access violation downcall interrupt vector */
1142 #define INT_DMATLB_ACCESS_DWNCL INT_DMA_CPL
1143 /** Device interrupt downcall interrupt vector */
1144 #define INT_DEV_INTR_DWNCL INT_WORLD_ACCESS
1146 #ifndef __ASSEMBLER__
1148 /** Requests the inode for a specific full pathname.
1150 * Performs a lookup in the hypervisor filesystem for a given filename.
1151 * Multiple calls with the same filename will always return the same inode.
1152 * If there is no such filename, HV_ENOENT is returned.
1153 * A bad filename pointer may result in HV_EFAULT instead.
1155 * @param filename Constant pointer to name of requested file
1156 * @return Inode of requested file
1158 int hv_fs_findfile(HV_VirtAddr filename);
1161 /** Data returned from an fstat request.
1162 * Note that this structure should be no more than 40 bytes in size so
1163 * that it can always be returned completely in registers.
1167 int size; /**< Size of file (or HV_Errno on error) */
1168 unsigned int flags; /**< Flags (see HV_FS_FSTAT_FLAGS) */
1171 /** Bitmask flags for fstat request */
1174 HV_FS_ISDIR = 0x0001 /**< Is the entry a directory? */
1175 } HV_FS_FSTAT_FLAGS;
1177 /** Get stat information on a given file inode.
1179 * Return information on the file with the given inode.
1181 * IF the HV_FS_ISDIR bit is set, the "file" is a directory. Reading
1182 * it will return NUL-separated filenames (no directory part) relative
1183 * to the path to the inode of the directory "file". These can be
1184 * appended to the path to the directory "file" after a forward slash
1185 * to create additional filenames. Note that it is not required
1186 * that all valid paths be decomposable into valid parent directories;
1187 * a filesystem may validly have just a few files, none of which have
1188 * HV_FS_ISDIR set. However, if clients may wish to enumerate the
1189 * files in the filesystem, it is recommended to include all the
1190 * appropriate parent directory "files" to give a consistent view.
1192 * An invalid file inode will cause an HV_EBADF error to be returned.
1194 * @param inode The inode number of the query
1195 * @return An HV_FS_StatInfo structure
1197 HV_FS_StatInfo hv_fs_fstat(int inode);
1200 /** Read data from a specific hypervisor file.
1201 * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf.
1202 * Reads near the end of the file will return fewer bytes than requested.
1203 * Reads at or beyond the end of a file will return zero.
1205 * @param inode the hypervisor file to read
1206 * @param buf the buffer to read data into
1207 * @param length the number of bytes of data to read
1208 * @param offset the offset into the file to read the data from
1209 * @return number of bytes successfully read, or an HV_Errno code
1211 int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset);
1214 /** Read a 64-bit word from the specified physical address.
1215 * The address must be 8-byte aligned.
1216 * Specifying an invalid physical address will lead to client termination.
1217 * @param addr The physical address to read
1218 * @param access The PTE describing how to read the memory
1219 * @return The 64-bit value read from the given address
1221 unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access);
1224 /** Write a 64-bit word to the specified physical address.
1225 * The address must be 8-byte aligned.
1226 * Specifying an invalid physical address will lead to client termination.
1227 * @param addr The physical address to write
1228 * @param access The PTE that says how to write the memory
1229 * @param val The 64-bit value to write to the given address
1231 void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access,
1232 unsigned long long val);
1235 /** Get the value of the command-line for the supervisor, if any.
1236 * This will not include the filename of the booted supervisor, but may
1237 * include configured-in boot arguments or the hv_restart() arguments.
1238 * If the buffer is not long enough the hypervisor will NUL the first
1239 * character of the buffer but not write any other data.
1240 * @param buf The virtual address to write the command-line string to.
1241 * @param length The length of buf, in characters.
1242 * @return The actual length of the command line, including the trailing NUL
1243 * (may be larger than "length").
1245 int hv_get_command_line(HV_VirtAddr buf, int length);
1248 /** Set a new value for the command-line for the supervisor, which will
1249 * be returned from subsequent invocations of hv_get_command_line() on
1251 * @param buf The virtual address to read the command-line string from.
1252 * @param length The length of buf, in characters; must be no more than
1253 * HV_COMMAND_LINE_LEN.
1254 * @return Zero if successful, or a hypervisor error code.
1256 HV_Errno hv_set_command_line(HV_VirtAddr buf, int length);
1258 /** Maximum size of a command line passed to hv_set_command_line(); note
1259 * that a line returned from hv_get_command_line() could be larger than
1261 #define HV_COMMAND_LINE_LEN 256
1263 /** Tell the hypervisor how to cache non-priority pages
1264 * (its own as well as pages explicitly represented in page tables).
1265 * Normally these will be represented as red/black pages, but
1266 * when the supervisor starts to allocate "priority" pages in the PTE
1267 * the hypervisor will need to start marking those pages as (e.g.) "red"
1268 * and non-priority pages as either "black" (if they cache-alias
1269 * with the existing priority pages) or "red/black" (if they don't).
1270 * The bitmask provides information on which parts of the cache
1271 * have been used for pinned pages so far on this tile; if (1 << N)
1272 * appears in the bitmask, that indicates that a 4KB region of the
1273 * cache starting at (N * 4KB) is in use by a "priority" page.
1274 * The portion of cache used by a particular page can be computed
1275 * by taking the page's PA, modulo CHIP_L2_CACHE_SIZE(), and setting
1276 * all the "4KB" bits corresponding to the actual page size.
1277 * @param bitmask A bitmap of priority page set values
1279 void hv_set_caching(unsigned long bitmask);
1282 /** Zero out a specified number of pages.
1283 * The va and size must both be multiples of 4096.
1284 * Caches are bypassed and memory is directly set to zero.
1285 * This API is implemented only in the magic hypervisor and is intended
1286 * to provide a performance boost to the minimal supervisor by
1287 * giving it a fast way to zero memory pages when allocating them.
1288 * @param va Virtual address where the page has been mapped
1289 * @param size Number of bytes (must be a page size multiple)
1291 void hv_bzero_page(HV_VirtAddr va, unsigned int size);
1294 /** State object for the hypervisor messaging subsystem. */
1297 #if CHIP_VA_WIDTH() > 32
1298 __hv64 opaque[2]; /**< No user-serviceable parts inside */
1300 __hv32 opaque[2]; /**< No user-serviceable parts inside */
1305 /** Register to receive incoming messages.
1307 * This routine configures the current tile so that it can receive
1308 * incoming messages. It must be called before the client can receive
1309 * messages with the hv_receive_message routine, and must be called on
1310 * each tile which will receive messages.
1312 * msgstate is the virtual address of a state object of type HV_MsgState.
1313 * Once the state is registered, the client must not read or write the
1314 * state object; doing so will cause undefined results.
1316 * If this routine is called with msgstate set to 0, the client's message
1317 * state will be freed and it will no longer be able to receive messages.
1318 * Note that this may cause the loss of any as-yet-undelivered messages
1321 * If another client attempts to send a message to a client which has
1322 * not yet called hv_register_message_state, or which has freed its
1323 * message state, the message will not be delivered, as if the client
1324 * had insufficient buffering.
1326 * This routine returns HV_OK if the registration was successful, and
1327 * HV_EINVAL if the supplied state object is unsuitable. Note that some
1328 * errors may not be detected during this routine, but might be detected
1329 * during a subsequent message delivery.
1330 * @param msgstate State object.
1332 HV_Errno hv_register_message_state(HV_MsgState* msgstate);
1334 /** Possible message recipient states. */
1337 HV_TO_BE_SENT, /**< Not sent (not attempted, or recipient not ready) */
1338 HV_SENT, /**< Successfully sent */
1339 HV_BAD_RECIP /**< Bad recipient coordinates (permanent error) */
1342 /** Message recipient. */
1345 #ifndef __BIG_ENDIAN__
1346 /** X coordinate, relative to supervisor's top-left coordinate */
1349 /** Y coordinate, relative to supervisor's top-left coordinate */
1352 /** Status of this recipient */
1353 HV_Recip_State state:10;
1354 #else //__BIG_ENDIAN__
1355 HV_Recip_State state:10;
1361 /** Send a message to a set of recipients.
1363 * This routine sends a message to a set of recipients.
1365 * recips is an array of HV_Recipient structures. Each specifies a tile,
1366 * and a message state; initially, it is expected that the state will
1367 * be set to HV_TO_BE_SENT. nrecip specifies the number of recipients
1368 * in the recips array.
1370 * For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts
1371 * to send that tile the specified message. In order to successfully
1372 * receive the message, the receiver must be a valid tile to which the
1373 * sender has access, must not be the sending tile itself, and must have
1374 * sufficient free buffer space. (The hypervisor guarantees that each
1375 * tile which has called hv_register_message_state() will be able to
1376 * buffer one message from every other tile which can legally send to it;
1377 * more space may be provided but is not guaranteed.) If an invalid tile
1378 * is specified, the recipient's state is set to HV_BAD_RECIP; this is a
1379 * permanent delivery error. If the message is successfully delivered
1380 * to the recipient's buffer, the recipient's state is set to HV_SENT.
1381 * Otherwise, the recipient's state is unchanged. Message delivery is
1382 * synchronous; all attempts to send messages are completed before this
1385 * If no permanent delivery errors were encountered, the routine returns
1386 * the number of messages successfully sent: that is, the number of
1387 * recipients whose states changed from HV_TO_BE_SENT to HV_SENT during
1388 * this operation. If any permanent delivery errors were encountered,
1389 * the routine returns HV_ERECIP. In the event of permanent delivery
1390 * errors, it may be the case that delivery was not attempted to all
1391 * recipients; if any messages were successfully delivered, however,
1392 * recipients' state values will be updated appropriately.
1394 * It is explicitly legal to specify a recipient structure whose state
1395 * is not HV_TO_BE_SENT; such a recipient is ignored. One suggested way
1396 * of using hv_send_message to send a message to multiple tiles is to set
1397 * up a list of recipients, and then call the routine repeatedly with the
1398 * same list, each time accumulating the number of messages successfully
1399 * sent, until all messages are sent, a permanent error is encountered,
1400 * or the desired number of attempts have been made. When used in this
1401 * way, the routine will deliver each message no more than once to each
1404 * Note that a message being successfully delivered to the recipient's
1405 * buffer space does not guarantee that it is received by the recipient,
1406 * either immediately or at any time in the future; the recipient might
1407 * never call hv_receive_message, or could register a different state
1408 * buffer, losing the message.
1410 * Specifying the same recipient more than once in the recipient list
1411 * is an error, which will not result in an error return but which may
1412 * or may not result in more than one message being delivered to the
1415 * buf and buflen specify the message to be sent. buf is a virtual address
1416 * which must be currently mapped in the client's page table; if not, the
1417 * routine returns HV_EFAULT. buflen must be greater than zero and less
1418 * than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the
1419 * number of tiles to which the sender has access; if not, the routine
1420 * returns HV_EINVAL.
1421 * @param recips List of recipients.
1422 * @param nrecip Number of recipients.
1423 * @param buf Address of message data.
1424 * @param buflen Length of message data.
1426 int hv_send_message(HV_Recipient *recips, int nrecip,
1427 HV_VirtAddr buf, int buflen);
1429 /** Maximum hypervisor message size, in bytes */
1430 #define HV_MAX_MESSAGE_SIZE 28
1433 /** Return value from hv_receive_message() */
1436 int msglen; /**< Message length in bytes, or an error code */
1437 __hv32 source; /**< Code identifying message sender (HV_MSG_xxx) */
1440 #define HV_MSG_TILE 0x0 /**< Message source is another tile */
1441 #define HV_MSG_INTR 0x1 /**< Message source is a driver interrupt */
1443 /** Receive a message.
1445 * This routine retrieves a message from the client's incoming message
1448 * Multiple messages sent from a particular sending tile to a particular
1449 * receiving tile are received in the order that they were sent; however,
1450 * no ordering is guaranteed between messages sent by different tiles.
1452 * Whenever the a client's message buffer is empty, the first message
1453 * subsequently received will cause the client's MESSAGE_RCV_DWNCL
1454 * interrupt vector to be invoked through the interrupt downcall mechanism
1455 * (see the description of the hv_downcall_dispatch() routine for details
1458 * Another message-available downcall will not occur until a call to
1459 * this routine is made when the message buffer is empty, and a message
1460 * subsequently arrives. Note that such a downcall could occur while
1461 * this routine is executing. If the calling code does not wish this
1462 * to happen, it is recommended that this routine be called with the
1463 * INTCTRL_1 interrupt masked, or inside an interrupt critical section.
1465 * msgstate is the value previously passed to hv_register_message_state().
1466 * buf is the virtual address of the buffer into which the message will
1467 * be written; buflen is the length of the buffer.
1469 * This routine returns an HV_RcvMsgInfo structure. The msglen member
1470 * of that structure is the length of the message received, zero if no
1471 * message is available, or HV_E2BIG if the message is too large for the
1472 * specified buffer. If the message is too large, it is not consumed,
1473 * and may be retrieved by a subsequent call to this routine specifying
1474 * a sufficiently large buffer. A buffer which is HV_MAX_MESSAGE_SIZE
1475 * bytes long is guaranteed to be able to receive any possible message.
1477 * The source member of the HV_RcvMsgInfo structure describes the sender
1478 * of the message. For messages sent by another client tile via an
1479 * hv_send_message() call, this value is HV_MSG_TILE; for messages sent
1480 * as a result of a device interrupt, this value is HV_MSG_INTR.
1483 HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf,
1487 /** Start remaining tiles owned by this supervisor. Initially, only one tile
1488 * executes the client program; after it calls this service, the other tiles
1489 * are started. This allows the initial tile to do one-time configuration
1490 * of shared data structures without having to lock them against simultaneous
1493 void hv_start_all_tiles(void);
1496 /** Open a hypervisor device.
1498 * This service initializes an I/O device and its hypervisor driver software,
1499 * and makes it available for use. The open operation is per-device per-chip;
1500 * once it has been performed, the device handle returned may be used in other
1501 * device services calls made by any tile.
1503 * @param name Name of the device. A base device name is just a text string
1504 * (say, "pcie"). If there is more than one instance of a device, the
1505 * base name is followed by a slash and a device number (say, "pcie/0").
1506 * Some devices may support further structure beneath those components;
1507 * most notably, devices which require control operations do so by
1508 * supporting reads and/or writes to a control device whose name
1509 * includes a trailing "/ctl" (say, "pcie/0/ctl").
1510 * @param flags Flags (HV_DEV_xxx).
1511 * @return A positive integer device handle, or a negative error code.
1513 int hv_dev_open(HV_VirtAddr name, __hv32 flags);
1516 /** Close a hypervisor device.
1518 * This service uninitializes an I/O device and its hypervisor driver
1519 * software, and makes it unavailable for use. The close operation is
1520 * per-device per-chip; once it has been performed, the device is no longer
1521 * available. Normally there is no need to ever call the close service.
1523 * @param devhdl Device handle of the device to be closed.
1524 * @return Zero if the close is successful, otherwise, a negative error code.
1526 int hv_dev_close(int devhdl);
1529 /** Read data from a hypervisor device synchronously.
1531 * This service transfers data from a hypervisor device to a memory buffer.
1532 * When the service returns, the data has been written from the memory buffer,
1533 * and the buffer will not be further modified by the driver.
1535 * No ordering is guaranteed between requests issued from different tiles.
1537 * Devices may choose to support both the synchronous and asynchronous read
1538 * operations, only one of them, or neither of them.
1540 * @param devhdl Device handle of the device to be read from.
1541 * @param flags Flags (HV_DEV_xxx).
1542 * @param va Virtual address of the target data buffer. This buffer must
1543 * be mapped in the currently installed page table; if not, HV_EFAULT
1545 * @param len Number of bytes to be transferred.
1546 * @param offset Driver-dependent offset. For a random-access device, this is
1547 * often a byte offset from the beginning of the device; in other cases,
1548 * like on a control device, it may have a different meaning.
1549 * @return A non-negative value if the read was at least partially successful;
1550 * otherwise, a negative error code. The precise interpretation of
1551 * the return value is driver-dependent, but many drivers will return
1552 * the number of bytes successfully transferred.
1554 int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1557 #define HV_DEV_NB_EMPTY 0x1 /**< Don't block when no bytes of data can
1559 #define HV_DEV_NB_PARTIAL 0x2 /**< Don't block when some bytes, but not all
1560 of the requested bytes, can be
1562 #define HV_DEV_NOCACHE 0x4 /**< The caller warrants that none of the
1563 cache lines which might contain data
1564 from the requested buffer are valid.
1565 Useful with asynchronous operations
1568 #define HV_DEV_ALLFLAGS (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \
1569 HV_DEV_NOCACHE) /**< All HV_DEV_xxx flags */
1571 /** Write data to a hypervisor device synchronously.
1573 * This service transfers data from a memory buffer to a hypervisor device.
1574 * When the service returns, the data has been read from the memory buffer,
1575 * and the buffer may be overwritten by the client; the data may not
1576 * necessarily have been conveyed to the actual hardware I/O interface.
1578 * No ordering is guaranteed between requests issued from different tiles.
1580 * Devices may choose to support both the synchronous and asynchronous write
1581 * operations, only one of them, or neither of them.
1583 * @param devhdl Device handle of the device to be written to.
1584 * @param flags Flags (HV_DEV_xxx).
1585 * @param va Virtual address of the source data buffer. This buffer must
1586 * be mapped in the currently installed page table; if not, HV_EFAULT
1588 * @param len Number of bytes to be transferred.
1589 * @param offset Driver-dependent offset. For a random-access device, this is
1590 * often a byte offset from the beginning of the device; in other cases,
1591 * like on a control device, it may have a different meaning.
1592 * @return A non-negative value if the write was at least partially successful;
1593 * otherwise, a negative error code. The precise interpretation of
1594 * the return value is driver-dependent, but many drivers will return
1595 * the number of bytes successfully transferred.
1597 int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1601 /** Interrupt arguments, used in the asynchronous I/O interfaces. */
1602 #if CHIP_VA_WIDTH() > 32
1603 typedef __hv64 HV_IntArg;
1605 typedef __hv32 HV_IntArg;
1608 /** Interrupt messages are delivered via the mechanism as normal messages,
1609 * but have a message source of HV_DEV_INTR. The message is formatted
1610 * as an HV_IntrMsg structure.
1615 HV_IntArg intarg; /**< Interrupt argument, passed to the poll/preada/pwritea
1617 HV_IntArg intdata; /**< Interrupt-specific interrupt data */
1620 /** Request an interrupt message when a device condition is satisfied.
1622 * This service requests that an interrupt message be delivered to the
1623 * requesting tile when a device becomes readable or writable, or when any
1624 * data queued to the device via previous write operations from this tile
1625 * has been actually sent out on the hardware I/O interface. Devices may
1626 * choose to support any, all, or none of the available conditions.
1628 * If multiple conditions are specified, only one message will be
1629 * delivered. If the event mask delivered to that interrupt handler
1630 * indicates that some of the conditions have not yet occurred, the
1631 * client must issue another poll() call if it wishes to wait for those
1634 * Only one poll may be outstanding per device handle per tile. If more than
1635 * one tile is polling on the same device and condition, they will all be
1636 * notified when it happens. Because of this, clients may not assume that
1637 * the condition signaled is necessarily still true when they request a
1638 * subsequent service; for instance, the readable data which caused the
1639 * poll call to interrupt may have been read by another tile in the interim.
1641 * The notification interrupt message could come directly, or via the
1642 * downcall (intctrl1) method, depending on what the tile is doing
1643 * when the condition is satisfied. Note that it is possible for the
1644 * requested interrupt to be delivered after this service is called but
1645 * before it returns.
1647 * @param devhdl Device handle of the device to be polled.
1648 * @param events Flags denoting the events which will cause the interrupt to
1649 * be delivered (HV_DEVPOLL_xxx).
1650 * @param intarg Value which will be delivered as the intarg member of the
1651 * eventual interrupt message; the intdata member will be set to a
1652 * mask of HV_DEVPOLL_xxx values indicating which conditions have been
1654 * @return Zero if the interrupt was successfully scheduled; otherwise, a
1655 * negative error code.
1657 int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg);
1659 #define HV_DEVPOLL_READ 0x1 /**< Test device for readability */
1660 #define HV_DEVPOLL_WRITE 0x2 /**< Test device for writability */
1661 #define HV_DEVPOLL_FLUSH 0x4 /**< Test device for output drained */
1664 /** Cancel a request for an interrupt when a device event occurs.
1666 * This service requests that no interrupt be delivered when the events
1667 * noted in the last-issued poll() call happen. Once this service returns,
1668 * the interrupt has been canceled; however, it is possible for the interrupt
1669 * to be delivered after this service is called but before it returns.
1671 * @param devhdl Device handle of the device on which to cancel polling.
1672 * @return Zero if the poll was successfully canceled; otherwise, a negative
1675 int hv_dev_poll_cancel(int devhdl);
1678 /** Scatter-gather list for preada/pwritea calls. */
1680 #if CHIP_VA_WIDTH() <= 32
1681 __attribute__ ((packed, aligned(4)))
1684 HV_PhysAddr pa; /**< Client physical address of the buffer segment. */
1685 HV_PTE pte; /**< Page table entry describing the caching and location
1686 override characteristics of the buffer segment. Some
1687 drivers ignore this element and will require that
1688 the NOCACHE flag be set on their requests. */
1689 __hv32 len; /**< Length of the buffer segment. */
1692 #define HV_SGL_MAXLEN 16 /**< Maximum number of entries in a scatter-gather
1695 /** Read data from a hypervisor device asynchronously.
1697 * This service transfers data from a hypervisor device to a memory buffer.
1698 * When the service returns, the read has been scheduled. When the read
1699 * completes, an interrupt message will be delivered, and the buffer will
1700 * not be further modified by the driver.
1702 * The number of possible outstanding asynchronous requests is defined by
1703 * each driver, but it is recommended that it be at least two requests
1704 * per tile per device.
1706 * No ordering is guaranteed between synchronous and asynchronous requests,
1707 * even those issued on the same tile.
1709 * The completion interrupt message could come directly, or via the downcall
1710 * (intctrl1) method, depending on what the tile is doing when the read
1711 * completes. Interrupts do not coalesce; one is delivered for each
1712 * asynchronous I/O request. Note that it is possible for the requested
1713 * interrupt to be delivered after this service is called but before it
1716 * Devices may choose to support both the synchronous and asynchronous read
1717 * operations, only one of them, or neither of them.
1719 * @param devhdl Device handle of the device to be read from.
1720 * @param flags Flags (HV_DEV_xxx).
1721 * @param sgl_len Number of elements in the scatter-gather list.
1722 * @param sgl Scatter-gather list describing the memory to which data will be
1724 * @param offset Driver-dependent offset. For a random-access device, this is
1725 * often a byte offset from the beginning of the device; in other cases,
1726 * like on a control device, it may have a different meaning.
1727 * @param intarg Value which will be delivered as the intarg member of the
1728 * eventual interrupt message; the intdata member will be set to the
1729 * normal return value from the read request.
1730 * @return Zero if the read was successfully scheduled; otherwise, a negative
1731 * error code. Note that some drivers may choose to pre-validate
1732 * their arguments, and may thus detect certain device error
1733 * conditions at this time rather than when the completion notification
1734 * occurs, but this is not required.
1736 int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len,
1737 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1740 /** Write data to a hypervisor device asynchronously.
1742 * This service transfers data from a memory buffer to a hypervisor
1743 * device. When the service returns, the write has been scheduled.
1744 * When the write completes, an interrupt message will be delivered,
1745 * and the buffer may be overwritten by the client; the data may not
1746 * necessarily have been conveyed to the actual hardware I/O interface.
1748 * The number of possible outstanding asynchronous requests is defined by
1749 * each driver, but it is recommended that it be at least two requests
1750 * per tile per device.
1752 * No ordering is guaranteed between synchronous and asynchronous requests,
1753 * even those issued on the same tile.
1755 * The completion interrupt message could come directly, or via the downcall
1756 * (intctrl1) method, depending on what the tile is doing when the read
1757 * completes. Interrupts do not coalesce; one is delivered for each
1758 * asynchronous I/O request. Note that it is possible for the requested
1759 * interrupt to be delivered after this service is called but before it
1762 * Devices may choose to support both the synchronous and asynchronous write
1763 * operations, only one of them, or neither of them.
1765 * @param devhdl Device handle of the device to be read from.
1766 * @param flags Flags (HV_DEV_xxx).
1767 * @param sgl_len Number of elements in the scatter-gather list.
1768 * @param sgl Scatter-gather list describing the memory from which data will be
1770 * @param offset Driver-dependent offset. For a random-access device, this is
1771 * often a byte offset from the beginning of the device; in other cases,
1772 * like on a control device, it may have a different meaning.
1773 * @param intarg Value which will be delivered as the intarg member of the
1774 * eventual interrupt message; the intdata member will be set to the
1775 * normal return value from the write request.
1776 * @return Zero if the write was successfully scheduled; otherwise, a negative
1777 * error code. Note that some drivers may choose to pre-validate
1778 * their arguments, and may thus detect certain device error
1779 * conditions at this time rather than when the completion notification
1780 * occurs, but this is not required.
1782 int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len,
1783 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1786 /** Define a pair of tile and ASID to identify a user process context. */
1789 /** X coordinate, relative to supervisor's top-left coordinate */
1792 /** Y coordinate, relative to supervisor's top-left coordinate */
1795 /** ASID of the process on this x,y tile */
1799 /** Flush cache and/or TLB state on remote tiles.
1801 * @param cache_pa Client physical address to flush from cache (ignored if
1802 * the length encoded in cache_control is zero, or if
1803 * HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL).
1804 * @param cache_control This argument allows you to specify a length of
1805 * physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
1806 * You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
1807 * You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
1808 * HV_FLUSH_ALL flushes all caches.
1809 * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
1810 * tile indices to perform cache flush on. The low bit of the first
1811 * word corresponds to the tile at the upper left-hand corner of the
1812 * supervisor's rectangle. If passed as a NULL pointer, equivalent
1813 * to an empty bitmask. On chips which support hash-for-home caching,
1814 * if passed as -1, equivalent to a mask containing tiles which could
1815 * be doing hash-for-home caching.
1816 * @param tlb_va Virtual address to flush from TLB (ignored if
1817 * tlb_length is zero or tlb_cpumask is NULL).
1818 * @param tlb_length Number of bytes of data to flush from the TLB.
1819 * @param tlb_pgsize Page size to use for TLB flushes.
1820 * tlb_va and tlb_length need not be aligned to this size.
1821 * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask.
1822 * If passed as a NULL pointer, equivalent to an empty bitmask.
1823 * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush.
1824 * @param asidcount Number of HV_Remote_ASID entries in asids[].
1825 * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that
1826 * are detected while parsing the arguments.
1828 int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control,
1829 unsigned long* cache_cpumask,
1830 HV_VirtAddr tlb_va, unsigned long tlb_length,
1831 unsigned long tlb_pgsize, unsigned long* tlb_cpumask,
1832 HV_Remote_ASID* asids, int asidcount);
1834 /** Include in cache_control to ensure a flush of the entire L2. */
1835 #define HV_FLUSH_EVICT_L2 (1UL << 31)
1837 /** Include in cache_control to ensure a flush of the entire L1I. */
1838 #define HV_FLUSH_EVICT_L1I (1UL << 30)
1840 /** Maximum legal size to use for the "length" component of cache_control. */
1841 #define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1)
1843 /** Use for cache_control to ensure a flush of all caches. */
1844 #define HV_FLUSH_ALL -1UL
1846 #else /* __ASSEMBLER__ */
1848 /** Include in cache_control to ensure a flush of the entire L2. */
1849 #define HV_FLUSH_EVICT_L2 (1 << 31)
1851 /** Include in cache_control to ensure a flush of the entire L1I. */
1852 #define HV_FLUSH_EVICT_L1I (1 << 30)
1854 /** Maximum legal size to use for the "length" component of cache_control. */
1855 #define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1)
1857 /** Use for cache_control to ensure a flush of all caches. */
1858 #define HV_FLUSH_ALL -1
1860 #endif /* __ASSEMBLER__ */
1862 #ifndef __ASSEMBLER__
1864 /** Return a 64-bit value corresponding to the PTE if needed */
1865 #define hv_pte_val(pte) ((pte).val)
1867 /** Cast a 64-bit value to an HV_PTE */
1868 #define hv_pte(val) ((HV_PTE) { val })
1870 #endif /* !__ASSEMBLER__ */
1873 /** Bits in the size of an HV_PTE */
1874 #define HV_LOG2_PTE_SIZE 3
1876 /** Size of an HV_PTE */
1877 #define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE)
1880 /* Bits in HV_PTE's low word. */
1881 #define HV_PTE_INDEX_PRESENT 0 /**< PTE is valid */
1882 #define HV_PTE_INDEX_MIGRATING 1 /**< Page is migrating */
1883 #define HV_PTE_INDEX_CLIENT0 2 /**< Page client state 0 */
1884 #define HV_PTE_INDEX_CLIENT1 3 /**< Page client state 1 */
1885 #define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */
1886 #define HV_PTE_INDEX_NO_ALLOC_L1 5 /**< Page is uncached in local L1$ */
1887 #define HV_PTE_INDEX_NO_ALLOC_L2 6 /**< Page is uncached in local L2$ */
1888 #define HV_PTE_INDEX_CACHED_PRIORITY 7 /**< Page is priority cached */
1889 #define HV_PTE_INDEX_PAGE 8 /**< PTE describes a page */
1890 #define HV_PTE_INDEX_GLOBAL 9 /**< Page is global */
1891 #define HV_PTE_INDEX_USER 10 /**< Page is user-accessible */
1892 #define HV_PTE_INDEX_ACCESSED 11 /**< Page has been accessed */
1893 #define HV_PTE_INDEX_DIRTY 12 /**< Page has been written */
1894 /* Bits 13-15 are reserved for
1896 #define HV_PTE_INDEX_MODE 16 /**< Page mode; see HV_PTE_MODE_xxx */
1897 #define HV_PTE_MODE_BITS 3 /**< Number of bits in mode */
1898 #define HV_PTE_INDEX_CLIENT2 19 /**< Page client state 2 */
1899 #define HV_PTE_INDEX_LOTAR 20 /**< Page's LOTAR; must be high bits
1901 #define HV_PTE_LOTAR_BITS 12 /**< Number of bits in a LOTAR */
1903 /* Bits in HV_PTE's high word. */
1904 #define HV_PTE_INDEX_READABLE 32 /**< Page is readable */
1905 #define HV_PTE_INDEX_WRITABLE 33 /**< Page is writable */
1906 #define HV_PTE_INDEX_EXECUTABLE 34 /**< Page is executable */
1907 #define HV_PTE_INDEX_PTFN 35 /**< Page's PTFN; must be high bits
1909 #define HV_PTE_PTFN_BITS 29 /**< Number of bits in a PTFN */
1912 * Legal values for the PTE's mode field
1914 /** Data is not resident in any caches; loads and stores access memory
1917 #define HV_PTE_MODE_UNCACHED 1
1919 /** Data is resident in the tile's local L1 and/or L2 caches; if a load
1920 * or store misses there, it goes to memory.
1922 * The copy in the local L1$/L2$ is not invalidated when the copy in
1923 * memory is changed.
1925 #define HV_PTE_MODE_CACHE_NO_L3 2
1927 /** Data is resident in the tile's local L1 and/or L2 caches. If a load
1928 * or store misses there, it goes to an L3 cache in a designated tile;
1929 * if it misses there, it goes to memory.
1931 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
1932 * when the copy in the remote L3$ is changed. Otherwise, such
1933 * invalidation will not occur.
1935 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
1936 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
1937 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
1939 #define HV_PTE_MODE_CACHE_TILE_L3 3
1941 /** Data is resident in the tile's local L1 and/or L2 caches. If a load
1942 * or store misses there, it goes to an L3 cache in one of a set of
1943 * designated tiles; if it misses there, it goes to memory. Which tile
1944 * is chosen from the set depends upon a hash function applied to the
1945 * physical address. This mode is not supported on chips for which
1946 * CHIP_HAS_CBOX_HOME_MAP() is 0.
1948 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
1949 * when the copy in the remote L3$ is changed. Otherwise, such
1950 * invalidation will not occur.
1952 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
1953 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
1954 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
1956 #define HV_PTE_MODE_CACHE_HASH_L3 4
1958 /** Data is not resident in memory; accesses are instead made to an I/O
1959 * device, whose tile coordinates are given by the PTE's LOTAR field.
1960 * This mode is only supported on chips for which CHIP_HAS_MMIO() is 1.
1961 * The EXECUTABLE bit may not be set in an MMIO PTE.
1963 #define HV_PTE_MODE_MMIO 5
1966 /* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers.
1967 * The assembler can't handle shifts greater than 31, but treats them
1968 * as shifts mod 32, so assembler code must be aware of which word
1969 * the bit belongs in when using these macros.
1971 #ifdef __ASSEMBLER__
1972 #define __HV_PTE_ONE 1 /**< One, for assembler */
1974 #define __HV_PTE_ONE 1ULL /**< One, for C */
1977 /** Is this PTE present?
1979 * If this bit is set, this PTE represents a valid translation or level-2
1980 * page table pointer. Otherwise, the page table does not contain a
1981 * translation for the subject virtual pages.
1983 * If this bit is not set, the other bits in the PTE are not
1984 * interpreted by the hypervisor, and may contain any value.
1986 #define HV_PTE_PRESENT (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT)
1988 /** Does this PTE map a page?
1990 * If this bit is set in the level-1 page table, the entry should be
1991 * interpreted as a level-2 page table entry mapping a large page.
1993 * This bit should not be modified by the client while PRESENT is set, as
1994 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
1996 * In a level-2 page table, this bit is ignored and must be zero.
1998 #define HV_PTE_PAGE (__HV_PTE_ONE << HV_PTE_INDEX_PAGE)
2000 /** Is this a global (non-ASID) mapping?
2002 * If this bit is set, the translations established by this PTE will
2003 * not be flushed from the TLB by the hv_flush_asid() service; they
2004 * will be flushed by the hv_flush_page() or hv_flush_pages() services.
2006 * Setting this bit for translations which are identical in all page
2007 * tables (for instance, code and data belonging to a client OS) can
2008 * be very beneficial, as it will reduce the number of TLB misses.
2009 * Note that, while it is not an error which will be detected by the
2010 * hypervisor, it is an extremely bad idea to set this bit for
2011 * translations which are _not_ identical in all page tables.
2013 * This bit should not be modified by the client while PRESENT is set, as
2014 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
2016 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2018 #define HV_PTE_GLOBAL (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL)
2020 /** Is this mapping accessible to users?
2022 * If this bit is set, code running at any PL will be permitted to
2023 * access the virtual addresses mapped by this PTE. Otherwise, only
2024 * code running at PL 1 or above will be allowed to do so.
2026 * This bit should not be modified by the client while PRESENT is set, as
2027 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
2029 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2031 #define HV_PTE_USER (__HV_PTE_ONE << HV_PTE_INDEX_USER)
2033 /** Has this mapping been accessed?
2035 * This bit is set by the hypervisor when the memory described by the
2036 * translation is accessed for the first time. It is never cleared by
2037 * the hypervisor, but may be cleared by the client. After the bit
2038 * has been cleared, subsequent references are not guaranteed to set
2039 * it again until the translation has been flushed from the TLB.
2041 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2043 #define HV_PTE_ACCESSED (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED)
2045 /** Is this mapping dirty?
2047 * This bit is set by the hypervisor when the memory described by the
2048 * translation is written for the first time. It is never cleared by
2049 * the hypervisor, but may be cleared by the client. After the bit
2050 * has been cleared, subsequent references are not guaranteed to set
2051 * it again until the translation has been flushed from the TLB.
2053 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2055 #define HV_PTE_DIRTY (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY)
2057 /** Migrating bit in PTE.
2059 * This bit is guaranteed not to be inspected or modified by the
2060 * hypervisor. The name is indicative of the suggested use by the client
2061 * to tag pages whose L3 cache is being migrated from one cpu to another.
2063 #define HV_PTE_MIGRATING (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING)
2065 /** Client-private bit in PTE.
2067 * This bit is guaranteed not to be inspected or modified by the
2070 #define HV_PTE_CLIENT0 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0)
2072 /** Client-private bit in PTE.
2074 * This bit is guaranteed not to be inspected or modified by the
2077 #define HV_PTE_CLIENT1 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1)
2079 /** Client-private bit in PTE.
2081 * This bit is guaranteed not to be inspected or modified by the
2084 #define HV_PTE_CLIENT2 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT2)
2086 /** Non-coherent (NC) bit in PTE.
2088 * If this bit is set, the mapping that is set up will be non-coherent
2089 * (also known as non-inclusive). This means that changes to the L3
2090 * cache will not cause a local copy to be invalidated. It is generally
2091 * recommended only for read-only mappings.
2093 * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2094 * level-2 page table is accessed.
2096 #define HV_PTE_NC (__HV_PTE_ONE << HV_PTE_INDEX_NC)
2098 /** Is this page prevented from filling the L1$?
2100 * If this bit is set, the page described by the PTE will not be cached
2101 * the local cpu's L1 cache.
2103 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2104 * it is illegal to use this attribute, and may cause client termination.
2106 * In level-1 PTEs, if the Page bit is clear, this bit
2107 * determines how the level-2 page table is accessed.
2109 #define HV_PTE_NO_ALLOC_L1 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1)
2111 /** Is this page prevented from filling the L2$?
2113 * If this bit is set, the page described by the PTE will not be cached
2114 * the local cpu's L2 cache.
2116 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2117 * it is illegal to use this attribute, and may cause client termination.
2119 * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2120 * level-2 page table is accessed.
2122 #define HV_PTE_NO_ALLOC_L2 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2)
2124 /** Is this a priority page?
2126 * If this bit is set, the page described by the PTE will be given
2127 * priority in the cache. Normally this translates into allowing the
2128 * page to use only the "red" half of the cache. The client may wish to
2129 * then use the hv_set_caching service to specify that other pages which
2130 * alias this page will use only the "black" half of the cache.
2132 * If the Cached Priority bit is clear, the hypervisor uses the
2133 * current hv_set_caching() value to choose how to cache the page.
2135 * It is illegal to set the Cached Priority bit if the Non-Cached bit
2136 * is set and the Cached Remotely bit is clear, i.e. if requests to
2137 * the page map directly to memory.
2139 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2141 #define HV_PTE_CACHED_PRIORITY (__HV_PTE_ONE << \
2142 HV_PTE_INDEX_CACHED_PRIORITY)
2144 /** Is this a readable mapping?
2146 * If this bit is set, code will be permitted to read from (e.g.,
2147 * issue load instructions against) the virtual addresses mapped by
2150 * It is illegal for this bit to be clear if the Writable bit is set.
2152 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2154 #define HV_PTE_READABLE (__HV_PTE_ONE << HV_PTE_INDEX_READABLE)
2156 /** Is this a writable mapping?
2158 * If this bit is set, code will be permitted to write to (e.g., issue
2159 * store instructions against) the virtual addresses mapped by this
2162 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2164 #define HV_PTE_WRITABLE (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE)
2166 /** Is this an executable mapping?
2168 * If this bit is set, code will be permitted to execute from
2169 * (e.g., jump to) the virtual addresses mapped by this PTE.
2171 * This bit applies to any processor on the tile, if there are more
2174 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2176 #define HV_PTE_EXECUTABLE (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE)
2178 /** The width of a LOTAR's x or y bitfield. */
2179 #define HV_LOTAR_WIDTH 11
2181 /** Converts an x,y pair to a LOTAR value. */
2182 #define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y)))
2184 /** Extracts the X component of a lotar. */
2185 #define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH)
2187 /** Extracts the Y component of a lotar. */
2188 #define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1))
2190 #ifndef __ASSEMBLER__
2192 /** Define accessor functions for a PTE bit. */
2193 #define _HV_BIT(name, bit) \
2194 static __inline int \
2195 hv_pte_get_##name(HV_PTE pte) \
2197 return (pte.val >> HV_PTE_INDEX_##bit) & 1; \
2200 static __inline HV_PTE \
2201 hv_pte_set_##name(HV_PTE pte) \
2203 pte.val |= 1ULL << HV_PTE_INDEX_##bit; \
2207 static __inline HV_PTE \
2208 hv_pte_clear_##name(HV_PTE pte) \
2210 pte.val &= ~(1ULL << HV_PTE_INDEX_##bit); \
2214 /* Generate accessors to get, set, and clear various PTE flags.
2216 _HV_BIT(present, PRESENT)
2218 _HV_BIT(client0, CLIENT0)
2219 _HV_BIT(client1, CLIENT1)
2220 _HV_BIT(client2, CLIENT2)
2221 _HV_BIT(migrating, MIGRATING)
2223 _HV_BIT(readable, READABLE)
2224 _HV_BIT(writable, WRITABLE)
2225 _HV_BIT(executable, EXECUTABLE)
2226 _HV_BIT(accessed, ACCESSED)
2227 _HV_BIT(dirty, DIRTY)
2228 _HV_BIT(no_alloc_l1, NO_ALLOC_L1)
2229 _HV_BIT(no_alloc_l2, NO_ALLOC_L2)
2230 _HV_BIT(cached_priority, CACHED_PRIORITY)
2231 _HV_BIT(global, GLOBAL)
2236 /** Get the page mode from the PTE.
2238 * This field generally determines whether and how accesses to the page
2239 * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the
2240 * page mode. The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this
2243 static __inline unsigned int
2244 hv_pte_get_mode(const HV_PTE pte)
2246 return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) &
2247 ((1 << HV_PTE_MODE_BITS) - 1);
2250 /** Set the page mode into a PTE. See hv_pte_get_mode. */
2251 static __inline HV_PTE
2252 hv_pte_set_mode(HV_PTE pte, unsigned int val)
2254 pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE);
2255 pte.val |= val << HV_PTE_INDEX_MODE;
2259 /** Get the page frame number from the PTE.
2261 * This field contains the upper bits of the CPA (client physical
2262 * address) of the target page; the complete CPA is this field with
2263 * HV_LOG2_PAGE_TABLE_ALIGN zero bits appended to it.
2265 * For all PTEs in the lowest-level page table, and for all PTEs with
2266 * the Page bit set in all page tables, the CPA must be aligned modulo
2267 * the relevant page size.
2269 static __inline unsigned long
2270 hv_pte_get_ptfn(const HV_PTE pte)
2272 return pte.val >> HV_PTE_INDEX_PTFN;
2275 /** Set the page table frame number into a PTE. See hv_pte_get_ptfn. */
2276 static __inline HV_PTE
2277 hv_pte_set_ptfn(HV_PTE pte, unsigned long val)
2279 pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN);
2280 pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN;
2284 /** Get the client physical address from the PTE. See hv_pte_set_ptfn. */
2285 static __inline HV_PhysAddr
2286 hv_pte_get_pa(const HV_PTE pte)
2288 return (__hv64) hv_pte_get_ptfn(pte) << HV_LOG2_PAGE_TABLE_ALIGN;
2291 /** Set the client physical address into a PTE. See hv_pte_get_ptfn. */
2292 static __inline HV_PTE
2293 hv_pte_set_pa(HV_PTE pte, HV_PhysAddr pa)
2295 return hv_pte_set_ptfn(pte, pa >> HV_LOG2_PAGE_TABLE_ALIGN);
2299 /** Get the remote tile caching this page.
2301 * Specifies the remote tile which is providing the L3 cache for this page.
2303 * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3.
2305 * In level-1 PTEs, if the Page bit is clear, this field determines how the
2306 * level-2 page table is accessed.
2308 static __inline unsigned int
2309 hv_pte_get_lotar(const HV_PTE pte)
2311 unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR;
2313 return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)),
2314 (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) );
2318 /** Set the remote tile caching a page into a PTE. See hv_pte_get_lotar. */
2319 static __inline HV_PTE
2320 hv_pte_set_lotar(HV_PTE pte, unsigned int val)
2322 unsigned int x = HV_LOTAR_X(val);
2323 unsigned int y = HV_LOTAR_Y(val);
2325 pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR);
2326 pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) |
2327 (y << HV_PTE_INDEX_LOTAR);
2331 #endif /* !__ASSEMBLER__ */
2333 /** Converts a client physical address to a ptfn. */
2334 #define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN)
2336 /** Converts a ptfn to a client physical address. */
2337 #define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN)
2339 #if CHIP_VA_WIDTH() > 32
2342 * Note that we currently do not allow customizing the page size
2343 * of the L0 pages, but fix them at 4GB, so we do not use the
2344 * "_HV_xxx" nomenclature for the L0 macros.
2347 /** Log number of HV_PTE entries in L0 page table */
2348 #define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN)
2350 /** Number of HV_PTE entries in L0 page table */
2351 #define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES)
2353 /** Log size of L0 page table in bytes */
2354 #define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES)
2356 /** Size of L0 page table in bytes */
2357 #define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE)
2359 #ifdef __ASSEMBLER__
2361 /** Index in L0 for a specific VA */
2362 #define HV_L0_INDEX(va) \
2363 (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2367 /** Index in L1 for a specific VA */
2368 #define HV_L0_INDEX(va) \
2369 (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2373 #endif /* CHIP_VA_WIDTH() > 32 */
2375 /** Log number of HV_PTE entries in L1 page table */
2376 #define _HV_LOG2_L1_ENTRIES(log2_page_size_large) \
2377 (HV_LOG2_L1_SPAN - log2_page_size_large)
2379 /** Number of HV_PTE entries in L1 page table */
2380 #define _HV_L1_ENTRIES(log2_page_size_large) \
2381 (1 << _HV_LOG2_L1_ENTRIES(log2_page_size_large))
2383 /** Log size of L1 page table in bytes */
2384 #define _HV_LOG2_L1_SIZE(log2_page_size_large) \
2385 (HV_LOG2_PTE_SIZE + _HV_LOG2_L1_ENTRIES(log2_page_size_large))
2387 /** Size of L1 page table in bytes */
2388 #define _HV_L1_SIZE(log2_page_size_large) \
2389 (1 << _HV_LOG2_L1_SIZE(log2_page_size_large))
2391 /** Log number of HV_PTE entries in level-2 page table */
2392 #define _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
2393 (log2_page_size_large - log2_page_size_small)
2395 /** Number of HV_PTE entries in level-2 page table */
2396 #define _HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
2397 (1 << _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
2399 /** Log size of level-2 page table in bytes */
2400 #define _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small) \
2401 (HV_LOG2_PTE_SIZE + \
2402 _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
2404 /** Size of level-2 page table in bytes */
2405 #define _HV_L2_SIZE(log2_page_size_large, log2_page_size_small) \
2406 (1 << _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small))
2408 #ifdef __ASSEMBLER__
2410 #if CHIP_VA_WIDTH() > 32
2412 /** Index in L1 for a specific VA */
2413 #define _HV_L1_INDEX(va, log2_page_size_large) \
2414 (((va) >> log2_page_size_large) & (_HV_L1_ENTRIES(log2_page_size_large) - 1))
2416 #else /* CHIP_VA_WIDTH() > 32 */
2418 /** Index in L1 for a specific VA */
2419 #define _HV_L1_INDEX(va, log2_page_size_large) \
2420 (((va) >> log2_page_size_large))
2422 #endif /* CHIP_VA_WIDTH() > 32 */
2424 /** Index in level-2 page table for a specific VA */
2425 #define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
2426 (((va) >> log2_page_size_small) & \
2427 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
2429 #else /* __ASSEMBLER __ */
2431 #if CHIP_VA_WIDTH() > 32
2433 /** Index in L1 for a specific VA */
2434 #define _HV_L1_INDEX(va, log2_page_size_large) \
2435 (((HV_VirtAddr)(va) >> log2_page_size_large) & \
2436 (_HV_L1_ENTRIES(log2_page_size_large) - 1))
2438 #else /* CHIP_VA_WIDTH() > 32 */
2440 /** Index in L1 for a specific VA */
2441 #define _HV_L1_INDEX(va, log2_page_size_large) \
2442 (((HV_VirtAddr)(va) >> log2_page_size_large))
2444 #endif /* CHIP_VA_WIDTH() > 32 */
2446 /** Index in level-2 page table for a specific VA */
2447 #define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
2448 (((HV_VirtAddr)(va) >> log2_page_size_small) & \
2449 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
2451 #endif /* __ASSEMBLER __ */
2453 /** Position of the PFN field within the PTE (subset of the PTFN). */
2454 #define _HV_PTE_INDEX_PFN(log2_page_size) \
2455 (HV_PTE_INDEX_PTFN + (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2457 /** Length of the PFN field within the PTE (subset of the PTFN). */
2458 #define _HV_PTE_INDEX_PFN_BITS(log2_page_size) \
2459 (HV_PTE_INDEX_PTFN_BITS - (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2461 /** Converts a client physical address to a pfn. */
2462 #define _HV_CPA_TO_PFN(p, log2_page_size) ((p) >> log2_page_size)
2464 /** Converts a pfn to a client physical address. */
2465 #define _HV_PFN_TO_CPA(p, log2_page_size) \
2466 (((HV_PhysAddr)(p)) << log2_page_size)
2468 /** Converts a ptfn to a pfn. */
2469 #define _HV_PTFN_TO_PFN(p, log2_page_size) \
2470 ((p) >> (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2472 /** Converts a pfn to a ptfn. */
2473 #define _HV_PFN_TO_PTFN(p, log2_page_size) \
2474 ((p) << (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2476 #endif /* _HV_HV_H */